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EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 6: Delay Models

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Announcements

Homework #1 posted Due February 25

Project teaming by January 20Title

½ page description

5 references

Project web page – e-mail me the link

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Outline

Last lectureTransistor on-currents and leakage

This lectureDelay modeling

C. Transistor C-V

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MOS Transistor as a Switch

Discharging a capacitor• Can solve:

DS DS DSi i v

DSDS DS

dvi C v

dt

• Prefer using equivalent resistances• Find tpHL

• Find equivalent C, R

+

-

vDSiDS

vGS

,

( )dDS DSpHL

DS GS DS

C v vt

i v v

C

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MOS Capacitances

Gate capacitanceNon-linear channel capacitance

Linear overlap, fringing capacitances

Miller effect on overlap, fringing capacitance

Non-linear drain diffusion capacitancePN junction

Wiring capacitancesLinear

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Gate and Drain CapacitancesGate capacitance

Drain capacitance

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Gate Capacitances

Gate capacitance is non-linearFirst order approximation with CoxWL (CoxL = 1.5fF/m)

Need to find the actual equivalent capacitance by simulating it

Since this is a linear approximation of non-linear function, it is valid only over the certain range

Different capacitances for HL, LH transitions and power computation

Drain capacitance non-linearity compensatesBut this changes with fanout

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D. Gate Delays

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MOS Transistor as a Switch (EECS141)Traversed path

C

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MOS Transistor as a Switch (EECS141)

Solving the integral:

Averaging resistances:

with appropriately calculated Idsat

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CMOS Performance

Propagation delay: LeqnpHL CRt 2ln LeqppLH CRt 2ln

ln2 = 0.7

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0.0E+00

1.0E-04

2.0E-04

3.0E-04

4.0E-04

5.0E-04

6.0E-04

0.2 0.4 0.6 0.8 1.0

VDS[V]

IDS[A]

Switching Trajectory

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Effective Current

Ion(VDD) is never reached

Define Ieff = (IH + IL)/2

IL = IDS(VGS=VDD/2, VDS=VDD); IH=IDS(VGS=VDD, VDS=VDD/2),

Na, IEDM’2002Von Arnim, IEDM’2007

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Effective Current in Stacks

Von Arnim, IEDM’2007

Add linear current, I3

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Calibrating Delays

Accurate delay model needs to incorporate:Slope effects

Non-linear capacitive loading

Signal arrival times

Wire models

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FO4 Inverter Delay

In

tpShapes the input slope to FO4

FO4 load Suppresses Millerkickback

Horowitz, IEEE Micro1/98

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Input Slope Dependence

One way to analyze slope effectPlug non-linear IV into diff. equation and solve…

Simpler, approximate solution:Use VThZ model

From Elad Alon

outout L NMOS PMOS

dVI C I I

dt

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Slope Analysis

For falling edge at output:

For reasonable inputs, can ignore IPMOS

Either Vds is very small, or Vgs is very small

So, output current ramp starts when Vin=VThZ

Could evaluate the integral

Learn more by using an intuitive, graphical approach

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Slope Dependence

Iout ramps linearly for VThZ<Vin<VDD

Constant once Vin =VDD

CL integrates Iout

VThZ<Vin<VDD: Vout quadratic

Vin = VDD: Vout linear

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Slope Dependence (2)

Consider step input whose output crosses VDD/2 at same time

Vout set by charge removed from CL

Need to makeQR = QS

Step has to shift to when Iout=IDSAT/2

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Slope Dependence (3)

To find Δtslope: Find Vin when Iout = IDSAT/2 (Vhalf)

And use input tr

IDSAT α (VDD-VThZ):Vhalf – VThZ = VDD/2 – VThZ/2

Vhalf = (VDD+VThZ)/2

So Δtslope = (VThZ/2)/kr

kr = VDD/(2*tp,in)

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Result Summary

For reasonable input slopes:

For tp,avg, VThZ is (VThZN + VThZP)/2VThZ/VDD typically ~1/3-1/2 at nominal supply

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Model vs. Spice Data

For reasonable input slope

Model matches Spice very well

Model breaks withvery large tr

Input looks “DC” –traces out VTCHave other problems here anyways

Short-circuit current

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E. Standard Cells

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Standard Cell LibraryContains for each cell:

Functional information: cell = a *b * c

Timing information: function of

input slew

intrinsic delay

output capacitance

non-linear models used in tabular approach

Physical footprint (area)

Power characteristics

Wire-load models - function ofBlock size

Fan-out

Library

K. Keutzer, EE244

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Synopsys Delay Models

Linear (CMOS2) delay model

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Example Cell Timing

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Cell Characterization (Linear Model)

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Synopsys Nonlinear Delay Model

Delay is a function of:

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Synopsys Nonlinear Delay Model

F. Static Timing

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33C. Visweswariah, ICCAD’07 tutorial

Setup Timing

LF1 LF2 CFLF3 Comb.

Comb.

Comb.

early clock

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Hold Tests

LF1 LF2 CFLF3 Comb.

Comb.

Comb.

early data

late clock

C. Visweswariah, ICCAD’07 tutorial

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Static Timing Analysis

clk

Combinationallogic

clk

Combinationallogic

clk

Combinationallogic

original circuit

extracted block

Combinationallogic

K. Keutzer, EE244

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Each Combinational Block

Arrival time in green A

C

B

f

2

2

2

1

0

1

0

.20.20

.20

.10

X

YZ

W

.15

.05

.05

.05

Interconnect delay in red

Gate delay in blue

What’s the right mathematical object to use to represent this physical object?

K. Keutzer, EE244

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Problem formulation - 1

C

B

f

X

Y

W

0

.05.1

1

.2

0

0

1

A

.15.20

.20

A

C

B

f

2

2

2

1

0

1

0

.20.20

.20

.10

X

YZ

W

.15

.05

.05

.05

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2

2

Z

Use a labeled directed graph

G = <V,E>

Vertices represent gates, primary inputs and primary outputs

Edges represent wires

Labels represent delays

Now what do we do with this?

K. Keutzer, EE244

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Problem formulation - Arrival Time

Arrival time A(v) for a node v is time when signal arrives at node v

uu

A( ) max (A(u) d )

FI( )

X

Y

A(Z)

Z

x zd

Y zd

A(X)

A(Y)

where d is delay from to andu u, {X,Y}, {Z}. FI(υ) = =

K. Keutzer, EE244

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Static Timing Analysis

Computing critical (longest) and shortest path delayLongest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 1966]

Used in most ASIC designs today

LimitationsFalse paths

Simultaneous arrival times

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False Paths

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Signal Arrival Times

NAND gate:

1

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Signal Arrival Times

NAND gate:

1

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Simultaneous Arrival Times

NAND gate:

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Impact of Arrival Times

A

B

Delay

0 tB - tA

A arrives early B arrives early

Up to 25%

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Next Lecture

Introduction to variability