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EE241 - Spring 2005Advanced Digital Integrated Circuits
Lecture 15:Power Distribution
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Power Distribution
Chapter 24 (Bowhill and Chandrakasan), Design and analysis of Power Distribution Networks by Blauuw, Panda and Chaudhury
S. Lin, N Chang, ISSCC Microprocessor Design Workshop 2001
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Power Distribution
Supply current is brought on chip at specific locations» on the edge for most chips
which are peripherally bonded
» distributed over the area of the chip for area bonded (C4, solder ball) chips
Loads consume this current at different locations on the chip at different times
There is often a large parasitic inductance associated with each bond-wire or solder-ball (0.1-10nH)
Current is distributed from the bond pads to the loads on thin metal wires» 0.04Ω/ typical
Load currents may be very high» average current may be as
large as 20A for very hot chips (50W at 2.5V)
» peak current may be 4-5x this amount (100A!)
L di/dt of bond wire and IR drop across on-chip wires are often a major source of supply noise
From [Dally]
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di/dt Trends
di/dt increases roughly as I*f
P6Pentium® proc
486386286
8086
80858080
800840040.01
0.10
1.00
10.00
100.00
1,000.00
1970 1980 1990 2000 2010Year
Icc
(am
p)
P6Pentium® proc
486386
286
8086
80858080
80084004
1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07
1970 1980 1990 2000 2010Year
L(d
i/dt)
/Vd
d
3
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Power Distribution Network: Simplified
Courtesy of IEEE Press, New York. © 2000
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IR Drop
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Option 1: The “Routed” Power Network (DSP Processor)
Courtesy of IEEE Press, New York. © 2000
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Option 2: The Power Grid
Power grid of PPC 750
Courtesy of IEEE Press, New York. © 2000
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DEC EV4 - 3 Metal Layers3rd “coarse and thick” metal layer added to the
technology for EV4 designPower supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid
90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2
Metal 1
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DEC EV5 - 4 Metal Layers4th “coarse and thick” metal layer added to the
technology for EV5 designPower supplied from four sides of the die
Grid strapping done all in coarse metal
90% of 3rd and 4th metals used for power/clock routing
Metal 3
Metal 2
Metal 1
Metal 4
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2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss
Significantly lowers resistance of gridLowers on-chip inductance
Option 3: Power PlanesDEC EV6 - 6 Metal Layers
Metal 4
Metal 2Metal 1
RP2/Vdd
RP1/Vss
Metal 3
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Power Distribution and Signal Net Inductance
L = k.A
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Reference Plane Example
Simulation Methodology
Extract Inductance & Resistance versus FrequencyModel Skin Effect Both Vertically and Horizontally
Construct Time-Domain SPICE Model and Simulate with SPICEUse FF Devices, High Vdd & Low Temperature to Aggravate Inductive Effects
Substrate
RP2
Metal 4
Metal 3
RP1Metal 2Metal 1
Substrate
RP2
Metal 4
Metal 3
Metal 1Metal 2
⇐ Metal 3 Victims
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Reference Plane Example (continued)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Time (ns)
M3 Victim
M3 Aggressors
M1 Aggressors
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Time (ns)
M3 Victim
M3 Aggressors
M1 Aggressors
RP2 Only RP1 & RP2
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Power Distribution Network Design Methodology
PPC 750Early Analysis(before actual circuit implementation)Assumes uniformcurrent distributionMax drop: 156 mV
Courtesy of IEEE Press, New York. © 2000
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Power Distribution NetworkDesign Methodology
PPC 750After floorplanning.Estimates of currentof each block.Power density uniformover blockMax drop: 172 mV
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Power Distribution NetworkDesign Methodology
PPC 750After layout.RC network extracted.Gates modeled astime-varying current sourcesMax drop: 170 mV
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Power DistributionAnalysis Tools
Source: Cadence
• Requires fast and accurate peak current prediction• Heavily influenced by packaging technology
BeforeBefore AfterAfter
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Dealing with Ldi/dtDecoupling Capacitors
SUPPLY
Boardwiring
Bondingwire
Decouplingcapacitor
CHIPCd
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2
Decoupling capacitors are added: • on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)
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Impact of Bypass Cap
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On-Chip Bypass Capacitors
• Much of the difference between peak and average current may be supplied by local, on-chip bypass (decoupling) capacitors
• Bypass capacitors are also critical in mitigating the effects of the supply bond-wire inductance
• Decoupling is done by all the devices, N-wells, and specific capacitors
• Capacitors need fuses to prevent manufacturing shorts, sizing for limited oscillations.
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3x Reduction in Peak Current
0
0
0.1
0.3
J (A
/mm
2 )
1 2 3t (ns)
Capacitor mustsupply this charge
( )( )( )
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2922
pF/mm26725.0
pC/mm67
pC/mm675.0101A/mm3.03
2
==∆
=
=×⎟⎠⎞
⎜⎝⎛= −
VV
QC
Q
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Decoupling Capacitor Ratios
EV4total effective switching capacitance = 12.5nF
128nF of de-coupling capacitance
de-coupling/switching capacitance ~ 10x
EV513.9nF of switching capacitance
160nF of de-coupling capacitance
EV634nF of effective switching capacitance
320nF of de-coupling capacitance -- not enough!
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EV6 Decoupling Capacitance
Design for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600 MHz0.32-µ F of on-chip de-coupling capacitance was added
Under major busses and around major gridded clock drivers
Occupies 15-20% of die area
1-µ F 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-coupling
160 Vdd/Vss bondwire pairs on the WACC minimize inductance
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EV6 WACC
587 IPGA
MicroprocessorWACC
Heat Slug
389 Signal - 198 VDD/VSS Pins389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
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WACC Assembly
Gieseke, ISSCC’97
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Flip-Chip Solutions
Intel Pentium 4
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Challenge
Resonance frequency of LC power distribution network (f = 1/(2π(LC)0.5)) used to be above clock frequencyBut …
LC of network is going down
Clock frequency going up
Impact of clock gating
Solutions …
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Grid Resonance
Courtesy of IEEE Press, New York. © 2000
Processor with 330MHz Clock
Resonant frequency ofpower network
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PPC750Comparison between R, RC, and RLC analysis
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AC Impedance
IBM POWER 4 FPU
Weekly, EPEP’03
Tantalumselectrolytics
Card ceramics
Module
Chip
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Challenges
Power distribution network become a lot more complex in the presence of “voltage islands”, power domains, and dynamic voltage scaling.
Voltage islands and power domains may require the distribution of multiple supply voltages
Switching modules in and out of the supply network causes transients (variable capacitance and inductance)
Dynamic voltage scaling makes the problem even more pronounced
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A New Perspective on Power DistributionPower Domains:Similar to “clock domains”, but extended to active supply and threshold voltage management and full power-down.
Power source
Active Power NetworkActive Power Network
Load Load Load
Power source
Active Power NetworkActive Power Network
Load Load Load
Power distribution backplane including regulation and conversion using 2.5D integration(distribution network, regulators, decoupling caps)
LocalLocal
voltagevoltage
regulationregulation
High voltage (5V)
distribution
High voltage (5V)
distribution Power distribution diePower distribution die
LocalLocal
voltagevoltage
regulationregulation
High voltage (5V)
distribution
High voltage (5V)
distribution Power distribution diePower distribution die
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A Longer Term Perspective:On chip power generation and conversion networks
Anchor Spring flexure Comb fingers
Energy generation and conversion network
Energy Source 1
Energy Source 2
Conversion
Netw
ork 1
Conversion
Netw
ork 2
Reservoir 1(capacitor)
Reservoir 2(microbattery)
Micro-battery
Electrostatic MEMSvibration converters