EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 1
EE247
Lecture 12
• Data Converters – Data converter testing (continued)
• Measuring DNL & INL– Servo-loop
– Code density testing (histogram testing)
• Dynamic tests– Spectral testing Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of frequency
• Direct Discrete Fourier Transform (DFT) based measurements utilizing sinusoidal signals
• DFT measurements including windowing
• Relationship between: DNL & SNR, INL & SFDR
• Effective number of bits (ENOB)
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 2
Summary
ADC Differential Nonlinearity & Integral Nonlinearity
End-Point
-1 0 1 2 3 4 5 6 7 8
0
1
6
7
Dig
ital
Ou
tpu
t C
od
e
ADC Input Voltage [D]
-1 LSB INL
2
3
4
5
1. Endpoints connected
2. Ideal characteristics derived eliminating offset & full-scale error (same as for DNL)
3. DNL deviation of
code width from D(1LSB)
4. INL deviation of code transition from ideal
+0.5 LSB DNL error
-0.5 LSB DNL error
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 3
How to measure DNL/INL?
• DAC:– Simply apply digital codes and use a good voltmeter to
measure corresponding analog output
• ADC– Not as simple as DAC need to find "decision levels", i.e.
input voltages at all code boundaries
• One way: Adjust voltage source to find exact code trip points "code boundary servo"
• More versatile: Histogram testing
Apply a signal with known amplitude distribution and analyze digital code distribution at ADC output
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 4
Code Boundary Servo
C1
ADC
InputR2
C2
ADC
Under
Test
VREF
i1
i2
Digital
Comp.
A<B
BAB
A
Input
Digital
Code
ADC
Output
fS
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 5
Code Boundary Servo
AD
C D
igit
al O
utp
ut
ADC Analog Input
111
110
101
100
011
010
001
000
D 2D 3D 4D 5D 6D 7D
• i1 and i2 are small, and C1 is large (DV=it/C1), so the ADC analog input moves a small fraction of an LSB (e.g. 0.1LSB) each sampling period
• For a code input of 101, the ADC analog input settles to the code boundary shown
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 6
Code Boundary ServoGood DVM
C1
R2
C2
ADC
VREF
i1
i2
Digital
Comp.
A<B
BAB
A
Input
Digital
Code
ADC
Output
fS
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 7
Code Boundary Servo
• A very good digital voltmeter (DVM)
measures the analog input voltage
corresponding to the desired code boundary
• DVMs have some interesting properties
– They can have very high resolutions (8½ decimal
digit meters are inexpensive)
– To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line
cycles to filter out pickup in the measurement loop
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 8
Code Boundary Servo
• ADCs of all kinds are
notorious for kicking
back high-frequency,
signal-dependent
glitches to their analog
inputs
• A magnified view of an
analog input glitch
follows …
Good DVM
R2
C2
ADC
VREFfS
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 9
Code Boundary Servo
• Just before the input is
sampled and
conversion starts, the
analog input is pretty
quiet
• As the converter begins
to quantize the signal, it
kicks back charge
time0 1/fS
an
alo
g in
pu
t
start of conversion
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 10
Code Boundary Servo
• The difference between
what the ADC
measures and what the
DVM measures is not
ADC INL, it’s error in
the INL measurement
• How do we control this
error?
time0 1/fS
an
alo
g in
pu
t
ADC converts this voltage
DVM measures the average
input including the glitch
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 11
Code Boundary Servo
• A large C2 reduces the
effect of kick-back
• At the expense of longer
measurement time
Good DVM
R2
C2
ADC
VREFfS
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 12
Histogram Testing
• Code boundary measurements are slow – Long testing time
• Histogram testing– Apply input with known pdf (e.g. ramp or sinusoid)
& quantize
– Measure output pdf
– Derive INL and DNL from deviation of measured pdf from expected result
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 13
Histogram Test Setup
Ramp
0
VREF
ADC PC
VREF
• Slow (wrt conversion time) linear ramp applied to ADC
• DNL derived directly from total number of occurrences of each
code @ the output of the ADC
Time
fS
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 14
A/D Histogram Test Using Ramp Signal
Digital Output
Analog
input
Ramp
Time
n.Ts
ADC
Input/Output
Example:
ADC sampling rate:
fs =100kHz Ts=10msec
1LSB =10mV
For 0.01LSB measurement
resolution:
n =100 samples/code
Ramp duration per code:
=100x10msec=1msec
Ramp slope: 10mV/msec
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 15
A/D Histogram Test Using Ramp Signal
Dig
ita
l O
utp
ut
Analog input
Ramp
Tim
e
n/fs
Ideal ADC
Input/OutputExample:
Ramp slope: 10mV/msec
1LSB =10mV
Each ADC code1msec
fs =100kHz Ts=10msec
n =100 samples/code# o
fS
am
ple
sP
er
co
de
DigitalOutput
n
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 16
Ramp Histogram
Example: Ideal 3-Bit ADC
0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
ADC characteristicsideal converter
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
160
180
200
ADC output code
Co
de C
ou
nt
Dig
ital
Ou
tpu
t C
od
e
ADC Input Voltage [D]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 17
Ramp Histogram
Example: Real 3-Bit ADC Including Non-Idealities
0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
ADC characteristicsideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
160
180
200
ADC output code
Co
de C
ou
nt
Dig
ital
Ou
tpu
t C
od
e
ADC Input Voltage [D]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 18
Example: 3 Bit ADC
DNL Extracted from Histogram
1- Remove “Over-range bins”
(0 and full-scale)
2- Compute average count/bin
(600/6=100 in this case)
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
ADC output code
Co
de
Co
un
t, E
nd
bin
s r
em
ov
ed
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 19
Example: 3 Bit ADC
Process of Extracting from Histogram
3- Normalize:
- Divide histogram by
average count/bin
ideal bins have exactly the average count, which, after normalization, would be 1
Non-ideal bins would have a normalized value greater or smaller than 1 0 1 2 3 4 5 6 7
0
0.2
0.4
0.6
0.8
1
1.2
1.4
ADC output code
No
rma
lize
d C
od
e C
ou
nt
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 20
Example: 3 Bit ADC
DNL Extracted from Histogram
4- Subtract 1 from the normalized code count
5- Result DNL (+-0.4LSB in this case)
0 1 2 3 4 5 6 7-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
ADC output code
DN
L =
Co
un
ts / M
ea
n(C
ou
nts
) -1
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 21
Example: 3-Bit ADC
Static Characteristics Extracted from Histogram
• DNL histogram used to reconstruct the exact converter characteristic (having measured only the histogram)
• Width of all codes derived from measured DNL (Code=DNL + 1LSB)
• INL(deviation from a straight line through the end points)- is found
0 1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
ADC Input VoltageD
igit
al O
utp
ut
Reconstructed ADC
Transfer Characteristic
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 22
Example: 3 Bit ADC
DNL & INL Extracted from Histogram
0 1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
ADC characteristics
Ideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
1 2 3 4 5 6-1
-0.5
0
0.5
1
DN
L [L
SB
]
1 2 3 4 5 6
Digital Output Code
INL
[LS
B]
Dig
ital O
utp
ut C
ode
ADC Input Voltage [D]
-1
-0.5
0
0.5
1
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 23
Measuring DNL
• Ramp speed is adjusted to provide large number of output/code - e.g. an average of 100 outputs of each ADC code (for 1/100 LSB resolution)
• Ramp test can be quite slow for high resolution ADCs
• Example:
16bit ADC & 100conversions/code @100kHz sampling rate
(216or 65,536 codes)(100 conversions/code)
100,000 conversions/sec= 65.6 sec
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 24
ADC Histogram Testing
Sinusoidal Inputs
• Ramp signal generators linear to only 8 to10bits & thus only good for testing ADCs <10bit res.
Need to find input signal with better purity for testing higher res. ADCs
• Solution:
Use sinusoidal test signal (may need to filter out harmonics)
• Problem: Ideal ADC histogram
not flat but has “bath-tub shape”
1000 2000 3000 40000
500
1000
ADC Output- Raw Histogram
ADC output code
Co
de C
ou
nt
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 25
ADC Histogram Test Using Sinusoidal Signals
Sinusoid
At sinusoid midpoint crossings:
dv/dt max.
least # of samples
At sinusoid amplitude peaks:
dv/dt min.
highest # of samples
ADC
Input/Output
Dig
ita
l O
utp
ut
Analog input
Tim
e
# o
f
Sa
mp
les
Per
co
de
DigitalOutput
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 26
Histogram Testing
Correction for Sinusoidal PDF
• Is it necessary to know the exact amplitude and offset of sinusoidal input? No!
• References:
– [1] M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic Testing and Diagnostics of A/D Converters,” IEEE Transactions on Circuits and Systems, vol. CAS-33, no. 8, Aug. 1986.
– [2] IEEE Standard 1057
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 27
DNL/INL Extraction Matlab Program
Sinusoidal Histogram
function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN
% dnl and inl ADC output
% input y contains the ADC output
% vector obtained from quantizing a
% sinusoid
% Boris Murmann, Aug 2002
% Bernhard Boser, Sept 2002
% histogram boundaries
minbin=min(y);
maxbin=max(y);
% histogram
h = hist(y, minbin:maxbin);
% cumulative histogram
ch = cumsum(h);
% transition levels found by:
T = -cos(pi*ch/sum(h));
% linearized histogram
hlin = T(2:end) - T(1:end-1);
% truncate at least first and last
% bin, more if input did not clip ADC
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
misscodes = length(find(dnl<-0.99));
% calculate inl
inl= cumsum(dnl);
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 28
Example: Test Results for DNL & INLUsing Sinusoidal Histogram
0 500 1000 1500 2000 2500 3000 3500 4000-1
0
1
code
DN
L [
LS
B]
DNL = +1.3 / -1 LSB, missing code if (DNL<-0.99)
0 500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
code
INL
[L
SB
]
INL = +1.7 / -0.69 LSB
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 29
Example: Matlab ADC Model
DNL/INL Code Test
% converter model
B = 6; % bits
range = 2^(B-1) - 1;
% thresholds (ideal converter)
th = -range:range; % ideal thresholds
th(20) = th(20)+0.7; % error
fs = 1e6;
fx = 494e3 + pi; % try fs/10!
C = round(100 * 2^B / (fs / fx));
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y));
dnl_inl_sin(y);
-30 -20 -10 0 10 20 30-1
-0.5
0
0.5
1
Digital Output
DN
L [
LS
B]
DNL = +0.7 / -0.7 LSB
-30 -20 -10 0 10 20 30
0
0.4
0.8
INL
[L
SB
]
INL = +0.7 LSB
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 30
Histogram Testing Limitations• The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.
• Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.
• Dynamic sparkle codes produce only minor DNL/INL errors
E.g. 123, 123, …, 123, 0, 124, 124, … look at ADC output to
detect
• Noise not detected & averaged out
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution
ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 31
Why Additional Tests/Metrics?
• Static testing does not tell the full story– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?– In principle we can vary fs and fin when performing
histogram tests
– Result of such sweeps is usually not very useful
– Hard to separate error sources, ambiguity
– Typically we use fs=fsNOM and fin << fs/2 for histogram tests
• For additional info regarding higher frequency operation Spectral testing
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 32
DAC Spectural Test or Simulation
• Input sinusoid Need to have significantly better purity compared to DAC linearity
• Spectrum analyzer need to have better linearity than DUT
• Typcally, test performed at several different input signal frequencies
VoutDAC
Spectrum
Analyzer
Sinusoid
Signal
Generator
Clock
Generator
Device Under Test
(DUT)Digital
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 33
Filtering Input to Spectrum Analyzer
Prevent Signal Distortion Incurred by Spec. Analyzer
0 ... f
Notch (Band Reject) Filter
fin
...
...
DAC
Output Signal
Amplitude
Spectrum
Analyzer
Input
Signal
Amplitude
2fin 3fin 4fin
0 ... ffin 2fin 3fin 4fin
1.Measure
fundamental
signal level
2.Notch out
fundamental
signal so that
Spec. Analyzer
input signal
becomes small
enough not to
drive S.A. input
into non-linear
region
3.Measure the
harmonic content
of the DAC output
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 34
Direct ADC Spectral Test via DAC
• Need DAC with much better performance compared to ADC under test
• Beware of DAC output sinx/x frequency shaping
• Good way to "get started"...
Vin Vout Spectrum
Analyzer
Signal
Generator
Clock
Generator
Device Under Test (DUT)
ADC DAC
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 35
Direct ADC-DAC Test
• Issues to beware of:– Linearity of the signal generator output has to be much better than ADC linearity
– Spectrum analyzer nonlinearities
May need to build/purchase filters to address one or both above problems
– Clock generator signal jitter
V in
Spectrum
Analyzer
Signal
Generator
Clock
Generator
Device Under Test (DUT)
Notch
Filter
Bandpass
or
Lowpass
Filter
ADC DAC
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 36
Filtering ADC Input Signal
0 ... f
Signal Generator
Output Signal
Amplitude
Bandpass Filter
fin
...
2fin 3fin 4fin
0 ... f
ADC
Input
Signal
Amplitude
fin
...
2fin 3fin 4fin
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 37
VinPC
Signal
Generator
ClockGenerator
Device Under Test
(DUT)
DataAcquisition
SystemADC
ADC Spectral Test via
Data Acquisition Sytem
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 38
Analyzing ADC Outputs via
Discrete Fourier Transform (DFT)
• Sinusoidal waveform has all its power at one single frequency
• An ideal, infinite resolution ADC would preserve ideal, single tone
spectrum
• DFT used as a vehicle to reveal ADC deviations from ideality
x(t) x(k)
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 39
Discrete Fourier Transform (DFT)
Properties
• DFT of N samples spaced Ts=1/fs seconds:– N frequency bins from DC to fs
– Num of bins N & each bin has width= fs /N
– Bin # m represents frequencies at m * fs /N [Hz]
• DFT frequency resolution:– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a computationally more efficient algorithm named:
– FFT Fast Fourier Transform
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 40
DFT Magnitude Plots
• Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is
redundant to plot Am’s for m >N/2
• Usually magnitudes are plotted on a log scale normalized so that a
full scale sinusoidal waveform with rms value aFS yields a peak bin of
0dBFS:
Am [dBFS] = 20 log10
Am
aFS .N/2
0 fs/2 fs
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 41
Matlab ExampleNormalized DFT
fs = 1e6;
fx = 50e3;
Afs = 1;
N = 100;
% time vector
t = linspace(0, (N-1)/fs, N);
% input signal
y = Afs * cos(2*pi*fx*t);
% spectrum
s = 20 * log10(abs(dft(y)/N/Afs*2));
% drop redundant half
s = s(1:N/2);
% frequency vector (normalized to fs)
f = (0:length(s)-1) / N;
0 0.2 0.4 0.6 0.8 1
x 10-4
-1
-0.5
0
0.5
1
Time
Am
plitu
de
0 0.1 0.2 0.3 0.4 0.5
-300
-200
-100
0
Frequency [ f / fs]
Mag
nit
ud
e
[ d
BF
S ]
fx/fs
Note: Where does the -300dBFS noise
floor come from?
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 42
“Another” Example …
Even though the
input signal is a
pure sinusoidal
waveform note that
the DFT results
does not look like
the spectrum of a
sinusoid …
Seems that the
signal is distributed
among several bins
0 1 2 3 4 5x 10-5
-1
0
1
Time
Sig
nal A
mp
litu
de
0 0.1 0.2 0.3 0.4 0.5-50
-40
-30
-20
-10
Frequency [ f / fs ]
Am
pli
tude
[ d
BF
S ]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 43
DFT Periodicity
• The DFT implicitly assumes that time sample blocks repeat every N samples
• With a non-integer number of signal periods within the observation window, the input yields significant amplitude/phase discontinuity at the block boundary
• This energy spreads into other frequency bins as “spectral leakage”
• Spectral leakage can be eliminated by either
1. Choice of integer number of sinusoids in each block
2. Windowing
-1
-0.5
0
0.5
1
Sig
nal A
mplit
ude
0 0.4 0.8 1.2x 10
-4
-1
-0.5
0
0.5
1
TimeS
ignal A
mplit
ude
Actual Signal
DFT Perceived Signal
0 0.4 0.8 1.2x 10
-4
Time
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 44
Frequency SpectrumInteger # of Cycles versus Non-Integer # of Cycles
0 0.1 0.2 0.3 0.4 0.5-60
-50
-40
-30
-20
-10
Frequency [ f / fs]
Am
plit
ud
e
[ dB
FS
]
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10-4
-1
-0.5
0
0.5
1
Time
Sig
nal A
mplitu
de
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10-4
-1
-0.5
0
0.5
1
Time
Sig
nal
Am
plit
ud
e
0 0.1 0.2 0.3 0.4 0.5-400
-300
-200
-100
0
Frequency [ f / fs]
Am
plit
ud
e
[ dB
FS
]
Integer number of cycles Non-integer number of cycles
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 45
Choice of Number of Cycles & Number of
Samples
To overcome frequency spectrum leakage problem:
– Number of Cycles integer
– N/cycles = fs / fx
non-integer (choose prime # of cycles) otherwise quant. noise periodic and non-random
– Preferable to have N: power of 2 (FFT instead of DFT)
N/cycles = fs / fx=6 integer
-1
-0.5
0
0.5
1
Sig
nal A
mplit
ude
-1
-0.5
0
0.5
1
Sig
nal A
mplit
ude
N/cycles = fs / fx=5.55 non-integer
Time
Time
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 46
Example: Integer Number of Cycles
fs = 1e6;
% Number of cycles in test
cycles = 67;
%Make N/cycles non-integer!
accomplished by choosing cycles prime #
%N=power of 2 speeds up analysis
N = 2^10;
%signal frequency
fx = fs*cycles/N
y = Afs * cos(2*pi*fx*t);
s = 20 * log10(abs(fft(y)/N/Afs*2));Notice: Range of test signals limited to
[( cycles)x fs/N]
0 0.1 0.2 0.3 0.4 0.5-350
-300
-250
-200
-150
-100
-50
0
Frequency [ f / fs ]
Mag
nit
ud
e[
dB
FS
]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 47
Example: Integer Number of Cycles
• Fundamental falls into a single
DFT bin
• Noise (this example numerical
quantization noise) occupies all
other bins
• “integer number of cycles”
constrains signal frequency fx
• Alternative: windowing 0 0.1 0.2 0.3 0.4 0.5
-350
-300
-250
-200
-150
-100
-50
0
Frequency [ f / fs]s ]
Am
plitu
de
[ d
B]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 48
Windowing
• Spectral leakage can be attenuated by “windowing” time samples prior to the DFT– Windows taper smoothly down to zero at the beginning and
the end of the observation window
– Time samples are multiplied by window coefficients on a sample-by-sample basis
Convolution in frequency domain
• Large number choices of various windows – Tradeoff: attenuation versus fundamental signal spreading to
number of adjacent bins
• Window examples: Nuttall versus Hann
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 49
Example: Nuttall Window
20 40 600
0.2
0.4
0.6
0.8
1
Samples
Am
plit
ud
e
Time domain
0 0.2 0.4 0.6 0.8-100
-80
-60
-40
-20
0
20
Normalized Frequency ( rad/sample)
Ma
gn
itu
de
(d
B)
Frequency domain
• Time samples are multiplied by window coefficients on a sample-by-sample basis
• Multiplication in the time domain convolution in the frequency domain
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 50
Windowed Data
• Signal before windowing
• Time samples are multiplied by window coefficients on a sample-by-sample basis
• Signal after windowing
– Windowing removes the discontinuity at block boundaries
0 0.2 0.4 0.6 0.8 1-1
0
1
Time [msec]
Sig
nal A
mp
litu
de
0 0.2 0.4 0.6 0.8 1-2
0
2
Win
do
wed
Sig
nal A
mp
litu
de
Time [msec]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 51
Nuttall Window DFT
• Only first 20 bins shown
• Response attenuated by -120dB
for bins > 5
• Lots of windows to choose from
(go by name of inventor-
Blackman, Harris, Nutall…)
• Various window trade-off
attenuation versus width
(smearing of sinusoids)
2 4 6 8 10 12 14 16 18 20
-120
-100
-80
-60
-40
-20
DFT Bin
No
rmali
zed
Am
pli
tud
e [
dB
]
0
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 52
DFT of Windowed Signal
Spectrum Before/After Windowing
• Windowing results in ~ 100dB attenuation of sidelobes
• Signal energy “smeared” over several (approximately 10) bins
0 0.1 0.2 0.3 0.4 0.5
-60
-20
0
Frequency [ fx / fs]
Sp
ectr
um
no
t W
indo
we
d
[ d
BF
S ]
0 0.1 0.2 0.3 0.4 0.5
-120
-80
-40
0
Win
dow
ed
Sp
ectr
um
[ d
BF
S ]
-40
Before windowing
After windowing
Frequency [ fx / fs]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 53
20 40 600
0.2
0.4
0.6
0.8
1
Samples
Am
plit
ud
eTime domain
0 0.2 0.4-100
-50
0
Normalized Frequency ( rad/sample)
Ma
gn
itu
de
(d
B)
Frequency domain
WindowNuttall versus Hann
Nuttall
Hann
Matlab code:
N=64;
wvtool(nuttallwin(N),hann(N));
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 54
Integer Cycles versus Windowing
• Integer number of cycles– Signal energy for a single sinusoid falls into single DFT bin
– Requires careful choice of fx– Ideal for simulations
– Measurements need to lock fx to fs (PLL)- not always possible
• Windowing– No restrictions on fx no need to have the signal locked to fs Good for measurements w/o having the capability to lock fx to fs or cases where input is not periodic
– Signal energy and its harmonics distributed over several DFT bins –handle smeared-out harmonics with care!
– Requires more samples for a given accuracy
– Note that no windowing is equal to windowing with a rectangular window!
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 55
Example: ADC Spectral Testing
• ADC with B bits
• Full scale input level=2
B = 10;
delta = 2/2^B;
%sampled sinusoid
y = cos(2*pi*fx/fs*[0:N-1]);
%quantize samples to delta=1LSB
y=round(y/delta)*delta;
s = abs(fft(y)/N*2);
f = (0:length(s)-1) / N;
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 56
ADC Output Spectrum
• Input signal bin:
– Bx @ bin # (N * fx /fs + 1)
(Matlab arrays start at 1)
– Asignal = 0dBFS
• What is the SNR?
0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0N=2048
Am
plit
ud
e [d
bF
S]
f /fs
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 57
Simulated ADC Output Spectrum
• Noise bins: all except signal bin
bx = N*fx/fs + 1;
As = 20*log10(s(bx))
%set signal bin to 0
s(bx) = 0;
An = 10*log10(sum(s.^2))
SNR = As - An
• MatlabSNR = 62dB (10 bits)
• Computed SQNR = 6.02xN+1.76dB=61.96dB
Note: In a real circuit including thermal/flicker noise the measured
total noise is the sum of quantization & noise associated with the circuit
0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0
N=2048
Am
plit
ud
e [d
bF
S]
f /fs
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 58
Why is Noise Floor Not @ -62dB ?
• DFT bins act like an analog
spectrum analyzer with
bandwidth per bin of fs /N
• Assuming noise is uniformly
distributed, noise per bin:
(Total noise)/N/2
The DFT noise floor wrt total
noise:
-10log10(N/2) [dB]
below the actual noise floor
• For N=2048:
-10log10(N/2) =-30 [dB]0 0.1 0.2 0.3 0.4 0.5
-120
-40
-20
0
Am
plit
ud
e [d
bF
S]
N=2048
30dB
-100
-80
-60
f /fs
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 59
DFT Plot Annotation
• Need to annotate DFT plot such that actual
noise floor can be readily computed by one of
these 3 ways:
1. Specify how many DFT points (N) are used
2. Shift DFT noise floor by 10log10(N/2) [dB]
3. Normalize to "noise power in 1Hz bandwidth“
then noise is in the form of power spectral
density
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 60
Example:10Bit ADC FFT
• For a real 10bit ADC
spectral test results:
• SNR=55.9dB
• A 3rd harmonic is barely
visible
• Is better view of distortion
component possible?-140
-120
-100
-80
-60
-40
-20
0
Am
plit
ude [ dB
FS
]
N = 4096
SNR = 55.9dB
SDR = 76.4dB
SNDR = 55.1dB
SFDR = 77.3dB
0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / fs]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 61
Example:10Bit ADC FFT
• Increasing N, the number of samples (and hence the measurement or simulation time) distributes the noise over larger # of bins
• Larger # of bins less noise power per bin (total noise stays constant)
• Note the 3rd harmonic is clearly visible when N is increased -150
-100
-50
0
Am
plit
ude [ dB
FS
]
N = 65536
SNR = 55.9dB SDR = 77.9dB
SNDR = 55.2dB SFDR = 78.5dB
0 0.1 0.2 0.3 0.4 0.5Frequency [ f / fs]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 62
Spectral Performance Metrics
ADC Including Non-Idealities
• Signal S
• DC
• Distortion D
• Noise N
• Ideal ADC adds:
– Quantization noise
• Real ADC typically adds:
– Thermal and flicker noise
– Harmonic distortion associated with circuit nonlinearities
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 63
ADC Spectral Performance Metrics
SNR
• Signal S
• DC
• Distortion D
• Noise N
• Signal-to-noise ratioSNR = 10log[(Signal Power) /
(Noise Power)]
• In Matlab: Noise power includes power associated with all bins except:
– DC
– Signal
– Signal harmonics
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 64
ADC Spectral Performance Metrics
SDR & SNDR & SFDR
• SDR Signal-to-distortion ratio= 10log[(Signal Power) /
(Total Distortion Power)]
• SNDR Signal-to-(noise+distortion)
= 10log[S / (N+D)]
• SFDR Spurious-free dynamic range= 10log[(Signal )/
(Largest Harmonic)]
Typically SFDR > SDR
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 65
Harmonic Components
• At multiples of fx
• Aliasing:
– fsignal = fx = 0.18 fs
– f2 = 2 f0 = 0.36 fs
– f3 = 3 f0 = 0.54 fs
0.46 fs
– f4 = 4 f0 = 0.72 fs 0.28 fs
– f5 = 5 f0 = 0.90 fs 0.10 fs
– f6 = 6 f0 = 1.08 fs 0.08 fs
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 66
Relationship INL & SFDR/SNDRADC Transfer Curve
INL Input
Output
Quadratic shaped transfer function:
Gives rise to even order harmonics
Real
INL Input
Output
Cubic shaped transfer function:
Gives rise to odd order harmonics
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 67
Frequency Spectrum versus INL & DNL
-0.03
0
DN
L [L
SB
]
100 200 300 400 500 600 700 800 9001000-2
-1
0
1
2
bin #
INL
[LS
B]
Good DNL and poor INL
suggests distortion
INLNot fully symmetric
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 68
Relationship INL & SFDR/SNDR
• Nature of harmonics depend on "shape" of INL curve
• Rule of Thumb: SFDR 20log(2B/INL)– E.g. 1LSB INL, 10b SFDR60dB
• Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input signal frequency
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 69
SNR Degradation due to DNL
• Uniform quantization error pdf was assumed for ideal quantizer over the range of: +/- D/2
• Let's now add uniform DNL over +/- D/2 and repeat math...
– Joint pdf for two uniform pdfs Triangular shape
[Source: Ion Opris]
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 70
SNR Degradation due to DNL
• To find total noise Integrate triangular pdf:
• Compare to ideal quantizer:
Error associated with DNL reduces overall SNR
6)1(2
2
0
22 D
D
D
dee
ee
3dB
[dB] 25.102.6 NSNR
12
22/
2/
22 D
D
D
D
dee
e[dB] 76.102.6 NSNR
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 71
SNR Degradation due to DNL
• More general case:
– Uniform quantization error (ideal) ±0.5D
– Uniform DNL error ± DNL [LSB]
– Convolution yields trapezoid shaped joint pdf
– SQNR becomes:
312
2
2
2
1
22
2
DNLSQNR
N
D
D
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 72
SNR Degradation due to DNL
• Degradation in dB:
0 0.2 0.4 0.6 0.8 10
2
4
6
8
SNR
Degradation
[dB]
|DNL| [LSB]
312
1
8
1
log1076.1deg_2DNL
SQNRValid only for cases where
no missing codes
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 73
SummaryINL & SFDR - DNL & SNR
INL & SFDR
• Type of distortion depends on
"shape" of INL
• Rule of Thumb:
SFDR 20 log(2B/INL)
– E.g. 1LSB INL, 10b
SFDR60dB
DNL & SNR
Assumptions:
• DNL pdf uniform
• No missing codes
312
2
2
2
1
22
2
DNLSQNR
N
D
D
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 74
Uniform DNL?
• DNL distribution of 12-bit ADC test chip
• Not quite uniform...
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50
50
100
150
200
250
DNL
# o
f o
ccu
rren
ces
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 75
Effective Number of Bits (ENOB)
• Is a 12-Bit converter with 68dB SNDR really a 12-Bit
converter?
• Effective Number of Bits (ENOB) # of bit of an ideal
ADC with the same SQNR as the SNDR of the non-
ideal ADC
Above ADC is a 12bit ADC with ENOB=11bits
Bits0.1102.6
76.168
dB02.6
dB76.1
SNDRENOB
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 76
ENOB
• At best, we get "ideal" ENOB only for
negligible thermal noise, DNL, INL
• Low noise design is costly 4x penalty in
power per (ENOB-) bit or 6dB extra SNDR
• Rule of thumb for good performance /power
tradeoff: ENOB < N-1
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 77
ENOB Survey
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on Selected Areas in Communications, pp. 539-50, April 1999