EE4800 CMOS Digital IC Design & Analysiszhuofeng/EE4800Slides2010Fall/Lecture_05_… · Catalog of...

EE4800 CMOS Digital IC Design & Analysis

Lecture 5 Logic EffortZhuo Feng

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20105.5.11

Outline■ Introduction■ Delay in a Logic Gatey g■ Multistage Logic Networks■ Choosing the Best Number of Stages■ Choosing the Best Number of Stages■ Example■ Summary■ Summary


Introduction■ Chip designers face a bewildering array of choices

►What is the best circuit topology for a function?►What is the best circuit topology for a function?►How many stages of logic give least delay?►How wide should the transistors be?

■ Logical effort is a method to make these decisions►Uses a simple model of delay►Allows back-of-the-envelope calculations►Helps make rapid comparisons between alternatives►Helps make rapid comparisons between alternatives►Emphasizes remarkable symmetries


Delay in a Logic Gatey g■ Express delays in process-independent unit

dabsddτ

=

τ = 3RCτ = 3RC

≈ 12 ps in 180 nm process

40 i 0 6≈ 40 ps in 0.6 μm process


Delay in a Logic Gatey g■ Delay has two components

d f p= +■ Effort delay f = gh (a.k.a. stage effort)

►g: logical effort▼Measures relative ability of gate to deliver current▼g ≡ 1 for inverter

►h: electrical effort = C t / Ci►h: electrical effort Cout / Cin▼Ratio of output to input capacitance▼Sometimes called fanout

P iti d l ■ Parasitic delay p►Represents delay of gate driving no load►Set by internal parasitic capacitance


►Set by internal parasitic capacitance

Delay Plotsyd = f + p

= gh + p I t2-inputNAND= gh + p

elay

: d

InverterNANDg =p =d =

5

6

rmal

ized

De g =

p =d =

d

3

4

Nor

0

1

2

Electrical Ef fort:h = Cout / Cin

0 1 2 3 4 5

0


out in

Delay Plotsyd = f + p

= gh + p I t2-inputNA ND= gh + p

■ What about elay

: d

InverterNA NDg = 4/3p = 2d = (4/3)h +2

5

6

■ What about NOR2?

rmal

ized

De g = 1

p = 1d = h + 1

d (4/3)h 2

Ef f tD l f

3

4

Nor Ef f ort Delay : f

Paras itic Delay: p0

1

2

Electrical Ef fort:h = Cout / Cin

0 1 2 3 4 5

0


out in

Computing Logical Effort■ DEF: Logical effort is the ratio of the input

capacitance of a gate to the input capacitance of p g p pan inverter delivering the same output current.

■ Measure from delay vs. fanout plotsO ti t b ti t i t idth■ Or estimate by counting transistor widths

A2 2 4

A Y A

B

YB

Y1

2

1 1

2

2

4

B1 1 12

Cin = 3 Cin = 4 Cin = 5


ing = 3/3

ing = 4/3

ing = 5/3

Catalog of Gatesg■ Logical effort of common gates

■ In multiples of pinv (≈1)

Gate type Number of inputsyp p

1 2 3 4 n

Inverter 1

NAND 4/3 5/3 6/3 (n+2)/3

NOR 5/3 7/3 9/3 (2n+1)/3

Tristate / mux 2 2 2 2 2

XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8


Example: Ring Oscillatorg■ Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Parasitic Delay: p =Stage Delay: d =Frequency: fosc =


Example: Ring Oscillatorg■ Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1

τ = 3RC

≈ 12 ps in 180 nm processParasitic Delay: p 1Stage Delay: d = 2

F f 1/(2*N*d) 1/4N80abs psd dτ ==

≈ 40 ps in 0.6 μm process

Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6 μm process has frequency of ~ 200 MHz


Example: FO4 Inverter■ Estimate the delay of a fanout-of-4 (FO4) inverter

dd

Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =Stage Delay: d =


Example: FO4 Inverter■ Estimate the delay of a fanout-of-4 (FO4) inverter

dd

Logical Effort: g = 1El t i l Eff t h 4Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay:d = 5

The FO4 delay is about

200 ps in 0.6 μm process

60 ps in a 180 nm processStage Delay:d = 5 60 ps in a 180 nm process

f/3 ns in an f μm process


Multistage Logic Networksg g■ Logical effort generalizes to multistage networks■ Path Logical Effort

■ Path Electrical Effort

iG g= ∏

out-path

in-path

CH

C=

■ Path Effort i i iF f g h= =∏ ∏

10 x y z 201 5/3 4/3 1


g1 = 1h1 = x/10

g2 = 5/3h2 = y/x

g3 = 4/3h3 = z/y

g4 = 1h4 = 20/z

Paths that Branch■ Can we write F = GH?

► No! Consider paths that branch:

G =5

1590

H =GH =h =

1590

h1 =h2 =F = GH?F GH?


Paths that Branch

G = 1G 1H = 90 / 5 = 18GH = 18 5

1590

h1 = (15 +15) / 5 = 6h2 = 90 / 15 = 6

5

1590

F = g1g2h1h2 = 36 = 2GH


Branching Effortg■ Introduce branching effort

► Accounts for branching between stages in pathg g p

on path off pathC Cb

C+

=on pathC

iB b= ∏■ Now we compute the path effort

► F = GBH► F = GBH

ih BH=∏Note:


Multistage Delaysg y■ Path Effort Delay

D f= ∑■ Path Parasitic Delay

F iD f= ∑

P th D l

iP p= ∑■ Path Delay

i FD d D P= = +∑∑


Designing Fast Circuitsg g

i FD d D P= = +∑■ Delay is smallest when each stage bears same

effort

i FD d D P+∑

effort1ˆ N

i if g h F= =

■ Thus minimum delay of N stage path is1ND NF P= +

■ This is a key result of logical effort► Find fastest possible delay


► Doesn’t require calculating gate sizes

Gate Sizes■ How wide should the gates be for least delay?

ˆ outCf gh g out

in

i

C

i out

f gh g

g CC

= =

⇒ =

Working backward apply capacitance

ˆiinCf

⇒ =

■ Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.

■ Check work by verifying input cap spec is met.


Example: 3-stage pathg■ Select gate sizes x and y for least delay from A to B

x

x y45

8 x y45

AB 45


Example: 3-stage pathg

x

x

y

8 x

x

y

45

45

AB

Logical Effort G =

y45B

Logical Effort G = Electrical EffortH =Branching Effort B =Path Effort F =Best Stage EffortParasitic Delay P =

f̂ =


yDelay D =

Example: 3-stage pathgx

y

8 x

x y

y

45A

B

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

y45B

Logical Effort G (4/3) (5/3) (5/3) 100/27Electrical EffortH = 45/8Branching Effort B = 3 * 2 = 6P th Eff t F GBH 125Path Effort F = GBH = 125Best Stage EffortParasitic Delay P = 2 + 3 + 2 = 7

3ˆ 5f F= =


Delay D = 3*5 + 7 = 22 = 4.4 FO4

Example: 3-stage pathg■ Work backward for sizes

y =x =

x

x

y45

8 x y

45

45

AB 45


Example: 3-stage pathg■ Work backward for sizes

y = 45 * (5/3) / 5 = 15y 45 (5/3) / 5 15x = (15*2) * (5/3) / 5 = 10


Best Number of Stagesg■ How many stages should a path use?

► Minimizing number of stages is not always fastestg g y

■ Example: drive 64-bit datapath with unit inverter

1 1 1 1Initial Driver

D =

64 64 64 64Datapath Load

N: 1 2 3 4


N:f:D:

1 2 3 4

Best Number of Stagesg■ How many stages should a path use?

► Minimizing number of stages is not always fastestg g y

■ Example: drive 64-bit datapath with unit inverter1 1 1 1Initial Driver

D = NF1/N + P N(64)1/N N

8 4

16 8

2.8

= N(64)1/N + N 16 8

23

64 64 64 64Datapath Load

N:f:

164

28

34

42.8


D: 65 18 15 15.3Fastest

Derivation■ Consider adding inverters to end of path

► How many give least delay?

( )11

11

N

n

i invi

D NF p N n p=

= + + −∑1 1 1D∂ 1 1 1

ln 0N N Ninv

D F F F pN

∂= − + + =

∂1

■ Define best stage effort

( )1 ln 0invp ρ ρ+ − =

NFρ =

N - n1 Ex tra Inv er tersLogic Bloc k:

n1 Stages


1Path Ef f or t F

Best Stage Effortg■ has no closed-form solution( )1 ln 0invp ρ ρ+ − =

■ Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)■ For pinv = 1, solve numerically for ρ = 3.59


Sensitivity Analysisy y■ How sensitive is delay to using exactly the best

number of stages?■ 2.4 < ρ < 6 gives delay within 15% of optimal

► We can be sloppy!► I like ρ = 4 1.6 1 51ρ

1 0

1.2

1.4

1.151.26

1.51D(

N) /D

(N)

1.0

(ρ =2.4)(ρ=6)

0 0


1.0 2.00.5 1.40.7

N / N

0.0

Example■ Ben Bitdiddle is the memory designer for the Motoroil

68W86, an embedded automotive processor. Help Ben design the decoder for a register filedesign the decoder for a register file.

A[3:0] A[3:0]32 bits

4:

■ Decoder specifications:► 16 word register file► Each word is 32 bits wide

16

16 words

16 Decoder

Register File

► Each word is 32 bits wide► Each bit presents load of 3 unit-sized transistors► True and complementary address inputs A[3:0]► Each input may drive 10 unit-sized transistors► Each input may drive 10 unit-sized transistors

■ Ben needs to decide:► How many stages to use?► How large should each gate be?


► How large should each gate be?► How fast can decoder operate?

Number of Stagesg

■ Decoder effort is mainly electrical and branchingElectrical Effort: H =Branching Effort: B =

■ If we neglect logical effort (assume G = 1)Path Effort: F =Path Effort: F =

Number of Stages: N =Number of Stages: N


Number of Stagesg

■ Decoder effort is mainly electrical and branchingElectrical Effort: H = (32*3) / 10 = 9.6Branching Effort: B = 8

■ If we neglect logical effort (assume G = 1)Path Effort: F = GBH = 76 8Path Effort: F = GBH = 76.8

Number of Stages: N = log4F = 3 1Number of Stages: N log4F 3.1

■ Try a 3-stage design


y g g

Gate Sizes & DelayyLogical Effort: G =Path Effort: F =Stage Effort:Path Delay:

f̂ =D =

Gate sizes: z = y =

A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 1010 10 10 10 10 10 10 10

word[0]

96 units of wordline capacitance

y z


word[15]y z

Gate Sizes & DelayyLogical Effort: G = 1 * 6/3 * 1 = 2Path Effort: F = GBH = 154

1/3ˆStage Effort:Path Delay:G t i 18 6 7

1/3 5.36f F= =ˆ3 1 4 1 22.1D f= + + + =

Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10

word[0]y z word[0]

96 units of wordline capacitance

y z


word[15]y z

Comparison■ Compare many alternatives with a spreadsheet

Design N G P DNAND4-INV 2 2 5 29.8NAND2-NOR2 2 20/9 4 30.1INV-NAND4-INV 3 2 6 22.1NAND4 INV INV INV 4 2 7 21 1NAND4-INV-INV-INV 4 2 7 21.1NAND2-NOR2-INV-INV 4 20/9 6 20.5NAND2-INV-NAND2-INV 4 16/9 6 19.7INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6


Review of Definitions

Term Stage PathTerm Stage Pathnumber of stages

logical effort iG g= ∏N

g

1

electrical effort

branching effort

out-path

in-path

CCH =

iB b= ∏

out

in

CCh =

on-path off-path

on-path

C CCb +=

effort

effort delay

i i d l

F GBH=

F iD f= ∑f gh=

f

parasitic delay

delayiP p= ∑

i FD d D P= = +∑p

d f p= +


Method of Logical Effortg1) Compute path effort2) Estimate best number of stages

F GBH=

4logN F=) g3) Sketch path with N stages4) Estimate least delay

4g

1ND NF P= +

5) Determine best stage effort

Fi d t i

1ˆ Nf F=

ii outg CC =6) Find gate sizes ˆiinC

f=


Limits of Logical Effortg■ Chicken and egg problem

► Need path to compute G► But don’t know number of stages without G

■ Simplistic delay model► N l t i t i ti ff t► Neglects input rise time effects

■ Interconnect► Iteration required in designs with wireq g

■ Maximum speed only► Not minimum area/power for constrained delay


Summaryy■ Logical effort is useful for thinking of delay in

circuits► Numeric logical effort characterizes gates► NANDs are faster than NORs in CMOS► Paths are fastest when effort delays are ~4► Paths are fastest when effort delays are 4► Path delay is weakly sensitive to stages, sizes► But using fewer stages doesn’t mean faster paths

f O► Delay of path is about log4F FO4 inverter delays► Inverters and NAND2 best for driving large caps

■ Provides language for discussing fast circuits■ Provides language for discussing fast circuits► But requires practice to master


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EE4800 CMOS Digital IC Design & Analysiszhuofeng/EE4800Slides2010Fall/Lecture_05_… · Catalog of...

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