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Digital Integrated Circuits © Prentice Hall 2000Interconnect

EECS 141 – F01Lecture 10

Digital Integrated Circuits © Prentice Hall 2000Interconnect

Interconnect

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

The Lumped Model

Vout

Drivercwi re

VinClumped

Rdriver Vout

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The Distributed RC-line

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

Step-response of RC wire as a function of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

volta

ge (

V)

x= L/10

x = L/4

x = L/2

x= L

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RC-Models

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The Elmore DelayRC Chain

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Driving an RC-line

Vin

Rs Vout(rw,cw,L)

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

Design Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> √ tpgate/0.38rc rc delays should only be considered when the

rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC» when not met, the change in the signal is slower

than the propagation delay of the wire

© MJIrwin, PSU, 2000

Digital Integrated Circuits © Prentice Hall 2000Interconnect

INTERCONNECT

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

Inductive Effects in Integrated Circuits

CoaxialCable

TriplateStrip Line

MicroStrip Wire aboveGround Plane

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L di/dt

VDD

L

L

VoutVin

CL

i(t)

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

L di/dt: Simulation

t

t

t

vout

iL

vL

20mA

40mA

5V

0.2V

0.01.02.03.04.05.0

V out

(V)

0

10

20

I L (m

A)

2 4 6 8 10t (nsec)-0.3

-0.1

0.1

0.3

0.5

V L(V

)

tfall = 0.5 nsec

tfall = 4 nsec

Signals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.

The Results of an Actual Simulation are Shown on the Right Side.

Digital Integrated Circuits © Prentice Hall 2000Interconnect

Choosing the Right Pin

Chip

MountingCavity

Lead Frame

Bonding Wire

Pin

L

L’

Make Rise- and Fall Times as slow as possible

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

Decoupling Capacitors

CHIPSUPPLY

BondingWire

BoardWiring

Cd

DecouplingCapacitor

+

-

Digital Integrated Circuits © Prentice Hall 2000Interconnect

Power Distribution Supply current is brought on

chip at specific locations» on the edge for most chips

which are peripherally bonded

» distributed over the area of the chip for area bonded (C4, solder ball) chips

Loads consume this current at different locations on the chip at different times

There is often a large parasitic inductance associated with each bond-wire or solder-ball (0.1-10nH)

Current is distributed from the bond pads to the loads on thin metal wires» 0.04Ω/ typical

Load currents may be very high» average current may be as

large as 20A for very hot chips (50W at 2.5V)

» peak current may be 4-5x this amount (100A!)

L di/dt of bond wire and IR drop across on-chip wires are often a major source of supply noiseFrom [Dally]

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

3x Reduction in Peak Current

0

00.1

0.3

J (A

/mm

2 )

1 2 3t (ns)

Capacitor mustsupply this charge

( )( )( )

22

2922

pF/mm26725.0

pC/mm67

pC/mm675.0101A/mm3.032

==∆

=

=×

= −

VVQC

Q

Digital Integrated Circuits © Prentice Hall 2000Interconnect

De-coupling Capacitor Ratios

EV4 (DEC Alpha 21064, 200MHz)» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x

EV5 (DEC Alpha 21164, 300MHz)» 13.9nF of switching capacitance » 160nF of de-coupling capacitance

EV6 (DEC Alpha 21264, 600MHz)» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough!

Source: B. Herrick (Compaq)

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

EV6 De-coupling Capacitance

Design for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600 MHz» 0.32-µF of on-chip de-coupling capacitance was

added– Under major busses and around major gridded clock drivers– Occupies 15-20% of die area

» 1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-coupling

– 160 Vdd/Vss bondwire pairs on the WACC minimize inductance

Source: B. Herrick (Compaq)

Digital Integrated Circuits © Prentice Hall 2000Interconnect

EV6 WACC

587 IPGA

MicroprocessorWACC

Heat Slug

389 Signal - 198 VDD/VSS Pins389 Signal Bondwires

395 VDD/VSS Bondwires320 VDD/VSS Bondwires

Source: B. Herrick (Compaq)

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

The Transmission Line

Vinr l

c

r l

c

r l

c

r l

c

Voutx

g g g g

The Wave Equation

Digital Integrated Circuits © Prentice Hall 2000Interconnect

Lossless Transmission Line -Parameters

vacuumspeed of light in

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Wave Propagation Speed

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Wave Reflection for Different Terminations

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

Transmission Line Response (RL= ∞)

0.0

1.0

2.0

3.0

4.0

5.0

V

0.0

1.0

2.0

3.0

4.0

V

0.0 5.0 10.0 15.0t (in tlightf)0.0

2.0

4.0

6.0

8.0

V

RS = 5Z0

RS = Z0

RS = Z0/5

(a)

(b)

(c)

VDestVSource

Digital Integrated Circuits © Prentice Hall 2000Interconnect

Lattice Diagram

VSource VDest

0.8333 V

1.6666 V+ 0.8333

+ 0.8333

+ 0.5556

+ 0.5556

+ 0.3704

+ 0.2469

+ 0.3704

+ 0.2469

2.2222 V

3.1482 V

3.7655 V

...

2.7778 V

3.5186 V

4.0124 V

L/ν

t

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Digital Integrated Circuits © Prentice Hall 2000Interconnect

Design Rules of Thumb

Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).

tr (tf) << 2.5 tflight Transmission line effects should only be considered when

the total resistance of the wire is limited:R < 5 Z0

The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance,

R < Z0/2