EEL 3705 / 3705L Digital Logic Design

FAMUFAMU--FSUFSU College of EngineeringCollege of Engineering

EEL 3705 / 3705LEEL 3705 / 3705LDigital Logic DesignDigital Logic Design

Fall 2006Fall 2006Instructor: Dr. Michael FrankInstructor: Dr. Michael Frank

Module #29: Module #29: Supplemental Topics: Supplemental Topics:

Hardware Description LanguagesHardware Description Languages

FAMU-FSU College of Engineering

Why HDLs?Why HDLs? Compared to schematic diagrams or netlist files, they

can be: More standardized & portable. Easier/faster to create. More concise. Easier to comment. Easier to read. Faster to simulate.

And, full manufacturable schematics/layouts can be automatically generated from HDLs by logic synthesis & place-and-route tools.


Hardware Description LanguagesHardware Description Languages VHSIC HDL (VHDL) (IEEE standard 1076)

See Carpinelli §5.4, misc books Verilog HDL (IEEE std. #1364, see web.) Status of “Verilog-VHDL” wars...

Verilog: Most popular, faster sims, better tools, easier to learn, faster to code...

VHDL: More tightly-structured language, higher-level, government standard, required for all defense contracts, widely supported. Verilog:VHDL :: C:Ada ?

Standards bodies Open Verilog International and VHDL International have merged accellera.org


VHDL (VHSIC HDL)VHDL (VHSIC HDL) See “VHSIC Hardware Description

Language", M.R. Shahdad et al, IEEE Computer 18(2):94-103 (Feb. 1985).

IEEE Standard #1076 (1987, revised 1993). Some references:

…


Behavioral vs. Structural ModelsBehavioral vs. Structural Models VHDL is suitable for describing designs using

descriptions mixing different levels of abstraction. Two major types of component models in VHDL:

Behavioral models specify the abstract functional behavior of components, w/o specifying how that behavior is implemented. Can be simulated, but cannot always be automatically synthesized.

Structural models provide an actual implementation, or the outline of an implementation. Can be simulated or synthesized.

VHDL designs can contain a mixture of the two types of models.


Basic Elements of VHDLBasic Elements of VHDL entity – Specifies a HW interface (≈ Java interface)

Think of it as an empty chip package, or as an empty circuit board enclosure, w. I/O ports already installed Comes with a set of named I/O pins of different types

architecture – Implements an interface, as a set of interconnected sub-components. (≈ Java class) Think of a printed circuit board design, or a block diagram of an IC,

with blank boxes for sub-modules component – Template for plugging in sub-components into

an architecture. (≈ interface variable) Like a type of empty chip socket, that can be replicated many times &

placed on a circuit board

continued…


Elements of VHDL, Elements of VHDL, cont.cont. configuration – For a given architecture of an entity,

selects which entity/architecture pairs will be used for each component. ≈ a class constructor that assigns class instances of specific types to the

class’s interface variables Like going through empty sockets of a board, selecting what packaged

chip to use in each one. Only a configuration can actually be simulated.

package – Module, collection of related declarations (components, datatypes, etc.). (≈ Java package)

process – Stateful, concurrently running, event-driven sequences of operations.


VHDL Example: Majority FunctionVHDL Example: Majority Function Goal of this block: Return majority value of 3 inputs. Declaring the interface w. an entity statement:

entity MAJORITY isport (A_IN, B_IN, C_IN : in BIT

F_OUT : out BIT);end MAJORITY;

Instantiating the interface with a behaviorial model, using an architecture specification:architecture LOGIC_SPEC of MAJORITY is

beginF_OUT <= (A_IN and B_IN) or

(A_IN and C_IN) or (B_IN and C_IN) after 4 ns;

end LOGIC_SPEC;


Structural Model for MajorityStructural Model for Majority-- Package decl. in WORK librarypackage LOGIC_GATES iscomponent AND2

port(A,B: in BIT; X:out BIT);end componentcomponent OR3

port(A,B,C:in BIT;X:out BIT);end component

-- Interface to our new guyentity MAJORITY is

port (A_IN, B_IN, C_IN: in BIT F_OUT : out BIT);

end MAJORITY;

-- Body (structural model)-- Uses components declared in-- package LOGIC_GATES in WORK-- library.-- Import entire packageuse WORK.LOGIC_GATES.allarchitecture LOGIC_SPEC of MAJORITY

is-- Declare internal signalssignal AB, AC, BC: BIT;-- Wire together some componentsbeginAND_1: AND2 port map(A_IN,B_IN,AB);AND_2: AND2 port map(A_IN,C_IN,AC);AND_3: AND2 port map(B_IN,C_IN,BC);OR_1: OR3 port map(AB,AC,BC,F_OUT);end LOGIC_SPEC;


Defined Signal TypesDefined Signal Types IEEE standard 9-value logic system, IEEE 1164-1993:

type STD_ULOGIC is (‘U’, -- Uninitialized‘X’, -- Forcing unknown‘0’, -- Forcing 0‘1’, -- Forcing 1‘Z’, -- High impedance‘W’, -- Weak unknown‘L’, -- Weak 0‘H’, -- Weak 1‘-’, -- Don’t care);

To use it:library IEEE;use IEEE.std_logic_1164.all


Verilog HDLVerilog HDL

No slides yet.

VHDL Introduction

(Slides from Dr. Perry)

VHDL Introduction

V- VHSIC Very High Speed Integrated Circuit

H- HardwareD- DescriptionL- Language

VHDL Benefits

1. Public Standard2. Technology and Process Independent

Include technology via libraries3. Supports a variety of design

methodologies1. Behavioral modeling2. Dataflow or RTL (Register Transfer Language)

Modeling3. Structural or gate level modeling

VHDL Benefits (cont)

4. Supports Design Exchange VHDL Code can run on a variety of

systems

5. Supports Design Reuse Code “objects” can be used in

multiple designs6. Supports Design Hierarchy

Design can be implemented as interconnected submodules

VHDL Benefits (cont)7. Supports Synchronous and Asynchronous Designs8. Supports Design Simulation

Functional (unit delay) Timing (“actual” delay)

9. Supports Design Synthesis Hardware implementation of the design obtained

directly from VHDL code.

10. Supports Design Documentation Original purpose for VHDL – Department of Defense

VHDLCODE

a11

a22

3a3

4a4

b1

b2

b3

b4

5

6

7

8

Vcc1

0

GND

0

FPLDVHDL

SynthsizeSoftware

VHDL Design Units

Entity Declaration Describes external view of the design (e.g. I/O)

Architecture Body (AB) Describes internal view of the design

Configuration DeclarationPackage Declaration Library Declaration

Package Body

Architecture Body (AB)

The architecture body contains the internal description of the design entity. The VHDL specification states that a single design entity can contain multiple architecture bodies. Each AB can be used to describe the design using a different level of abstraction.

VHDL Statement Terminator

Each VHDL Statement is terminated using a semicolon

;

VHDL Comment Operator

To include a comment in VHDL, use the comment operator

-- This is a comment -- This is an example of a

comment y <= 0; -- can occur at any point

Signal Assignment Operator

To assign a value to a signal data object in VHDL, we use the

signal assignment operator

<=Example:

y <= ‘1’; -- signal y is assigned the value ONE

Complete AND GATE Example

Library altera;Use altera.maxplus2.all;Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Entity and_example is port(a,b: in std_logic; ya,yb,yc: out std_logic);End entity and_example;Architecture test of and_example is begin --- dataflow model (ya) ya <= a and b; -- structural model (yb)

and2:a_7408 port map(a,b,yb);

-- behavioral model (yc) process(a,b) begin yc <= ‘0’; if((a=‘1’) and (b = ‘1’)) then yc <= ‘1’; else yc <= ‘0’; end if;end process;End architecture test;

AND GATE Example (cont)When synthesized, we obtain the following logic circuit

Ya

Yb

Yc

A

B

Synthesis tool creates three ANDgates.

Maxplus II Block Diagram

VHDL Example - Hardware

It is important to remember that VHDL is a “hardware” language, so you must think and code in “hardware.”Statements within the architecture body run “concurrently.” That is, order does not matter!!! We’ll introduce “sequential” statements

later when I introduce “process blocks”

VHDL Example – Hardware

Example – Logic Circuit

a

b

c

d

Y1

Y2

Y

-- Code Fragment AArchitecture test of example is begin y1 <= a and b; y2 <= c and d; y <= y1 or y2; end architecture test;



a

b

c

d

Y1

Y2

Y

-- Code Fragment BArchitecture test of example is begin y <= y1 or y2; y2 <= c and d; y1 <= a and b; end architecture test;



a

b

c

d

Y1

Y2

Y

-- Code Fragment CArchitecture test of example is begin y2 <= c and d; y <= y1 or y2; y1 <= a and b; end architecture test;

All three code fragments produce the same result

VHDL Syntax

VHDL Syntax – Entity Declaration

Describes I/O of the design. I/O Signals are called ports.

The syntax is:

Entity design_name is

port(signal1,signal2,…..:mode type; signal3,signal4,…..:mode type);

End entity design_name;

VHDL Syntax – Entity Example

Entity my_example is port( a,b,c: in std_logic;

s: in std_logic_vector(1 downto 0); e,f: out std_logic; y: out std_logic_vector(4 downto 0));

end entity my_example;

Maxplus II Block Diagram

Architecture Body Syntax

Architecture name of entity_name is internal signal and constant declarationsBegin Concurrent statement 1;

Concurrent statement 2;Concurrent statement 3;Concurrent statement 4;

End architecture name;

VHDL Program Template

Library altera;Use altera.maxplus2.all;Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;

Entity design_name is port(signal1,signal2,…..:mode

type; signal3,signal4,…..:mode

type);End entity design_name;

Architecture name of entity_name is internal signal and constant declarationsBegin Concurrent statement 1;

Concurrent statement 2;Concurrent statement 3;Concurrent statement 4;

End architecture name;

Simple Concurrent StatementsAssignment Operator

Assignment operator <= Ex: y <= a and b; -- defines a AND gate For simulation purposes only, you may specify a delay.

Ex: y <= a and b after 10 ns; This is useful if you want to also use VHDL to generate a

known test waveform or vector. This is known as a “test bench.” However, we will use Maxplus II to generate test vectors. Note, you cannot specify a delay for synthesis purposes.

VHDLTest Bench

VHDLDesign

OutputVector

Test Vector

Simple Concurrent StatementsLogical Operators

Logical operatorsAnd, or, nand, nor, xor, xnor, not Operates on std_logic or Boolean data objects All operators (except for the not operator)

require at least two arguments

Ex: y <= a and b; -- AND gate

Simple Concurrent StatementsLogical Operators

Logical operators Examples y <= a and not b;

Use parenthesis to define order of execution Ex: y<= (a and b) or c; y <= a and (b or

c);

Y

a

b

c

Y

c

b

a

Complex Concurrent Statementswith-select-when

with-select-whenSyntax is with select_signal select signal_name <= value1 when value1_of_select_sig, value2 when value2_of_select_sig, value3 when value3_of_select_sig, value_default when others;

Complex Concurrent StatementsWith-select-when

Example---- library statements (not shown)

entity my_test is port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);

s: in std_logic_vector(1 downto 0); y: out std_logic_vector(3 downto 0)); end entity my_test;

architecture behavior of my_test is begin with s select

y <= a3 when “11”, a2 when “10”, a1 when “01”, a0 when others; -- default condition end architecture behavior;

Complex Concurrent StatementsWith-select-when

What is the logic expression for y?

What is this in hardware? A 4-bit 4X1 MUX

0 1 0 1 1 0 2 1 0 3 1 0

0,1,2,3n n n n ny a s s a s s a s s a s s

n

A3

Y

S

MuxYMUX

A2

A1

A0

A3

S

A2

A0

A1

VHDL Data Objects

VHDL is an Object Oriented Programming (OOP) Language. Objects can have values, attributes and methods. We will primarily use the following VHDL data objects:

SignalsConstantsVariables

Data ObjectsSignals

SignalsSignals are data objects in which the value of the object can be changed. There is an implied or explicit delay between the signal assignment and when the signal is updated. We will use signals to represent nets (i.e. wires) in our circuits. They can be implemented in hardware. Signals are defined in port statements and architecture declaration blocks.

Data ObjectsConstants

Constants Constants are data objects in which the value of the object cannot be changed. They are defined within an architecture or process declaration block. They cannot be implemented in hardware.

Data ObjectsConstants

Syntax:constant name: type := value;

Example: constant s0: std_logic_vector(1 downto 0):= “01”;

Notes:1. Use a set of single apostrophes to enclose a

single bit (e.g. ‘1’). 2. Use a set of quotations to enclose multiple bits

(e.g. “01”).

Data ObjectsVariables

Variables Variables are data objects in which the value of the object can be changed. This change occurs instantaneously. Variables can only be defined within a process declaration block. They cannot be implemented in hardware.

More about variables later

Sequential StatementsProcess Statements

In VHDL, sequential statements are executed within a process block. Syntax is:

[label:] process (sensitivity list) constant or variable declarations begin sequential statements; end process [label];

The sensitivity list contains all of the inputs to the process block.

Sequential StatementsProcess Statements (cont)

A process block is considered a single concurrent statement. Let’s review our AND example

Sequential StatementsProcess Statements - Example

---- library statementsentity and_example is port(a,b: in std_logic; ya,yb,yc: out std_logic);End entity and_example;Architecture test of and_example

is begin --- dataflow model ya <= a and b;

--- structural model

a_7408 port map(a,b,yb);

-- Process Block process(a,b) begin yc <= ‘0’; if ((a=‘1’) and (b = ‘1’)) then yc <= ‘1’; else yc <= ‘0’; end if; end process;End architecture test;

Sequential StatementsProcess Statements

When synthesized, we obtain the following logic circuit

Ya

Yb

Yc

A

B

The process statement synthesizes into an AND gate just like the dataflow and structural statements.Note, the process block synthesized AND gate “runs” concurrently with the other synthesized AND gates.

Sequential StatementsImplied Registers

Registers

Sequential StatementsImplied RegistersPositive edge triggered D-FF with asynchronous reset

Process (d,clock,reset) begin if (reset = ‘0’) then q <= ‘0’; elsif( clock’event and clock=‘1’) then q <= d; end if; end process;

A clock’event is a 0 to 1 or 1 to 0 transition on the clock line.

In hardware, this becomes

Q

QSET

CLR

D Qn+1D

Clock

Reset


How does this produce a register?1. If reset = 0, q is set to 0 (asynchronous reset)2. If clock line makes a transition from 0 to 1

• Clock’event and clock = 1then q is assigned to d

But, we have not defined an output for1. Reset = 1,2. A non Clock’event , or3. Clock’Event and Clock = 0

So, VHDL assumes we want to retain the current value of q for these conditions and synthesizes a D-FF for us.

Q

QSET

CLR

D Qn+1D

Clock

Reset

Sequential StatementsImplied RegistersWe can easily extend this to a register block by using a std_logic_vector datatype instead of a std_logic datatype.

…….Signal ns,ps:std_logic_vector(7 downto 0);……..Process (ns,clock,reset) begin if (reset = ‘0’) then ps <= “00000000”; elsif( clock’event and clock=‘1’) then ps <= ns; end if; end process;

In hardware, this becomes

REG

ns ps

reset


We can also define a S0 (reset state) and use it to reset the register.…….

Signal ns,ps:std_logic_vector(7 downto 0);Constant S0:std_logic_vector(7 downto 0) := “00000000”;……..Process (ns,clock,reset) begin if (reset = ‘0’) then ps <= s0; --- use ‘reset’ state elsif( clock’event and clock=‘1’) then ps <= ns; end if; end process;

Sequential StatementsCase -When StatementUse a CASE-WHEN statement when priority is not needed. All FSMs will be implemented using Case-when statements.Syntax is:

Case expression is when choice_1 => sequential statements; when choice_2 => sequential statements; …………. when choice_n => sequential statements; when others => -- default condition sequential statements; end case;

VHDL FSM Example 1 2-bit Up Counter

State Diagram

S0

s3

S2

S1

Reset

Y=0

Y=1

Y=2

Y=3

VHDL FSM Example 1

State Table

ps ns y

S0 S1 0

S1 S2 1

S2 S3 2

S3 S0 3

S0 = 00

S1 = 01

S2 = 10

S3 = 11

Let

Let S0 = reset state

Recall Moore FSM

REG

CL

F

CL

H Ypsns

X

clock

reset

Input Vector Output Vector

NextState

PresentState

Feedback Path

Clock

Rese

t

Use a case statement to implement the designsince priority is not needed

VHDL Code - Header Info-------------------------------------------------------------------- Program: fsm1.vhd---- Description: 2-bit up counter. -- -- Author: R.J. Perry-- Date: -- Revisions:----------------------------------------------------------------- Signal I/O------------------------------------------------------------------ Signal name Direction Description-- clock,reset in clock,reset-- count out output

count----------------------------------------------------------------

VHDL Code - Entity Declaration

-- Call Altera and IEEE packageslibrary altera;use altera.maxplus2.all;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

-- define entityentity fsm1 is port ( clk,reset: in std_logic; count: out std_logic_vector(1 downto 0) );end entity fsm1;

VHDL Code - Architecture Dec

-- define architecture

architecture fsm of fsm1 is-- define constants

constant s0: std_logic_vector(1 downto 0) := "00"; constant s1: std_logic_vector(1 downto 0) := "01"; constant s2: std_logic_vector(1 downto 0) := "10"; constant s3: std_logic_vector(1 downto 0) := "11";

signal ns,ps: std_logic_vector(1 downto 0);begin

VHDL Code -- F Logic---- this process executes the F logic-- process ( ps) begin ns <= s0; -- This is the default output case ps is when s0 => ns <= s1; when s1 => ns <= s2; when s2 => ns <= s3; when s3 => ns <= s0; when others => ns <= s0; -- default condition end case; end process;

State Diagram for F Logic

Note: we only need to “describe” the behaviorVHDL will “figure out” the functional relationships

Input into F logic

VHDL Code -- Register Logic

-- -- This process includes the registers

implicitly-- reg: process (clk, reset, ns) begin if(reset = '0') then ps <= s0; elsif (clk'event and clk = '1') then ps <= ns; end if; end process reg;

REG

ns ps

Reset

clk

Inputs to reg logic

VHDL Code -- H Logic---- Use concurrent statement to implement H

Logic--

count <= ps;

end architecture fsm;

ps count

Recall – Gate Level Logic Diagram

Maxplus II “Produces”

Is this correct?

0 0

1 1 0 0 1 1 0

s s

s s s s s s s

n p

n p p p p p p

We have,

OK, same as before

OK, same as before

How does this code fit into our Moore FSM architecture?

T = Toggle FF

T input

System Design Example

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EEL 3705 / 3705L Digital Logic Design

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