EEWeb Pulse - Volume 43

PULSE EEWeb.comIssue 43

April 24, 2012

Dr. Katie HallWiTricity

Electrical Engineering Community

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EEWeb | Electrical Engineering Community Visit www.eeweb.com 3

TABLE O

F CO

NTEN

TSTABLE OF CONTENTS

Dr. Katie Hall 4WITRICITY

Featured Products 9Current Limiting Resistors for LEDs BY DAVIDE ANDREA WITH LI-LON BATTERY MANAGEMENT

Metastability and Clock Uncertainty 17 in FPGA DesignsBY RAY ANDRAKA WITH ANDRAKA CONSULTING GROUP, INC

RTZ - Return to Zero Comic 22

Interview with Dr. Katie Hall - Chief Technology Officer

Tips to avoid asynchronous input errors.

How to accurately calculate the value of current limiting resistors.

11


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WiTricity

fill a core requirement. It dealt with projectiles and introductory optics, and it was so much fun! I’d always been somebody who liked to tinker and put things together, like bicycles and such. The chance to study how things worked in the lab really hooked me. I had a professor there who said, “You know, you’re pretty good at this. Maybe you should think about this as a major.” I think it was the combination of the fact that I liked it and someone telling me I might be decent at it that led me toward my decision. It only took about one more semester for me to realize that I wasn’t going to be a politician—that I was going to major in physics.

Once I made the switch I was completely hooked. I took every chance I had to take classes with labs. Whether it was a class or an internship, I really enjoyed working in the lab. I had a really great professor there, Liz Marshall, whose lab I worked in over the summer. She taught me things I continue to use to this day.

When it came time to graduate, I got very lucky and was offered a job at Bell Labs in New Jersey, to work as a technician in an optical communications lab. I spent three years there learning from such an incredible and intelligent group of guys, which was a great experience. The whole time I was down there, the guys kept asking me, “Why aren’t you in graduate school?” Until then, I hadn’t really thought about it. But then I realized that if I wanted to get to do anything like work on some of the bigger problems or direct some of the work being done—I would have to

Dr.Katie

Dr. Katie Hall - Chief Technology Officer

HallHow did you get into electrical engineering and when did you start?I wouldn’t say that I was especially interested in science as a career

until I went to college. I went to Wellesley College in Wellesley, Massachusetts, with the intention of being a politician, and took a physics class with a lab my first semester to


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go to graduate school. So I returned to Massachusetts, where I’ve spent most of my life and went to graduate school at MIT, studying nonlinear effects in semiconductor diode lasers. It was in the same general field as what I had been working on at Bell Labs—optical devices and semiconductor physics. One of the really nice things about MIT is that we got to focus on a specific problem, which was figuring out some of the mechanisms that limit or enhance the performance of semiconductor lasers.

I think that I, along with a lot of other people who have been fortunate in their careers, have been blessed to work with really great people who not only motivate, but also provide invaluable assistance along the way by sharing knowledge and experience. My graduate advisor, Erich Ippen, was like that. He has been an incredible influence in my life, and is to this day.

When I finished at MIT, I got a job offer to work at Lincoln Laboratory in Bedford, Massachusetts, which is actually part of MIT and is funded primarily by the Department of Defense. Working there was really exciting because they were doing work on optical communications—more specifically optical switching—which took advantage of the nonlinearities that I had been studying in graduate school. It was a great place to work, and was an equally great opportunity for me to step right into some really interesting programs.

I worked at Lincoln Lab for about six years, and one of my colleagues and I had the opportunity to start a company developing optical

networking equipment, so we spun out and started our own company called PhotonEx. It was such a great experience, and it made me realize that I love working at small companies. I didn’t have to deal with the bureaucracy and it kind of felt like we were alone on a raft on an exciting adventure, which I really enjoyed. Since then I’ve pretty much stayed in the world of start-ups and small companies.

I think there is going to come a day when

young kids ask, “Why is it called wireless?”

It will have never occurred to them that there was a wire for any of it originally.

In 2007, I joined WiTricity working on wireless power, which is quite different from the optical communications that I had been working on until then. But some great advice Liz Marshall gave me in college was to always worry a lot more about who I worked with rather than what I worked on. There are so many problems in the world that need solving, you won’t have trouble finding an interesting one. But if you aren’t working with people you really like and respect, the job really won’t be worth working on at all. And now, not only do I love the

people I work with, but I also love the work we are doing. It’s just so exciting, with so many interesting applications.

Why are you so excited about wireless power transfer technology?It’s essentially the last thing to go wireless. I’m looking forward to the day that it becomes fully integrated into our society. I was telling somebody the other day about reading a book to my young kids, and they would ask me a question about it, and then ask the same question again and again. So I’d say to them, “You sound like a broken record.” And they don’t even know what a record is; they’ve had CDs since they were little. Like that, I think there is going to come a day when young kids ask, “Why is it called wireless?” It will have never occurred to them that there was a wire for any of it originally.

Can you tell us more about WiTricity and what it offers?We view ourselves as a technology enabler. For example, we might develop a design for wireless charging of a laptop computer, but we aren’t going to manufacture and sell a laptop. However, we will likely build proof-of-concept systems as well as prototype components or elements of the subsystem that is required to transfer the power. In other cases we consult with a manufacturer, but let them take responsibility for the actual component and product design and manufacture. Several companies have already designed wireless power solutions, and some have come to us to see if we can help


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improve on the efficiency or distance range of their system. So what we offer as a company depends on the demands and needs of our different customers.

We intend to license the technology to companies that want to build products, so that it can be widely adopted and used in a broad range of applications. We have a lot of patents, and are looking forward to the opportunity to work with other people and companies to see all the places the technology may be commercialized.

Are you interested in partnering with others to enhance the technology?Absolutely. We are still a relatively small company, and we are focused on a very specific problem, wireless power transfer. So when we work on technology to wirelessly power vehicles, for example, we team with car manufacturers and Tier One suppliers to improve our reference designs, and to better understand their requirements.

The same goes for other technologies. We enjoy partnering with others to continue to improve and extend the possibilities for wireless power transmission.

What is your role at WiTricity?I am the Chief Technology Officer at WiTricity and I have a number of roles. Early on, I spent a lot of time in the lab, helping to develop and demonstrate proof-of-concept systems and applications. All along I have been involved in building and managing our intellectual property portfolio and also building out our engineering team. As the

company has grown, I have started to spend more time with partners and customers, especially early on in engagements where a team of people come in and want to understand the technology, and how it might impact their products or their market space.

The technology has an incredibly wide range of applications and often, with just a short discussion, we can determine whether or not our wireless power transfer technology is a viable or recommended option. Most often we find that the answer is “Yes,” that there is an advantage to using our technology, whether it’s enabling an application that wasn’t previously possible, or making an existing application more reliable or convenient or green. There is almost never a problem that we can’t address, unless it’s really outside the range of the technology. For example, our technology is really meant to be what we call “mid-range” power transfer. So if you think about it, the transfer is meant to take place within a room or a building or a mid-sized outdoor environment. We’re not trying to wirelessly beam power over kilometers.

What are some of the areas that you are excited to see adopt this technology?There are consumer devices that have already been powered using what we refer to as “traditional induction.” This is what’s used in electric toothbrushes that are placed in a cradle to charge. Also, there are cell phones for which you buy a special back or battery pack that you can place on a pad, which proceeds to charge the device. In some applications, these traditional

induction methods work very well. The reason our technology is different is because it operates over distance; you don’t actually have to put something in a cradle or place it on a pad for it to charge. As I said, in some applications that doesn’t matter, but in other applications it really does. For example, we don’t need to use a pad to wirelessly charge consumer devices. Our power source may be built into another device, such as the base of a lamp or display, or it may be hidden in furniture or behind a wall.

There are a lot of different ways that

power can be moved around, and it’s

really fascinating. I’ve been working on it for years now and I still love coming to work and working

on it every day.

And people don’t have to carefully place their devices in a certain position, they can just put their devices in the general vicinity of a WiTricity source, and their device will start charging. Another example we’re very excited about relates to improving the efficacy of implanted medical devices. Our technology


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provides much more flexibility regarding where implanted medical devices can be placed in the body and how much power they can draw. This application is so important and exciting because it really has the potential to improve people’s lives.

Another place that I think we’ll see our technology—hopefully sooner rather than later—is in electric vehicles. We’ve been able to show wireless recharging of vehicles while they’re parked in a garage or parking space, with no need to plug them in. Here our technology is useful because people are not necessarily such great parkers; they don’t park with pin-point precision. As I said, our technology works over distance, with flexible positioning so it can accommodate less-than-perfect positioning within the parking space, as well as cars with different ground clearances, while still transferring power efficiently. A lot of car manufacturers think that this technology could really

accelerate the adoption of electric vehicles in the market because it would make things so easy for people.

At what distance is this power transfer technology capable?The distance over which power can be efficiently transferred can be described relative to the size of the resonators themselves. So if a resonator is built into a cell phone, the phone can capture wireless power over distances a few times the size of the cell phone. It’s a phenomenon that scales, so if you build a larger resonator into a larger device, such as a tablet computer or a laptop for example, the power can be transferred wirelessly over a larger distance. But that distance between one source and one device is not an ultimate limit because another interesting thing about the technology is that the resonators don’t just have to be in sources that supply power and devices that capture it; you can have what are called repeaters—resonators

that aren’t attached to anything at all but can be used to extend the transmission distance. Some people think of it as if the power or energy is hopping from one resonator to another. Imagine you want to get from one side of a stream to the other side without getting wet, but it’s too far to make it in one jump. You could hop from rock-to-rock to get to the other side without falling in. We have a demo version here, which we show people and they tend to get a kick out of it. We have a source resonator placed against a wall overlapping a traditional outlet, and the carpet tiling in the room has repeater resonators built into it, and we’re able to power lamps all around the room and devices on a coffee table all from that single source against the wall.

There are a lot of different ways that power can be moved around, and it’s really fascinating. I’ve been working on it for years now and I still love coming to work and working on it every day.

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Energy-Measurement Analog Front EndMicrochip Technology Inc., a leading provider of microcontroller, analog and Flash-IP solutions, announced its next-generation energy-measurement analog front end (AFE), the MCP3911, which features two 24-bit, delta-sigma ADCs that operate at 3V with industry-leading accuracy of 94.5 dB SINAD and 106.5 dB THD. This provides better energy-meter and power-monitoring performance by accurately measuring from start-up to maximum current, and enables faster calibration during production. Four different power modes offers the

flexibility of enabling either extremely low-power designs, to 0.8 mA per channel, or designs for higher-speed signals and harmonic content. The extended temperature range allows operation from -40°C to +125°C. The MCP3911 also features 2.7 to 3.6V analog and digital operation, which simplifies the interface by running off of the same power rail as the microcontroller. An internal, low-temperature-coefficient voltage reference, along with PGAs on each channel, further enables metering and monitoring designs. For more information, please click here.

65 GHz Bandwidth OscilloscopeLeCroy Corporation, a leading supplier of oscilloscopes, protocol analyzers and signal integrity test solutions, announced the addition of a 65 GHz oscilloscope module to the LabMaster 10 Zi modular oscilloscope platform and unveiled its roadmap to provide 100 GHz of real-time bandwidth in the LabMaster 10 Zi platform. The top-bandwidth increase to 65 GHz is made possible by outstanding results achieved with LeCroy’s 8HP Silicon Germanium (SiGe) chipsets, which are performing in the laboratory beyond expectations. LeCroy’s 100 GHz real-time oscilloscopes will utilize this advanced chipset and the Company’s patented Digital Bandwidth Interleave™ (DBI) technology,

and will be available in calendar year 2013. LeCroy is currently shipping the world’s fastest real-time oscilloscopes with 45 GHz bandwidth, which are also based on the Company’s patented DBI technology. For more information, please click here.

spin a customer’s 3-phase brushless DC motor. The operation of this system is controllable and viewable across a USB interface using an included Crosshairs-enabled GUI environment that consists of a PC application interface and Crosshairs’ embedded kernel running on the LM3S818 MCU. The LM3S818 MCU provides all of the necessary computational requirements to run TI’s InstaSPIN BLDC technology and other customer-developed applications as well.For more information, please click here.

3-Phase BLDC Motor KitThe Texas Instruments’ Medium Voltage Digital Motor Control Kit for Stellaris® Microcontrollers (DK-LM3S-DRV8312) is a development platform for spinning 3-phase brushless DC (BLDC) motors. The low-cost Stellaris LM3S818 microcontroller (MCU) on the MDL-LM3S818CNCD controlCARD module comes pre-programmed with the necessary firmware in flash memory to run the Texas Instruments’ (TI) InstaSPIN™ BLDC motor control solution out-of-the-box once plugged into the DRV8312 baseboard. The system will automatically detect and

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One of the questions that hobbyists ask over and over is how to select the value of a current limiting resistor for an LED. Usually the seat

of the pants response is: “Subtract 2 V from the supply voltage and divide by 20 mA.” While many feel that answer is good enough, in reality the resulting current will be noticeably different from the calculated value.

LED Current Limiting Resistor

There are 6 situations that people may find themselves in:

1. Given the spec sheet of the LED and desired LED current, find a resistor value.

2. Given the spec sheet of the LED and a resistor value, find the LED current.

3. Given a general type of LED (no specs), and desired LED current, find a resistor value.

4. Given a general type of LED (no specs), and a resistor value, find the LED current.

5. Given an LED in your hands (no specs), and desired LED current, find a resistor value.

6. Given an LED in your hands (no specs), and a resistor value, find the LED current.

For each situation, this is how to proceed.

1. Given the spec sheet of the LED and desired LED current, find a resistor value:

This problem is best solved using a graphic method (analytical methods may be too cumbersome: even with SPICE, you’d have to create an accurate model for the LED).

• Find the “Forward Current vs. Forward Voltage” graph in the LED’s spec sheet.

• Either print it, or copy it to a simple graphic application (such as “Paint”).

• On the LED’s V-I curve, note the LED voltage at the desired current.

• Subtract that voltage from the supply voltage.

• Divide that difference by the desired current, to get the resistor’s value.

CurrentLimitingResistorsfor LEDs

Davide AndreaEngineer


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For example: the resistance analytically. Do note that you need to use the quadratic equation to solve it. Therefore, I maintain that the graphic method is still more convenient.

2. Given the spec sheet of the LED and a resistor value, find the LED current:

Again, this problem is best solved using a graphical method .

• Find the “Forward Current vs. Forward Voltage” graph in the LED’s spec sheet.

• Either print it, or copy it to a simple graphic application (such as “Paint”).

• Extend the horizontal axis, from 0 V to the supply voltage.

• Calculate the current through that resistor if it were connected directly to the supply (no LED): I = supply voltage / resistor value.

• On the vertical axis, at 0 V, mark that current.

• On the horizontal axis, mark the supply voltage.

• Draw a straight line through those two points: that is the “load line” for that resistor and that supply voltage

• Note the point where the load line crosses the LED’s V-I curve: that is the operating point of the LED with that resistor and at that supply voltage.

For example:

The LED’s V-I curve has a logarithmic component due to semiconductor effects, plus a linear component due to ohmic effects. Depending on their relative contribution in a particular LED, the curve will appear more “curvy” or more flat.

If you must use an analytical approach, you may want to approximate the curve of the LED’s V-I characteristics with a straight line. For example:

Figure 1

Figure 2

As long as the desired current is in the area where the straight line is close the V-I curve, then you can calculate

Figure 3

3. Given a general type of LED (no specs), and desired LED current, find a resistor value:

Without specs, you will have to guess the LEDs V-I curve, and then use method 1, above. On a first order of approximation, for a small LED (as opposed to a power LED for illumination), the V-I curve is determined its

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Vled = 2.93V + 13.25 V/A

Use the quadratic equation to solveR = 90Ω

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20 mA

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color.This set of curves is taken from the spec sheets of T-1-3/4 sized, 20 mA LEDs from Lite-On.

Note that the LED voltage increases as the wavelength decreases: for example, an infrared LED has the longest wavelength as well as the lowest voltage. This actually follows from quantum mechanic principles (a photon’s energy is proportional to its frequency).

Note that there are really 3 groups of curves:

• IR

• Red to green

• Blue and white (white LEDs use a UV LED and phosphors)

So, just knowing the color of an LED, and assuming it’s a low current LED, you can use these I-V curves, to estimate a current limiting resistor’s value.

protection), a 1 kOhm pot (variable resistor) and a DVM (Digital VoltMeter) set to measure current, 200 mA full scale.

• Connect that series string to the power supply you’ll use to power that LED.

• Vary the pot until the DVM shows the desired current.

• Disconnect the pot and measure its resistance.

• Select a standard resistor value closest to to that reading (E6 standard: 100, 150, 220, 330, 470, 680, 1K, etc.).

Figure 4

4. Given a general type of LED (no specs), and a resistor value, find the LED current:

Those same curves can be used to estimate the LED current given a resistor value, using the method described in point 2, above.

5. Given an LED in your hands (no specs), and desired LED current, find a resistor value:

If you want to use an LED that you have in your hands, and know little about it, you need to use empirical methods to find the resistor value.

• Connect in series the LED, a 100 Ohm resistor (for

Figure 5

6. Given an LED in your hands (no specs), and a resistor value, find the LED current:

• Connect in series the LED, the resistor and a DVM (Digital VoltMeter) set to measure current, 200 mA full scale.

• Connect them to the power supply you’ll use to power that LED.

• Measure the current.

Temperature and Supply Voltage Effects

Using one of the methods above, you can determine the value of the current limiting resistor, or the resulting current. That is fine at the nominal supply voltage, and at room temperature. But when either one changes significantly, the LED current will change as well. This curve shows how an LED’s voltage changes with temperature; note that at 25 °C, the voltage is 100 %, meaning that is is nominal.

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The worst effect is when the supply voltage is very close to the LED voltage (for example, a 3.0 V supply and a 2.5 V LED voltage); the voltage will change noticeably as the temperature or the supply voltage vary a bit.

As a good designer, you need to consider worst case situation and make sure that the LED will still light up at one extreme and will not be driven too hard at the other extreme (a typical, small LED will be able to handle a maximum of 30 mA continuous current).

LEDs in Series

If you have multiple LEDs that are lit at the same time, it is best to place them in series, so that the same current flows in all of them, inherently. In that case, the LED voltages add-up; so, make sure that the power supply voltage is high enough to power the entire string.

Figure 6

Figure 7

LEDs in Parallel

LEDs should never be connected directly in parallel, because they will not share the current equally. Instead, place a resistor in series with each LED, to set each the current in each individual LED.

Figure 8

Figure 9

LED Driver ICs

Of course, the ideal solution is to drive the LED with a current source. Various ICs are available to drive LEDs (or even a string of them in series) at a constant current. In so doing, the V-I characteristics of the LED become of secondary importance. One of the simplest such ICs is the NSI50010YT1G from ON Semi, a 2-leaded current source that is placed in series with the LED, and regulates the current at 10 mA, regardless of the LED and the supply voltage (the voltage across the IC has to be between 1.8 V and 50 V).

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Many LED driver ICs boost the supply voltage, which is great when you’re operating from a single cell, especially as its voltage starts dropping at the end of its charge.

Determining LED Polarity

While on the subject of LEDs, here is something to watch out for. It is a common belief that you can tell the polarity of an LED by looking at its inner structure: “ the LED chip is mounted on a shelf that is part of the cathode.” Well… maybe. That is true for most, but not all LEDs.

The only 2 ways to determine the polarity of a round, leaded LED by looking at it are:

• The anode lead is longer (assuming they haven’t been cut).

• The round lens body has a flat spot by the cathode lead.

Figure 9

Figure 10

Figure 11 is an example of a board with 5 LEDs, all with the cathode on the left. In the 4 LEDs on the right, the shelf is on the cathode. In the LED on the left (red) the shelf is on the anode. In case of doubt, you can always use a DVM in the DIODE range to see in which direction the LED lights.

Figure 11

About the Author

Davide Andrea is the designer of Li-ion Battery Management Systems for Elithion, and the author of the book “Battery Management Systems for Large Lithium-Ion Battery Packs”.

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Low Power Ambient Light and Proximity Sensor with Internal IR-LED and Digital OutputISL29043The ISL29043 is an integrated ambient and infrared light-to-digital converter with a built-in IR LED and I2C Interface (SMBus Compatible). This device uses two independent ADCs for concurrently measuring ambient light and proximity in parallel. The flexible interrupt scheme is designed for minimal microcontroller utilization.

For ambient light sensor (ALS) data conversions, an ADC converts photodiode current (with a light sensitivity range up to 2000 Lux) in 100ms per sample. The ADC rejects 50Hz/60Hz flicker noise caused by artificial light sources.

For proximity sensor (Prox) data conversions, the built-in driver turns on an internal infrared LED and the proximity sensor ADC converts the reflected IR intensity to digital. This ADC rejects ambient IR noise (such as sunlight) and has a 540μs conversion time.

The ISL29043 provides low power operation of ALS and proximity sensing with a typical 136μA normal operation current (110μA for sensors and internal circuitry, ~28μA for LED) with 220mA current pulses for a net 100μs, repeating every 800ms (or under).

The ISL29043 uses both a hardware pin and software bits to indicate an interrupt event has occurred. An ALS interrupt is defined as a measurement that is outside a set window. A proximity interrupt is defined as a measurement over a threshold limit. The user may also require that both ALS/Prox interrupts occur at once, up to 16 times in a row before activating the interrupt pin.

The ISL29043 is designed to operate from 2.25V to 3.63V over the -40°C to +85°C ambient temperature range. It is packaged in a clear, lead-free 10 Ld ODFN package.

Features• Internal LED + Sensor = Complete Solution

• Works Under All Light Sources Including Sunlight

• Dual ADCs Measure ALS/Prox Concurrently

• <1.0μA Supply Current When Powered Down• Temperature Compensated• Pb-Free (RoHS compliant)

Intelligent and Flexible Interrupts

• Independent ALS/Prox Interrupt Thresholds• Adjustable Interrupt Persistency

- 1/4/8/16 Consecutive Triggers Required Before Interrupt

Applications• Display and Keypad Dimming Adjustment and Proximity

Sensing for:- Mobile Devices: Smart Phone, PDA, GPS- Computing Devices: Laptop PC, Netbook, Tablet PC- Consumer Devices: LCD-TV, Digital Picture Frame, Digital

Camera- Industrial and Medical Light and Proximity Sensing

Related Literature• See AN1436, “Proximity Sensors”

FIGURE 1. TYPICAL APPLICATION DIAGRAM FIGURE 2. PROXIMITY RESPONSE vs DISTANCE

ADDR02

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IRDR 9

ISL29043

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(8-B

IT)

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Ray AndrakaPresident AndrakaConsulting Group Inc.

Metastabilityand ClockUncertaintyin FPGADesigns

Too frequently designs do not properly treat asynchronous inputs, leading to unreliable designs that can be hard to diagnose.

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital design 101 topic, the number of designs I see where these issues are not properly addressed indicates that it is not as well understood in the design community as it should be. Every clocked digital system that accepts input from the outside has an asynchronous input, as do systems with multiple clock domains whenever a signal crosses into a portion of the design clocked by an unrelated clock signal.

Flip-flops in clocked logic are the storage elements in digital logic, and form the basis of sequential logic such as state machines. To guarantee reliable operation, the inputs for a flip-flop must be stable for a minimum time before (setup time, Tsu) and after (hold time, Th) the active clock. The output of the flip flop changes according to

the inputs as a result of the active clock edge a short time after the clock edge occurs (delay bounded by the clock to output time, Tco) provided the setup and hold times were met as shown by the data_in1 and data_out1 signals in Figure 1. If the input violates either the minimum setup or hold times as shown by the signal data_in2, the flip-flop may remain in the previous state, go to the intended next state, or wind up in an unstable in-between state for an indeterminate amount of time before it resolves to one of the two stable states (shown as data_out2) . This last condition is a “metastable state,” which is neither of the two valid stable states (high or low). It may manifest as an oscillation, as an output voltage that is between the defined high and low states, or as an output that looks like a valid output but with an extended clock to output propagation time. It may also cause a “runt pulse” on the output, which is a short-lived pulse that reverts to the original state without another clock event. A metastable state will eventually resolve to one of the two stable states after an indeterminate amount of time with a probability of persisting that is exponential with time. The window of time relative to the clock edge where metastability will actually be triggered is much smaller than the window


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defined by the setup and hold times (on the order of femtoseconds in modern FPGAs), however, it’s exact location is not known and is a function of a number of variables including temperature and voltage. Meeting the setup and hold requirements guarantee a metastable state will not be triggered.

In most cases, a system is not adversely affected if the metastability resolves in time to meet the setup time of the flip-flop(s) fed (possibly through combinatorial logic) by the flip-flop exhibiting the metastable behavior. If it does not, an unknown state is propagated into the system, and a system upset can occur if that causes the value of the signal to be sensed at different logic levels by two or more flip-flops inside the system. When the inputs are synchronized to the clock, it is easy to guarantee the input does not change inside the setup and hold window, which, in turn, guarantees the output will follow the input within a period of time defined by Tco. When the input is asynchronous however, an input transition will eventually happen within that window and will occasionally trigger a metastable state by doing so. Unfortunately, that can’t be avoided, but we can design to minimize the probability of it causing a system upset.

If we define a failure due to metastable behavior as the metastable state lingering long enough to affect operation at the next clock, then the Mean Time Between Failures (MTBF) is generally accepted as:

exponential term. Anything we can do to increase the time allowed for resolution (increasing the sampling interval or decreasing the combined propagation delays and setup time between the metastable flip-flop and the next ones in the system) yields an exponential increase in the circuit’s reliability. Decreasing the input rate or increasing the input sample interval only increases the reliability proportionately. Note that in most systems, the resolution time is a related to the sample interval, although that is not reflected in the equation. The MTBF for a 3ns resolution time with commensurate data and sample intervals is generally in the many millions of years in modern FPGAs. Metastability is very unlikely to be actually encountered in FPGA designs with reasonable clock rates and input data rates. It does, however, need to be considered in designs with high speed inputs and fast clocks to make sure the probability of a metastability induced failure is small enough to be acceptable.

Metastability cannot be eliminated, so we design to reduce the likelihood of a failure to an acceptably low rate (e.g. more than hundred million years MTBF). The most effective way to reduce the probability of failure is to increase the available resolution time. The probability of failure reduces exponentially with increased resolution time, where it only decreases linearly with changes in rates of occurrence of input and sample instants. The resolution time is the slack time between arrival of the signal transition from the synchronizing flip-flop at the destination flip-flop and the arrival of the clock at that flip-flop, less the minimum required setup time.

The resolution time can be increased by using clock enables or a slower clock if the input signal is relatively slow. Note that the setup time to the next flip-flop as well as propagation delays due to routing or logic between the synchronizing flip-flop and the next flip-flop, and the synchronizer’s clock to output delay all subtract from the clock period in calculating the available resolution time. It is vitally important to minimize the routing and logic delays in the path from the synchronizer flip-flop to the next flip-flop regardless of the clock and data rates in order to preserve the resolution time. This is especially important on an FPGA where the routing delays can account for a large percentage of the total propagation delay. In order to do this, it is necessary to put maximum delay constraints on the synchronizer output data paths in an attempt to force the placement and routing to put

MTBF Fd Fc K1(e )K2 T

=) )

)

Where K1 and K2 are constants related to the width of the metastable window and mean time to recovery respectively, Fd is the average rate of change of the input, 1/Fc is input sample interval, which is usually the clock frequency, and T is the time allowed for resolution. K1 and K2 are determined empirically through careful testing of individual flip-flops. Those values are unfortunately not publicized for many FPGAs. There is nothing an FPGA user can do about those constants, as they are determined by factors in the design of the FPGA infrastructure.

Examination of the MBTF equation tells us the parameter with the most effect on reliability is the time allowed for recovery to occur, as it is the only variable within the


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these flip-flops as close together as practical to minimize the length of the routing path. In tools that allow it, it also helps to manually place the flip-flops in adjacent locations with a direct fast routing path available between the locations.

Often the incoming data rate is such that it is not practical to use clock enables or a slower clock to increase the resolution time. In those cases, the solution is to chain together multiple synchronizing flip-flops in order to boost the system reliability as shown in Figure 3. This is almost like pipelining the resolution time. The first synchronizer outputs only to another synchronizer flip-flop, and then the output of the last one in the chain output feeds into the system. The MBTF of each synchronizer flip-flop in the chain is given by the reliability equation above. Chaining them together results in a composite reliability given by:

failures, it is far more likely that you have inadvertently ended up with an asynchronous signal driving more than one flip-flop. Fortunately, this situation is easily avoided by following one simple rule: Never feed an asynchronous input to more than one flip-flop. Never. Synthesis tools will often duplicate logic in a design to improve performance. The designer has to be extra careful to make sure that any synchronizing registers in his design are not duplicated by the synthesis tools, which often means adding attributes to the design source to explicitly prevent duplication of those synchronizing flip-flops.

A related design error occurs when the designer feeds multiple bits into a set of asynchronous inputs as shown in Figure 5. Even though the bits may be synchronous to one another, clocking them into the system on a clock that is asynchronous to the data changes will eventually result in some of the bits arriving before and some after a clock edge due to differences in the delays of the parallel circuits. When multiple bits are transferred into a system with a clock that is asynchronous to the data, additional handshake logic is necessary to ensure data is captured only when all bits are unchanging. That can be done with asynchronous FIFO memories (which just pushes that handshake down a level, hiding it from the designer), or with various data strobe schemes some of which I will address in a future column.

This is the most common way to address reliability, as it is easily retrofitted into a design with only a small hardware cost and a small penalty in signal latency with no changes to the system clocking. The clock should still be the same clock. Attempting to reduce latency by using alternating phases of the clock does not work, because the resolution time of each synchronizer is reduced by half a clock cycle by doing so and you actually end up with a lower reliability than you would have with half the number of synchronizers on the same clock phase due to the smaller resolution time at each synchronizer.

A far more common design error, which I’ll call clock uncertainty, occurs when the designer connects an asynchronous input to more than one flip-flop in the design as shown in Figure 4. No matter how carefully parallel paths are matched, subtle differences in the routing, logic and clock delays or in the set-up or hold times will eventually cause an asynchronous input signal to arrive just in time to be clocked into one flip-flop and be missed until the next clock by another resulting in two different input values being sensed at the same time by different parts of the system. This is often mistaken as a metastability issue because the result is similar, even though no flip-flop ends up in a metastable state. If you are seeing frequent failures that look like metastable

Figure 1: Data in 1 meets the setup and hold requirements, so its output is transferred to its output which appears within the clock to output maximum propagation time, Data_in2 violates the setup time and as a result the output may catch or miss the input, or can go metastable as shown by data out 2. The resolution time for metastability adds to the clock to data valid out time causing a delayed output.

Clock

Tsu Th

Data in 1

Data out 1

Data in 2

Data out 2

T∞

MTBF MTBF1 MTBF2 Fd Fc K1(e )

( )

[k2(T1 T2)]

= =)) )

+


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Figure 5: Synchronization of multiple bits without handshake is bad design practice because bits can arrive on different clock edges due to delay differences. A single bit handshake indicating data is stable is required for reliable transfer of a multi-bit asynchronous signal.

About the Author

Raymond J. Andraka, P.E. earned a B.S.E.E. degree from Lehigh University, Bethlehem, PA, and an M.S.E.E. degree from the University of Massachusetts, Lowell, in 1984 and 1992, respectively. He is the President of the Andraka Consulting Group, Inc., a digital hardware design firm he founded in 1994. His company is focused exclusively on high-performance DSP designs using FPGAs. He has applied FPGAs to signal processing applications including radar processors, radar environment simulators, sonar, Industrial ultrasound, HDTV, digital radio, spectrum analyzers, image processing, and communications test equipment. Ray’s prior signal processor design experience includes five years with Raytheon Missile Systems designing radar signal processors and three years of signal detection and reconstruction algorithm development for the U.S. Air Force. He also spent two years developing image readers and processors for G-Tech, where he set the company time-to-market record for a new product. He has also authored over 20 conference papers and articles dealing with various high-performance FPGA design and signal processing topics, and has been a regular contributor to several on-line forums dealing with FPGA and DSP design.

Figure 2: Synchronizer flip-flop B added at input to system. Minimizing delay between synchronizer flip-flop B and next flip-flop(s), C, in system maximizes metastability recovery time for a given system clock. Ideally there should be no combinatorial logic between B and C, and the routing delay should be minimized by placement and timing constraints.

Source Clock

System Clock

System Input

System Clock DomainSource Clock Domain

AD Q

BD Q

CD Q

Figure 3: Inserting a second synchronizing flip-flop C between synchronizer B and system D increases reliability without having to reduce sample interval

Source Clock

System Clock

System Input


AD Q

BD Q

CD Q

DD Q

Figure 4: Multiple destinations for an asynchronous input is bad design practice because signal transition may be seen slightly before clock on one and slightly after clock on other resulting in a split value.

Source Clock

System Clock

System Clock Domain

Source Clock Domain

AD Q

CD Q

BD Q

System InputCombinatorial

Logic

CombinatorialLogic

Source Clock

System Clock


D Q

D Q

D Q

D Q

System Input

System Input

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