IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 7, JULY 1995 1255

m- SI0 (bulcm'. kV, tUL YIJ.) n+ S/D (hlcm'. kV]

2.4x1Om, Y), 3# 6xlO", 80

Effects of SourceDrain Implants on Short-Channel

3 . 2 x l P . U), d 3x1OU, 16,p Ixl@'. I, p KxlO", 80 Sxl@', 80 SxlO", a0

MOSFET I-V and C-V Characteristics

1.. (A) 94.1 91.7 Dn x IO-L (cm-'eV-') 4 4.4

V?B (VI -0.976 4.00 Nr x lO-" (cm-') 4 4

k. (rml 0 . 4 0.42 AL I&" 0.08 0.09 14 (n) 54.5 ss.6 vrn (V) 0.548 0.178

Cheng-Liang Huang, Member, IEEE, Nadim A. Khalil, Member, IEEE, Narain D. Arora, Senior Member, IEEE, Bjom Zetterlund, Member, IEEE, and Lawrence A. Bair, Member, IEEE

94.7 M.7 5.1 5.1

4.981 4.981 4 4

0.56 0.41 0.M 0.02 a 4 0 l . 6 0.537 0.613

Abstruct- The effects of sourcddrain implants on n-channel MOSFET I-V and C-V characteristics are measured and com- pared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substan- tial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced I>H roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the devicdcircuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations.

I. INTRODUCTION

S device dimensions of advanced CMOS technologies A continue to shrink, obtaining the optimal source/drain im- plant condition for sub-0.5 pm devices becomes increasingly critical. It has been reported [I]-[8] that for short-channel MOSFETs, device I-V and C-V characteristics are sensitive to variations in the source/drain implant and annealing condi- tions. In order to achieve the best device performance and also minimize the hot-carrier effects on short-channel MOSFETs, the proper selection of source/drain processing conditions is of paramount importance, especially when the operating voltage of CMOS devices is not proportionally scaled with device dimensions.

Several approaches [6]-[9] have been suggested to sup- press hot-camer degradation in n-channel MOSFETs. It has been found [6]-[8] that the MOSFET device lifetime can be substantially increased by using a LATID (large-angle- tilt implanted drain) design. The improvement in hot-carrier reliability with the LATID process is attributed mainly to a reduction in the lateral electric field near the drain end.

Because most published data on source/drain engineer- ing have focused primarily on hot-carrier degradation, few reported results [7], [IO] show the effects of source/drain implants on short-channel device performance. In this work the impact of source/drain design on sub-0.5 pm MOSFET I- V and C-V characteristics is examined. In order to understand the effects of process differences on device characteristics, measured results are analyzed in terms of implant conditions

Manuscript received January 19, 1994; revised October 31, 1994. The

The authors are with the Digital Equipment Corporation, Hudson, MA

IEEE Log Number 941 1408.

review of this paper was arranged by Associate Editor D. A. Antoniadis.

01749 USA.

for the source/drain regions. In addition, experimental data and two-dimensional numerical simulations that include I- V characteristics, intrinsic gate capacitances, and overlap capacitances are compared using both the effective channel length (L,tf) and the polysilicon gate length (Lpoly). We note that a distinction between L,E and Lpoly is necessary, especially for sub-0.5 pm devices.

11. DEVICE FABRICATION AND EXPERIMENT

The MOS transistors used in this study were fabricated using a retrograde n-well, salicided dual-gate CMOS process. The p-type starting material had a 5 pm thick, 30 ohm-cm epitax- ial layer on a 0.08 ohm-cm substrate. After shallow trench isolation and n-well formation the gate dielectric was furnace grown in pure 0 2 ambient to a thickness of approximately 9.54. The polysilicon gate was doped by the source/drain implant. A 2-minute rapid thermal anneal (RTA) at T = 975°C was used to insure proper activation of the polysilicon gate while maintaining shallow source/drain junctions. A CoSi2 salicide process was used to form low resistivity gates, sources and drains. All the MOSFETs have a drawn gate width of W = 64 pm with drawn gate lengths ranging from L = 64 pm to 0.375pm. Table I shows the key processing conditions and extracted parameter values. Scanning Electron Microscope (SEM) measurements indicate that the oxide spacer width for all devices investigated in this work is relatively long spacer (L , "N 0.15 pm.) Note that the only differences in the processing conditions for devices A through C are the tilt angle and the implant dose/energy for the 71- source/drain regions. Devices C and D are LDD devices that differ only in the polysilicon gate length (Lpoly).

The oxide thicknesses (tax) (see Table I) and the substrate impurity concentrations were determined by high frequency

0018-9383/95$04,00 0 1995 IEEE

1256 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42. NO. 7, JULY 1995

I I I I

-0.15 -0.05 0.05 0.15 0.25 0.35

X-coordinate (Fm)

Fig. 1. Extracted one-sided sourcddrain and channel profiles at SiO;?/Si interface (device A-solid line, device B-short dashed line, devices C and D-long-short dashed line). The insert shows a schematic diagram of half of a ?,-channel MOSFET.

C-V measurements [ 111 using a large area MOS capacitor (200pmx 200pm). The experimental data show that varia- tions in t, and substrate impurity concentrations are small for the devices used in this study. The extracted sourceldrain and channel profiles for several implant conditions are given in Fig. 1. The detailed description of this profile extrac- tion procedure is reported elsewhere [12], [13]. We note, however, that compared to other techniques (Secondary Ion Mass Spectroscopy (SIMS) and Spreading Resistance Profiling (SRP)), this new method requires no sample preparation, is nondestructive in nature and can be applied to shallow junction devices. Fig. 1 and Table I show that as the implant angle/dose increases, the lateral diffusion length ( L d i ~ ) also increases. Consequently, the A L (= Lpoly - L,K) values for devices A and B are expected to be larger than devices C and D.

The density of interface states (DJ determined from high- low frequency C-V measurements [111 shows no signifi- cant differences between devices. The experimental flat-band voltage (1%~) and the polysilicon concentration ( N p ) were obtained by comparing the experimental C-V data with a one-dimensional solution of Poisson's equation that takes into account the polysilicon depletion effect and the nonuniform doping profile in the silicon substrate [ 5 ] .

The polysilicon gate length (Lpoiy) was determined by adjusting Lpoly in MINIMOS [14], [15] to get the best agreement between simulated (lines) and measured (symbols) gate-to-channel (Cgc) capacitances in the inversion regime (see Fig. 2). We note that in addition to obtaining Lp+ for the various devices used in this study, the accuracy of the doping profiles given in Fig. 1 is also verified by reasonably good agreement between the measured and simulated bias- dependent overlap capacitances (see Fig. 2). A significant increase in the bias-dependent overlap capacitance for the LATID processes is clearly seen in both devices A and B (long dashed line and long-short dashed line) at VGS 5 the

1201 I I 1

01 I I I -3.0 -1.0 1 .o 3 .O

V,, - V,, (VOLTS)

Fig. 2. Comparison of gate-to-channel capacitance as a function of V ~ S - VTH for device A-long dashed line and open squares, device B-long-short dashed line and solid squares, device C-short dashed line and solid dots, and device &solid line and open circles. Lines represent the MINIMOS simulations while symbols indicate experimental data.

threshold voltage VTH. Note that since the to, and N p values are the same for devices A through D, the C$, differences in the inversion region are due mainly to LI,<>ly variations. Once Lpoly is obtained, one can further verify [ 161 that as the implant angle/dose increases A L (or I&) is indeed increased. Table I shows that the Lpoly difference between devices A, B and D is only 0.01 pm while values of effective channel length L,R (= Lpoly - A L ) are almost identical (0.33pmf 0.01pm) for devices A, B and C.

All experimental I-V and C-V characteristics presented in this work were obtained using an HP4145B Parameter Analyzer and an HP 4275A LCR meter. The measurement frequency of the HP 4275A LCR meter was set to 100 kHz. The resolution of the system is approximately 0.1 fF. In order to reduce the noise level in the measured results, the experimental C-V data for sub-0.5 pm devices were averaged over several measurements. As a result, the actual resolution of the experimental data is better than 0.1 fF. The experimental setup for the gate capacitance measurements (gate-to-drain and gate-to-source capacitances) is identical to those published in [17] and [IS].

111. RESULTS AND DISCUSSION

The relative importance of the overlap capacitance com- pared to the intrinsic gate capacitance is significantly in- creased as device sizes decrease. In order to reduce the effect of the gate capacitance on overall circuit performance, the source/drain implant conditions for sub-0.5 pm CMOS devices need to be carefully chosen to ensure minimum overlap capacitances. In this section, the effects of the LATID design on the intrinsic and overlap capacitances are examined. The dc characteristics of various source/drain profiles are also presented to help understand the impact of implant conditions on circuit performance.

HUANG et al.: EFFECTS OF SOURCEDRAIN IMPLANTS ON SHORT-CHANNEL MOSFET

40-

20

1251

-

h

% U

U-

.....*....r..

i . o ; .T oooooooooo ooooooooooooooc 1 0

lo

wn = 64 p m . 5 pm

v,=ov

-2.0 -1.0 0.0 1.0 2.0 3.0 VGs - V, (VOLTS)

Fig. 3 . Comparison of C,, capacitance as a function of I C s - b + ~ in the linear and saturation regions. (device A-dashed lines, device B-solid dots and device C-open circles.)

80

60

4c E ”%

2a

(I

W L = 64 pm10.5 bm v,=3v

-2.0 -1.0 0.0 1.0 2.0 3 VGs - V m (VOLTS)

Fig. 4. Comparison of C,, capacitance as a function of 1hs - ti.^ in the linear and saturation regions. (device A-dashed lines, device B-solid dots and device C-apen circles.)

A. Effect of Source/Drain Implant on AC Characteristics In Fig. 3 we compare the experimental gate-to-drain ( C g d )

capacitances for devices A through C. It is found that for a given L,R (-0.33pm) the LATID devices (solid dots and dashed lines) have approximately 10-20% larger gate capacitance than the LDD devices (open circles) in both the “off” state (VGS = VDS = 0 V) and the “on” state (VGS = VDS = 3 V). Similar percentage differences in Cg, capacitance between the LATID and LDD devices are shown in Fig. 4. As expected, the effect of the source/drain implants on the intrinsic gate capacitances for various devices is insignificant; this is in strong contrast to the bias-dependent overlap capacitance.

To demonstrate further the marked increase in the bias- dependent overlap capacitance for LATID devices, Fig. 5 shows a comparison of C,, capacitances in the accumulation region. Note that for devices operated in this regime, the gate

W=64pl

0.0 1 .o 2.0 3.0 VDs (VOLTS)

Fig. 5. Comparison of Cgd capacitance as a function of t,bs in the accumulation region. (device A 4 a s h e d lines, device B-solid dots, device C-pen circles and device D-solid lines.)

capacitance is dominated mainly by the overlap capacitance. Also note that for V i s near the flat-band voltage VFB (--1 V), the LATID devices (solid dots and dashed lines) have substantially larger gate capacitance than the LDD devices (open circles and solid lines). The differences in gate capaci- tance between the LATID and LDD devices are reduced with increasing VDS and decreasing VGS.

To show that the relative increase in C,, and C,,d for LATID devices can be significant, especially for sub-0.5 pm devices, Fig. 6 presents MINIMOS simulations of gate capacitance for the various profiles given in Fig. 1. It has been noted [I31 that it is imperative to reduce the overlap capacitance as device dimensions are reduced. Fig. 6 shows, however, a substantial increase in C,, and Cgd for the LATID devices at VGS-VTH = VDS = 3 V, that is contrary to high performance device and circuit design practice. The relative increase in C,, becomes more pronounced as the device size decreases, while the difference in C g d between LATID and LDD devices remains more or less constant. This is due primarily to the reduction in the intrinsic gate capacitance component of C,, as L,ff decreases, while the overlap capacitance component of c g d remains almost constant.

B. Effect of Source/Drain Implant on DC Charucteristics

Since the main purpose of the LATID design for n-channel MOSFETs is to show the improvement in device reliability, Fig. 7 gives the maximum substrate current, Jbrrlax, for the various profiles investigated in this work. It is found that the

values for the LATID devices (solid dots and open circles) are approximately 2-3 times smaller than for the LDD devices at L,ff zz 0.25~111. These results are consistent with most published data [6]-[8]. In addition, we also note that devices A and B (both are LATID) have very similar I,,,,. Due to variations in Ldiff (see Fig. I ) , the locations of the damaged area [ 191 created under channel-hot-carrier stress might be different for devices A and B; thus, the lifetime of these two devices is not necessarily the same.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 7, JULY 1995

2.0 I I I 1.5

vGs- v, = vm= 3 \I

1 .o 1 I I .0.5 0.1 0.6 1.1 1.6 2.1

Lefi (PI 0.0 02 0.4 0.6 0.8 1.0

Eeff (MV/cm) Comparison of relative Cgd and C,, increase for devices A and

(LDD) as a function of L e E , <both are LAnD) with respect to device Fig. 8. Comparison of effective channel mobility as a function of effective vertical field for device A-solid line, device B-solid dots and devices C and D--open circles. (dashed l inedev ice Ndevice C, solid l inedev ice B/device C).

W = 6 4 p l vm=4v

3 0 1 T=2OoC

*O t

35 5 w n = 64jlmfQ.5 pn

3ot VGS - v, = 3 v

25

20

15

10

5

0 0.0 1 .o 2.0 3.0 4.0

V,, (VOLTS)

Fig, 7, Comparison of peak substrate current at vD'us = dots, device B--open circles and devices

,, for device Fig. 9. Comparison of I-V characteristics in the linear and saturation regions for device A-dashed lines, device B-solid dots, device C-open circles and device D-solid lines. and D--open

It is well known 1201, [21] that the drain current IDS is determined mainly by L,E:

IDS = pWeffCOx(V~s - VTH - ~ ~ V D S ) . vDS/(Leff + vDS/Ec). (1)

For devices A, B and C one would expect that the IDS values for these three devices would be very similar, given that the effective channel mobility p (see Fig. 8) [18], Weff and Cox are almost the same. In ( I ) , E, is the critical field at which the carrier velocity saturates and a = 1 + yS, where y is the body factor, S = 0 . 5 / . , / m , + f is the bulk potential, and V ~ S is the substrate bias. Fig. 9 shows a comparison of the experimental I-V data for devices A through D. The IDS differences for devices A through C (symbols and dashed lines), which have almost identical L,E, are negligible. This, however, is no longer true for device D (solid lines), which

has almost the same Lpoly as devices A and B but a much longer L,R. The estimated reduction in IDS for device D is approximately 10% compared to devices A through C. These results clearly show that for a given Lpolyr LATID devices (solid dots and dashed lines) have significantly larger IDS than LDD devices (solid lines).

To further support the statement given above, MINIMOS simulations of IDSAT for the various profiles shown in Fig. 1 are also presented (see Fig. 10). Note that for a given Leff and biases, the variations in IDSAT for these three profiles (upper 3 curves) are small, even for L,ff = 0.25pm. This, however, is no longer true when one plots IDSAT versus Lpoly (lower 3 curves). Also note that as a result of the extended overlap between the gate and source/drain regions for the LATID devices (see Fig. l), the threshold voltage roll-off (see Fig. 11) becomes more pronounced for the LATID devices (solid line and long-short dashed line) at a given Lpoly.

HUANG ct al.: EFFECTS OF SOURCWDRAIN IMPLANTS ON SHORT-CHANNEL MOSFET 1259

1/L,ff (w-9 1 .o 2 .o 3.0 4.0 I I I 150

0.0 40)

A 1 v, - v, = v, = 3 v

I 1 J io 0.0 1 .o 2.0 3.0 4.0

1 b l Y (w-9

v, - v, = v, = 3 v

30 -

20 -

1 0 -

0 0.0 1 .o 2.0 3.0 4.0

1 b l Y (w-9

T

Vout

Fig. IO. Comparison of simulated saturation current for device A-solid lines, device B-long-short dashed lines, devices C and D-short dashed lines as a function of 1/L,fi and l / L p o ~ y - .

I I V,=O.lV

0.4

O.: 0.2 0.0

V . in

Fig. 12. with a conventional inverter (T3 and T4) as a load.

A schematic circuit diagram of a precharged inverter (TI and T2)

L,,, (Pm)

Fig. 11. Comparison of simulated threshold voltage ( lk f j ) roll-off for device A (solid line), device B (long-short dashed line) and devices C and D (short dashed line) as a function of L,,,1,.

C. Effect of Source/Drain Implant on Circuit Per$ormance

Since the choice of Lpoly or Leff as the reference for the evaluation of LATID and LDD devices results in such different conclusions, it is important to know how circuit speed is affected by different choice of length criteria. Fig. 12 shows an inverter with a precharged p-channel MOSFET (T2) and a conventional inverter (T3 and T4) as a load. The precharged inverter was chosen because it can be independently evaluated for the n-channel MOSFET (TI) performance without added complications from the p-channel device (T2).

SPICE simulations were performed using extracted param- eters from devices A through C. Fig. 13 shows the input and output waveforms of the precharged inverter. Note that the T1 drain voltage was initially precharged to VDD via T2 by lowering Gp.. Gpc was then brought up to VDD again,

0 @Pc v~~

V. v~~

in 0

Fig. 13. The input and output waveforms of the precharged inverter

followed by the rising edge of Vin. The circuit delay was estimated as the time difference between Vi, = v D o / 2 and Vout = V 0 ~ / 2 . Fig. 14 shows the normalized gate delay as a function of le^ and Lpoly for LATID devices with respect to LDD device. It is interesting to note that

1) For devices with Lpoly (or Leg) 2 5 pm, the normalized gate delay approaches a constant ratio, showing no sig- nificant difference in device speed between the LATID and LDD designs.

2) For a given Lpolyr the LATID devices show smaller delay time than the LDD device (lower 2 curves). The ratio decreases as device length is reduced. However, this is no longer true when one plots gate delay versus

(upper 2 curves). It shows that the LATID device is actually slower than the LDD device.

Both of these observations can be easily explained by approximating the gate delay, 7: using:

where Ctotal is the total capacitance at the output node (Vout) and IDSAT is the saturation drain current of the n-channel MOSFET (TI). Combining (2) with the results shown in Fig. 10, one would expect that for a given L,R the ratio of

1260 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 7, JULY 1995

I I I I 1.12 ; , #

- 3 3 - 6 & 0.97 -

0.92 I I I I

in IDS and gate capacitances between LATID and LDD

as the source/drain implant angle increases to improve hot- carrier reliability for short-channel MOSFETs, the total gate capacitance for LATID devices also increases compared to LDD devices at a given L,E. Consequently, the intrinsic speed of LATID devices/circuits has been found to be slower than LDD devices/circuits. For a given Lpoly ~ however, LATID devices have demonstrated better drive current capability than LDD devices, but with more pronounced threshold voltage roll-off. We ascribe the increase in IDS and VTH roll-off for LATID devices mainly to the extended overlap between the gate and source/drain regions. In short, we have found that the LATID design indeed offers better device reliability

devices at a given L,R or Lpoly. It has been found that

Fig. 14. Comparison of simulated gate delay between LATID and LDD devices as a function of L,tf and L,,l, (solid line--7.4/~~ and dashed line--TB/Tp .)

the gate delay for LATID and LDD devices can be simplified to: -- TLATID - ctotal,LATID/IDSAT,LATID

TLDD Ctotal,LDD/IDSAT,LDD

(3) Ctota1,LATID

M G 0 t a i , ~ ~ ~

where the total capacitance is:

Ctotal = CJ + 2 C g d o , T l + C g d o , T 2 + c l o a d (4)

C3 is the drain-to-substrate junction capacitance of devices T1 and T2, Cload is the input capacitance of the inverter T3 and T4, C g d o denotes the gate-to-drain overlap capacitance, and the multiplication factor “2” represents the Miller effect. We note that (4) is independent of the TI device length and Ctotal is dominated mainly by Cload and C, for long-channel devices. As a result, the ratio of the gate delay for LATID and LDD devices is expected to be very close to, but still larger than, 1 (see Fig. 14). As L,ff decreases, because of reduction in C I ~ , ~ ~ , the ratio of gate delay becomes more pronounced.

On the other hand, at a given Lpoly. the delay difference shown in Fig. 14 is affected primarily by the IDSAT of the LATID and LDD devices (see Fig. 10):

-- TLTLATID - Ctotal , LATID /IDSAT, LATID TLDD ct’total,LDD/IDSAT,LDD

- - ctotal ,LATID IDSAT,LDD ( 5 )

where I ~ S A T , L D D / l ~ S A T , L A T I D is significantly less than 1 .O as device length is reduced.

C t o t a i . ~ ~ ~ IDSAT,LATID

IV. CONCLUSIONS The effect of the source/drain implant on sub-0.5 pm CMOS

devicekircuit performance has been measured and compared

the devicekircuit performance degrades. The degradation of devicekircuit performance becomes more pronounced as de- vice length is reduced. As a result, the LATID design might have a limited range of application for short-channel MOS- FETs.

ACKNOWLEDGMENT The authors thank K. Mistry for designing the LATID

devices used in this work and the ULSI Operation Group at Digital for fabricating the devices.

REFERENCES

[I] C. Y. Wong, J. Y.-C. Sun, Y. Taur, C. S. Oh, R. Angelucci, and B. Davari, “Doping of Nf and Pf polysilicon in a dual-gate CMOS process,” in IEDM Tech. Dig., 1988, p. 238.

[2] C:Y. Lu, J. M. Sung, H. C. Kirsch, S. J. Hillenius, T. E. Smith, and L. Manchanda, “Anomalous C-V characteristics of implanted poly MOS structure in n+/p+ dual-gate CMOS technology,” IEEE Electmn Device Lett., vol. IO, p. 192, 1989.

[3] S.-W. Lee, C. Liang, C.-S. Pan, W. Lin, and J. B. Mark, “A study on the physical mechanism in the recovery of gate capacitance to CO, in implanted polysilicon MOS structure,” IEEE Electron Device Lett., vol. 13, p. 2, 1992.

[4] C:L. Huang, N. D. Arora, A. I . Nasr, and D. A. Bell, “Effect of polysilicon depletion on MOSFET I-V characteristics,” Electron. Lett., vol. 29, p. 1208, 1993.

[5] C.-L. Huang and N. D. Arora, “Measurements and modeling of MOS- FET I-V characteristics with polysilicon depletion effect,” IEEE Trans. Electron Devices, vol. 40, p. 2330, 1993.

[6] T. Hori, “1/4 p m LATID (Large-Tilt-Angle Implanted Drain) technol- ogy for 3.3 V operation,” in IEDM, 1989, p. 777.

[7] T. Hori, Y. Odake, J. Hirase, and T. Yasui, “Gate-capacitance charac- teristics of deep-submicron LATID (Large-Angle-Tilt Implanted Drain) MOSFET’s,” in IEDM, 1991, p. 375.

[8] T. Hori, J. Hirase, Y. Odake, and T. Yasui, “Deep-submicrometer Large- Angle-Tilt Implanted Drain (LATID) technology,” IELE Trans. Electron Devices, vol. 39, p. 2312, 1992.

[9] T.-Y. Huang, W. W. Yao, R. A. Martin, A. G. Lewis, M. Koyanagi, and J. Chen, “A novel submicron LDD transistor with inverse-gate structure,” in IEDM, 1986, p. 742.

[ I O ] H. Ishiuchi, K. Mitsui, S. Kusunoki, H. Oda, K. Tsukamoto, and Y. Akasaka, “Gate capacitance characteristics of gate/rc- overlap LDD transistor with high performance and high reliability,” in IEDM, 1991, p. 371.

[ I I] N. D. Arora, MOSFETModels for V U I Circuit Simulation-Theoq and Practice, Wien: Springer-Verlag, 1993.

HUANG et al.: EFFECTS OF SOURCEIDRAIN IMPLANTS ON SHORT-CHANNEL

[I21 N. Khalil, J. Faricelli, D. Bell, and S. Selberherr, “A novel method for extracting the two-dimensional doping profile of a sub-half micron MOSFETs,” in V U 1 Symposium, 1994, p. 131.

[I31 N. Khalil, C.-L. Huang, and I. Faricelli, “Measurements and simulations of short-channel MOSFET I-V and C-V characteristics,” submitted for publication in lEEE Trans. Electron Devices.

[ 141 S. Selberherr, A. Schutz, and H. Potzl, “MINIMOS-A two-dimensional MOS transistor analyzer,” IEEE Trans. Electron Dev., vol. ED-27, p. 1770, 1980.

1151 P. HabaS and J. Faricelli, “Investigation of the physical modeling of the gate-depletion effect,” IEEE Trans. Electron Devices. vol. 39, p. 1496, 1992.

1161 Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, “A new shift and ratio method for MOSFET channel-length extraction,” IEEE Electron Device Lett., vol. 13, p. 267, 1992.

[17] Y.-T. Yeow, “Measurement and numerical modeling of short-channel MOSFET gate capacitance,” IEEE Trans. Electron Devices, vol. ED-35, p. 2510, 1987.

[I81 C.-L. Huang, J. Faricelli, and N. D. Arora, “A new technique for measuring MOSFET inversion layer mobility,” IEEE Truns. Electron Devices, vol. 40, p. 1134, 1993.

[I91 H. Haddara and S. Cristoloveanu, “Two-dimensional modeling of locally damaged short-channel MOSFET’s operating in the linear region,” IEEE Trcins. Electron Dev.,., vol. ED-34, p. 378, 1987.

[20] G . Sh. Gildenblat and C.-L. Huang, “N-channel MOSFET model for the 6C300 temperature range,” IEEE Trans. Computer-Aided Design, vol. IO, p. 512, 1991.

1211 N. D. Arora, R. Rios, C.-L. Huang, and K. Raol, “PCIM: A physically based continuous short-channel IGFET model for circuit simulation,” IEEE Trans. Electron Devices, vol. 41, p. 988, 1994.

Cheng-Liang Huang (M’90) was born in Taipei, Taiwan, in 1960. He received the M.S. and Ph.D. degrees in electrical engineenng from The Pennsyl- vania State University, Univenity Park, in 1986 and 1991, respectively.

From 1986 to 1990, he was a research assistant in the Department of Electrical Engineenng at Penn State, working on low-temperature MOSFET device characterization and modeling. In February 1990, he joined Digital Equipment Corporation, Hudson, MA, where he is presently a pnncipal manufacturing

engineer in the TCADAJLSI Operations Group. His current interests include interface physics, device reliability, device physics and modeling He has authored and co-authored over 20 papers in these fields.

MOSFET 1261

N a d m A. Khalil (M’87) received the B.S.E.E. degree (with distinction) from the American Univer- sity, Beirut, Lebanon, in 1978, and an M.S.E.E. de- gree from Louisiana State University, Baton Rouge, in 1979. He is presently completing the Ph.D. degree at the Technical University, Vienna, Austria.

In 1985, he joined Digital Equipment Corpora- tion, Hudson, MA, where he is now a member of the TCADlULSI Operation Group. His current re- search interests are in the development of numerical software tools for the design and characterization of

CMOS technologies, optimization, and inverse modeling.

Narain D. Arora, (M’81-S’91) for photograph and biography, see p. 942 of the May 1995 issue of this TRANSACTIONS.

Bjorn Zetterlund (S’XO-M’SS) received the B.S., M.E., and Ph.D. degrees in electrical engineering from Rensselaer Polytechnic Institute, Troy, NY in 1970, 1972, and 1985, respectively.

From 1972 to 1984, he was an engineer with Raytheon Company in both Sudbury and Bedford, MA. Since 1985, he has been with Digital Equip- ment Corporation, Hudson, MA, where he has led development work on transistors for 1.0, 0.5, and, currently, 0.25 p m CMOS microprocessor technolo- gies.

Lawrence A. Bair (M’87) received the B.S. and M.S. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1984 and 1986, respectively.

In 1986, he joined Digital Equipment Corpora- tion, Hudson, MA, where he has worked on char- acterization and modeling of cryogenic and conven- tional CMOS devices. Currently, he is a principal manufacturing engineer in the ULSI Operations Group. His current interests include process and de- sign interactions, prediction of product performance.

and SPICE modeling of deep submicron MOSFETs.