Electric magnetic resonance control system

Performed By: Rawan Mnasra and Anan KabahaInstructor: Mony Orbach

Semesterial Winter 2014-2015Mid-semester presentation

Project motivation (1):

The lab of electron magnetic resonance uses ESR method.

Ferro-magnetic material , with interactions between spin of electrons and magnetic field.

ESR method may be used to detect oxygen condensation , injuries, cancer…

Project motivation (2):

In order to work with the oxygen detector, today we use big system ,this system is not suitable for performing tests easily, we want to implement the functionality of this big system using FPGA.

Project motivation (3):

The controller is sequencer that generates each clock one sequence.

The sequence contains rules for the ESR system.

The sequencer may contains loops.

Project goals:

Implement controller with an option to run nested loops (max 8) using VHDL.

Implement compiler for the sequencer.

Validation & Verification for the design.

The sequencer :

• Loop line by line over a sequence.• Sequencer rate is 100MHZ -> take one decision each

10 [ns].

• The sequence may contain loops.• Maximum nested loops is 8.• Each loop can have number of iterations of 20 bit .

Sequencer block diagram:8 K

8 bit

1111 0000

RAM

Address

Sequencer

out

CLKResetLoad

1111 0001

0011 0001

0000 0001

1111 1111

8 bit

“Good” cases :

For i = 1 :10

“1”

“2”

“3”

end

For i = 1 : 10 “1” For j = 1 : 5 “2” “3” end “4”end

“Bad” cases :

For i = 1 :10

“1”

end

For i = 1 : 10 For j = 1 : 5 For k = 1 : 3 For l = 1:20 For m = 1:2 For n = 1:30 For t = 1:6 “1” end “2” end “3” end ….end

For i = 1 : 10 “1” For j = 1 : 5 “2” For k = 1 : 3 “3” For l = 1:20 “4” For m = 1:2 “5” For n = 1:30 “6” For t = 1:6 “7” For s = 1:100 ”8” End End End ….. EndEnd

Row representation in our implementation:

DATA U-FLAG

FLAG

8 bit 4 bit 20 bit

FLAG

REGULAR LINE

0X00000

END OF FOR 0XFFFFE

END OF FILE 0XFFFFF

START OF FOR

ELSE

U-FLAG

0

Number of Fors “s to end. (0-7)

0

Number of for ”s” after this for to open. (0-7)

Compiler:

We will use a compiler to convert “bad” cases to “good” cases.

This compiler will be simple GUI. we will write it using matlab.

“Bad” cases : (1)

For i = 1 :10

“1”

end

For i = 1 :5 “1” “1”end

For i = 1 :9 “1”end

For i = 1 :4 “1” “1”End “1”

“Bad” cases : (2)

For i = 1 : 10 For j = 1 : 5 For k = 1 : 3 For l = 1:20 For m = 1:2 For n = 1:30 For t = 1:6 “1” end “2” end “3” end ….end

For i = 1 : 10 (jump 7 + initialize 7 fors) “1” For j = 1 : 5 (jump 6 + initialize 6 fors) “1” For k = 1 : 3 (jump 5 + initialize 5 fors “1” For l = 1:20 “1” For m = 1:2 “1” For n = 1:30 (jump 2 …) “1” For t = 1:3 “1” “1” end “2” end “3” end ….end

“Bad” cases : (3)For i = 1 : 10 “1” For j = 1 : 5 “2” For k = 1 : 3 “3” For l = 1:20 “4” For m = 1:2 “5” For n = 1:30 “6” For t = 1:6 “7” For s = 1:100 ”8” End End End ….. EndEnd

For i = 1 : 10 “1” For j = 1 : 5 “2” For k = 1 : 3 “3” For l = 1:20 “4” For m = 1:2 “5” For n = 1:30 “6” For t = 1:6 “7” For s = 1:100 ”8”

END (One end with number of For’s to close)

Compiler Algorithm:1. Loop over the rows and convert bad cases #1 to good case #1.2. Loop over the rows and convert bad cases #2 & #3 to good case #2

& #3.3. Loop over the rows and generate the sequence.

Sequencer FSM

START No Loop

Loop 1

Loop 2Loop 8

⋯

addr= 0

addr = addr + 1If end_loopaddr = loop_addresselseaddr = addr + 1

𝐿𝑜𝑜𝑝

𝐿𝑜𝑜𝑝

𝐿𝑜𝑜𝑝

𝐿𝑜𝑜𝑝𝐿𝑜𝑜𝑝

𝐿𝑜𝑜𝑝

𝑙𝑜𝑜𝑝 𝑖𝑛𝑑𝑒𝑥>0

𝐸𝑂𝐹 /𝑇𝑟𝑖𝑔𝑔𝑒𝑟/𝑅𝑒𝑠𝑒𝑡

If end_loopaddr = loop_addresselseaddr = addr + 1

If end_loopaddr = loop_addresselseaddr = addr + 1

> 0 > 0

= 0 = 0

= 0

= 0

𝐸𝑂𝐹 /𝑇𝑟𝑖𝑔𝑔𝑒𝑟/𝑅𝑒𝑠𝑒𝑡

𝐸𝑂𝐹 /𝑇𝑟𝑖𝑔𝑔𝑒𝑟/𝑅𝑒𝑠𝑒𝑡

𝑅𝑒𝑠𝑒𝑡

𝐸𝑂𝐹 /𝑇𝑟𝑖𝑔𝑔𝑒𝑟 /𝑅𝑒𝑠𝑒𝑡

In each state we check the bad cases also.

Time Line• 13/1/2015 to 21/1/2015 start syntheses. Jan• 22/1/2015 to 31/1/2015 Exams.Jan• 1/2/2015 to 17/2/2015 Exams.Feb• 18/2/2015 to 28/2/2015 Finish syntheses.Feb• Define test bench and run it in the module.Mar• Writing the module to the FPGA +

validation.April

• Final presentation.May

Questions?

Thank you