36
1 2006/Mar/2
1
2006/Mar/2
2
Noise Margin
3
VTC of an Inverter
Figure 1.29 Voltage transfer characteristic of an inverter. The VTC is approximated by three straightline segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).
Figure 1.30 The VTC of an ideal inverter.
NMH=VOHVIH
NML=VILVOL
4
Propagation Delays
Figure 10.3 Definitions of propagation delays and switching times of the logic inverter.
tP=1/2(tPLH+tPHL)
5
Power Dissipation &Other Design Concern
• Static power (0 for CMOS inverter)• Dynamic power:
PD = f C(VDD)2
• Delay-Power ProductDP = PD tP
• Silicon Area (Process technology, circuit design techniques, careful layout)
• Fan-In and Fan-out
6
Digital system Design
• Custom VLSI vs. gate-array chips• FPGA (field-programmable gate array)• Design Abstraction (standard cells)
• Computer Aids
7
Inverter Equivalent Circuit
Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied in Section 4.10.
8
CMOS Inverter
Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.
tnDD
nnDSN VV
LWkr 1
tpDD
ppDSP VV
LWkr 1
9
CMOS InverterStatic Operation (1)
tnDD
nnDSN VV
LWkr 1
Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit.
10
CMOS InverterStatic Operation (2)
Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit.
tpDD
ppDSP VV
LWkr 1
11
CMOS InverterStatic Operation (3)
Figure 4.56 & 10.5 The voltage transfer characteristic of the CMOS inverter. (When QN and QP are matched.)
kn > kp
kp > kn
SlopetansitiongmN+gmP)(roN //roP)
pn
tnpntpDDth kk
VkkVVV
1
np
n
p LW
LWmatching
:
tDDLH VVNMNM
32
83
nLWn
pLWp
2minArea Lpn
12
CMOS InverterDynamic Operation (1)
Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge.
13
CMOS InverterDynamic Operation (2)
Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge.
14
CMOS InverterDynamic Operation (3)
Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an identical inverter formed by Q3 and Q4.
C=2Cgd1+2Cgd2+Cdb1+Cdb2+Cg3+Cg4+Cw
tPHL=1.6C/[k’n(W/L)nVDD]
(Section 4.10) Vt~0.2VDD
15
CMOS InverterDynamic Operation (4)
Figure 10.7 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
2210 tDD
nnDN VV
LWki
2
221
2DDDD
tDDn
nPHLDNVVVV
LWkti
20
avPHLDNDN
DNtiii
av
2
DN
DDPHL i
VCt tPHL=1.7C/[k’n(W/L)nVDD] under Vt~0.2VDD
16
CMOS InverterDynamic Operation (5)
Figure 10.7 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
tPLH=1.7C/[k’p(W/L)pVDD]
under |Vtp|~0.2VDD
2 n DissipatioPower Dynamic DDD CVfP
17
Example 10.1
fF 25.622fF 2.0
fF 3625.23.02
fF, 7875.03.02fF 1 fF, 1
fF, 3375.03.0 fF, 1125.03.0
. and , , Find fF. 2.0 ecapacitanc wiringThe fF. 1and fF 1 are escapacitancbody -drain of valueeffective theFurther, width.
gate of mfF/ 0.3 be tospecified are escapacitanc overlapdrain -gate and source-gate The m.m/0.251.125 is for that and m,m/0.250.375 is of ratio
/ The V. 5.2 and V, 4.0 ,A/V 115 ,mfF/ 6for which process m-0.25 ain fabricatedinverter CMOS aConsider Dynamic
432121
4
3
21
21
22
wggdbdbgdgdw
pppoxg
nnnoxg
dbdb
pgdngd
PPLHPHLwdbp
dbn
PN
DDtptnoxnox
CCCCCCCCC
WLWCC
WLWCCCC
WCWCSolution
tttCCC
LWVVVCC
18
Example 10.1
ps 5.26
9.273.13.23383.33.23
matched.not isinverter the,83.3 and 3
ps 3.232
A 3492
318380
A 31822
12
A 380210
)(continued
21
av
av
2
2
PLHPHLP
PLH
pnnp
DN
DDPHL
DN
DDDDtDD
nnPHLDN
tDDn
nDN
ttt
pst
WW
iVCt
i
VVVVL
Wkti
VVL
Wki
Solution
19
CMOS Logic-Gate Circuits
Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.
Figure 10.11 Usual and alternative circuit symbols for MOSFETs.
20
Pull-Down Networks
Figure 10.9 Examples of pull-down networks.
21
Pull-Up Networks
Figure 10.10 Examples of pull-up networks.
22
Two input NOR / NAND Gates
Figure 10.12 A two-input CMOS NOR gate. Figure 10.13 A two-input CMOS NAND gate.
23
A Complex Gate
Figure 10.14 CMOS realization of a complex gate.
DCBA
CDBA
CDBA
CDBAY
BABA
BAAB
:functin logiccomplex more aConsider
:law sDeMorgan'
24
The Exclusive-OR Function (XOR)
Figure 10.15 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDNthat is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27).
(a)BAABY
BABAY
25
Summary of the Synthesis Method
• The PDN can be most directly synthesized by expressingY as a function of the uncomplemented variables. If complemented variables appear in this expression, additional inverters will be required to generate them.
• The PUN can be most directly synthesized by expressingY as a function of the complemented variables and then applying the uncomplemented variables to the gates of the PMOS transistors. If uncomplemented variables appear in this expression, additional inverters will be needed.
• The PDN can be obtained from the PUN (and vice versa) using the duality property.
26
Transistor Sizing
Figure 10.16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.
Rseries = rDS1 + rDS2 + …
= constant________(W/L)eq
(W/L)eq;series =1_______________
1(W/L)1
_____ 1(W/L)2
_____+ +...
(W/L)eq;parallel =
(W/L)1+(W/L)2+…
27
Transistor Sizing
Figure 10.17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.
28
Example 10.2
Figure 10.18 Circuit for Example 10.2.
Basic inverter:n = 1.5, p = 5, L = 0.25 m
29
Homework #1
• Problems in Chapter 10: 4, 7, 10, 12, 15, 18, 25, 29
30
Pseudo-NMOS Logic Circuits
Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter.
Swing
NM
Static PD
31
Pseudo-NMOS Logic Circuits
Figure 10.20 Graphical construction to determine the VTC of the inverter in Fig. 10.19.
1:10~4: pn kk
pn kkr
NM
32
Pseudo-NMOS InverterStatic Characteristics
n)(saturatio for ,221
tIOtInDN VvvVvki
(triode) for , 221
tIOOOtInDN VvvvvVvki
(triode) for , 221
tOODDODDtDDpDP VvvVvVVVki
n)(saturatio for ,221
tOtDDpDP VvVVki
Region QN QP ConditionI Cutoff Triode vI < VtnII Sat. Triode vO > vI VtnIII Triode Triode Vtp < vO < vI VtnIV Triode Sat. vO < Vtp
33
)1(
rr
VVVV tDDtIL
22tItDDtO VvrVVVv
1)or (
r
VVVVV tDDtthM
22 1)( tDDtItIO VVr
VvVvv
tDDtIH VVr
VV 32
rVVV tDDOL
111
Figure 10.21 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V, Vtn = –Vtp = 1 V, and r = 9.
34
Pseudo-NMOS Logic Circuits
• Noise Margin vs. r
• Dynamic Operation
11111rrr
VVVNM tDDtL
r
VVNM tDDH 321
DDpPLH Vk
Ct 7.1
DDn
PHL
Vr
k
Ct
46.01
7.1Asymmetrical delay
35
Pseudo-NMOS Inverter Design
• The design parameters of interest:VOL, NML, NMH, Istat, PD, tPLH, tPHL
• r : VOL , NM area , tP
• W/L: small W/L small C, Istat, PDlarge W/L small tP
• Typically, Istat ~ 50 to 100Aand PD ~ 0.25 to 0.5 mW
36
Pseudo-NMOS Logic Circuits
Figure 10.22 NOR and NAND gates of the pseudo-NMOS type.
PDN design
