ENGG1015: lab 4 Ball Counting Circuit 1 st Semester 2012-13 Equipments you’ll need in this lab: (a) Multi-meter (b) Wire Kit (c) Potentiometer (d) Tunnel (e) Tunnel Con- nector (f) FPGA Cable (g) FPGA Connector (h) Breadboard Figure 1: Materials for this lab ✓ ✒ ✏ ✑ The goal of this lab is to connect the abstract digital logic world to the physical world that interacts with voltage, current and resistance. You will get familiar with the lab equipment that you will also use in your project. ...................................................................... 1 Finding your lab partner You will be working with a randomly assigned partner for this lab. To find your assigned lab partner and the assigned table, 1. Log in to Moodle. 2. Select the assignment Lab 4 Partner Please proceed to your assigned table.
Transcript
ENGG1015: lab 4
Ball Counting Circuit
1st Semester 2012-13
Equipments you’ll need in this lab:
(a) Multi-meter (b) Wire Kit (c) Potentiometer
(d) Tunnel (e) Tunnel Con-nector
(f) FPGA Cable (g) FPGA Connector
(h) Breadboard
Figure 1: Materials for this lab
The goal of this lab is to connect the abstract digital logic world to the physical world thatinteracts with voltage, current and resistance. You will get familiar with the lab equipment thatyou will also use in your project.
In digital logic design, signals take the abstract value TRUE/FALSE, HIGH/LOW, “1”/“0”.Such definition is useful to abstract the low level details of the circuit such that very complexsystems can be composed easily.
In reality, physical values such as voltage and current are used to represent such discrete logicalvalues. In particular, any physical values that do not overlap may be used to represent TRUEand FALSE. The following table shows some example definition of TRUE and FALSE usingcircuit:
voltage voltage range currentTRUE 12V 2.0–3.3V +100mAFALSE 0V 0–1.5V -100mA
4.1 Interfacing with the FPGA board We will start with determining I/O voltage that arebeing used by the FPGA on the Basys2 board to represent the logical value of HIGH and LOW.Load the file testio.xise. Take a look at file testio.sch. At the top part of the schematic,it has a simple design that directly connect button 1 to the output testout. At the bottom, ithas another signal testin that connects to LED4.
The signals testin and testout are connected to the I/O connector JA on the Basys2 board.In particular, testin is connected to the pin B2, and testout is connected to the pin J3.
The FPGA is connected to the breadboard using an FPGA Cable. On each end of the cablethere is an extra dot (See Figure 2(a)) that helps identify the location of Pin 1. When using theFPGA Cable, make sure it is connected with the correct orientation.
(a) Pin 1 on an FPGA cable (b) I/O Connector JA on Basys2 Board
Figure 2: FPGA Connections
4.2 FPGA Cable – Breadboard ↔ Basys2 Board One end of the FPGA cable should beconnected the breadboard.
Figure 3: Internal connections on a breadboard
A breadboard is a handy tool for constructing simple circuits. Circuit components, such asresistors and integrated circuits (ICs) can be inserted into one of the many tiny sockets, or holes,in the breadboard. The holes are internally connected according to the Figure 3. All the holesin the top and bottom two rows are connected. The holes in the middle are connected verticallyin a group of five.
When constructing circuits, the two rows in the top and bottom should be used for distributingpower and ground. Integrated circuits should be inserted in the middle gap. When insertingwires into the holes, make sure they are securely pushed all the way down. Try to use wires ofappropriate length so there is no loose wire left hanging.
Before you can obtain the FPGA board from our TAs, first make the following connection onthe breadboard:
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ENGG1015 lab 4
1 5
10
15
20
25
30
35
1 5
10
15
20
25
30
35
ab
cd
ea
bc
de
4.3 Call Your TA/LA, Get Your Board The other end of the FPGA cable should be connectedto the connector JA on the Basys2 board. The connector is located at the corner of the boardas shown in Figure 2(b). Pin 1 of the FPGA cable should be connected to VCC of connectorJA. As a result, Pin 6 will be connected to the pin labeled as B2 on the same connector.
From the picture in Figure 2(b), answer the following questions before asking your TA/LA togive you a board.
• How do you measure VCC on the breadboard?• Once connect to the FPGA, where are the signals testout and testin connected
to on the breadboard? (Recall that testout is routed to pin J3, testin is routedto pin B2.)
4.4 Using the FPGA Cable, connect from the I/O connector JA from the Basys2 board tothe breadboard. Also connect the FPGA board to the computer. Turn on the power switch onthe FPGA board.
Measure the voltage of VCC on the breadboard using a DMM. It is the main power source forthe breadboard. What is the value of VCC?
Vcc =
4.5 Output from FPGA Implement the design in testio.xise and download the implementedtestio.bit to the FPGA board. Once downloaded, the value of button 1 will be reflected atthe output testout. Measure the voltage of testout on the breadboard. What is the voltage(VL) when button 1 is not pressed? What is the voltage when button 1 is pressed (VH)?
VL = VH =
4.6 Using a POT Now we know what voltage level the FPGA outputs to represent HIGH andLOW, we want to know what the board expects the outside to put in its input pin to representLOW and HIGH. In other word, we want to determine the threshold voltage that the FPGAuses to differentiate a HIGH signal from a LOW signal.
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ENGG1015 lab 4
For that, we will use a potentiometer (POT). A POT is a device that allows a user to adjustits resistance by turning a knob. The POT we are using in this lab can be represented by thefollowing diagram:
Pin 1
Pin 2
Pin 3
(a) Circuit Diagram
Pin 1 2 3
(b) Pin Location
Pin 1 2 3
(c) Pin Location
Figure 4: Potentiometer
As can be seen from the diagram above, the resistance between pin 1 and 3 (R13) is constantregardless of the dial position of the POT. The resistance between pin 1 and 2 (R12), and pin 2and 3 (R23) varies when the dial of the POT is turned, with R12 + R23 = R13.
Using a DMM (with the dial switched to measuring resistance, start with 2000), measure R13.Also, verify that R12 and R23 varies as the dial is turned. When you have finished, turn the dialuntil R12 = R13/2.
R13 =
4.7 Input to FPGA Disconnect the FPGA before you change the circuit on the bread-board. Then, construct the following circuit on the breadboard.
VCC
GND
+
−Vtestin
It can be achieved simply by inserting the POT into the FPGA. Make sure the 3 pins of thePOT are inserted on different columns of the board as shown below:
1 5
10
ab
cd
e
Connect pin 2 of the POT to pin 6 on the FPGA connector. Once you have finished constructingthe circuit, double check all the connections are correct. (At the minimum, you should checkif there is any short circuit between the two power rails.) After you have double checkedyour connection, reconnect the FPGA, power it on, and configure it with testio.bit again.
4.8 Finding the input threshold Assuming you have set your POT above such that R12 =R13/2, read the voltage Vtestin using the DMM, what is the voltage?
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Vtestin =
Now slowly turn the dial on the POT. It should change the value Vtestin depending on thedirection you are turning. When Vtestin drops below certain value (VT ), you will find that LED4 will be turned off. What is the value VT ?
VT =
To define a logical interface for input to FPGA, we usually define two values: VIL and VIH .VIL is the maximum input voltage that the FPGA will regard as logical LOW, and VIH is theminimum input voltage that the FPGA will regard as logical HIGH.
Based on the above measurements, make suggestion on the values of VIL and VIH .
VIL = VIH =
4.9 Checkoff 1
Demonstrate your working connection between the FPGA and the breadboard and an-swer the following questions:• What are the values of VL, VH and VT ? What do these values represent?• What happen to the LED when Vtestin ≈ VT ?• Explain your choice of VIL and VIH . Can we set VIL = VIH = VT ?.
Last week you have constructed a simple “ball counter” using digital logic circuits. A button onthe Basys2 board was used to mimic the effect of a ball rolling through a detector. This week,you will construct the ball detector and connect to the ball counter from last week. This ballcounter will eventually become part of your final project of this class.
5.1 A ball detection tunnel has been constructed using a laser diode and a photo detector.When a ball rolls through the tunnel, it blocks the laser, thereby changing the resistance of thephoto detector. Your circuit should use this change in resistance to signal if a ball is detected.When there is a ball blocking the laser, it should produce a logical HIGH signal. When there isno ball, it should produce a logical LOW signal.
Figure 5(a) shows internal circuit of the ball tunnel. It should be connected to the breadboardusing the Tunnel Cable, which has a 5×2 pin connector. Pin 1 of the cable is aligned with theRED wire. Note that every other pins (i.e. 1 & 2, 3 & 4, etc) are connected together for sake ofsimplicity.
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Roff ∼ Ron
100 Ω
R+
R−
not connected
L+
L−
1 2
9 10
Ball Tunnel InternalTunnel CableCable Connector
(a) Tunnel Connection
(b) Pin Numbers
Figure 5: Ball Tunnel Connections
The first step is to determine the characteristics of the photo detector. A photodetector is simplya resistor with a variable resistance that depends on the amount of light shinning on it. Whenlight is shinning on the photodetector, it has resistance of Ron. When there is no light shinningon the photodetector, it has resistance of Roff . Take a ball tunnel and measure the values Ron
and Roff . You need to supply power to the laser diode in the tunnel using the FPGA board.Connect L+ to VCC and L− to GND.
Roff = Ron =
5.2 Load the file cnt3.xise from the downloaded file. It contains the same ball counting statemachine from last week’s lab. Instead of connecting the input din to a button, din is connectedto the I/O port at pin B2.
Using the values of Roff and Ron and the input threshold voltage VT obtained above, design acircuit that produces a voltage (Vdin) to represent the presence of ball through the tunnel. Thissignal should be connected to the din input of the ball counter. When there is no ball blockingthe photodetector, din should be at a voltage that represents LOW. When the ball is blockingthe photodetector, din should be at a voltage that represents HIGH.
A simple potential divider circuit connecting the photodetector to another fixed resistor Rpull
is adequate for this purpose. You have to determine how Rpull should be connected to thephotodetector to provide the correct function described above. Draw your circuit in the spacebelow.
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What is the value of Rpull?
Rpull =
Tune the POT to the calculated value of Rpull.
The following diagram will guide you in constructing the circuit in the breadboard. The lefthand side represent the FPGA Cable connection, and the right hand side represent the TunnelCable connection. Connect the dots to implement your potential divider circuit.
R+
R−
L+
L−
1 2
9 10
din
GND
VCC1
6
5.3 Connect All Construct your circuit above on the breadboard. Connect the FPGA and theTunnel using the FPGA Cable and the Tunnel Cable respectively.
Finally, load the file cnt3.xise, which contains a sample implementation of the ball counterfrom last lab. Implement the design and download the resulting cnt3.bit to the FPGA.
If all things work, you should now be able to count the number of ball rolling through the tunnel.
5.4 Checkoff 2
Show to your TA a completed circuit connecting the Tunnel with the FPGA. Demonstratethe function of the tunnel.• What happen if the ball rolls too fast? How can you avoid that problem?• What happen if the ball rolls too slowly?
