ENGR 303 – Introduction to Logic Design Lecture 15

Dr. Chuck BrownEngineering and Computer Information Science

Folsom Lake College

• Synchronous Sequential Logic Design

• Finite State Machines

Outline for Todays Lecture

ENGR 303

• Breaks cyclic paths by inserting registers

• State changes at clock edge: system synchronized to the

clock

• Rules of synchronous sequential circuit composition:

– Every circuit element is either a register or a combinational circuit

– At least one circuit element is a register

– All registers receive the same clock signal

– Every cyclic path contains at least one register

• Two common synchronous sequential circuits

– Finite State Machines (FSMs), Pipelines

Synchronous Sequential Logic Design

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Next

State

Current

State

S’ S

CLK

CL

Next State

Logic

Next

StateCL

Output

Logic

Outputs

• Consists of:

– State register

• Stores current state, Q

• Loads next state at clock edge, D → Q

– Combinational logic

• Computes the next state

• Computes the outputs

Finite State Machine (FSM)

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D Q

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Examples of Finite State Machines

• Vending Machine

• Combination Lock

• Elevator Controller

• Light Controller

• Alarm System

• Pattern Recognition

• Network Controller

• Interface Controller

• and more

CLKM Nk knext

state

logic

output

logic

Moore FSM

CLKM Nk knext

state

logic

output

logic

inputs

inputs

outputs

outputsstate

statenext

state

next

state

Mealy FSM

• Next state determined by current state and inputs

• Two types of finite state machines differ in output logic:

– Moore FSM: outputs depend only on current state

– Mealy FSM: outputs depend on current state and inputs

Types Finite State Machines (FSMs)

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TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bra

vado

Blv

d.

Dorms

Fields

Dining

Hall

Labs

• Traffic light controller

– Traffic sensors: TA, TB (TRUE when there’s traffic)

– Lights: LA, LB

FSM Example

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TA

TB

LA

LB

CLK

Reset

Traffic

Light

Controller

• Inputs: CLK, Reset, TA, TB

• Outputs: LA, LB

FSM Black Box

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S0

LA: green

LB: red

Reset

• Moore FSM: outputs labeled in each state

• States: Circles

• Transitions: Arcs

FSM State Transition Diagram

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• Moore FSM: outputs labeled in each state

• States: Circles

• Transitions: Arcs

1. FSM State Transition Diagram

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S0

LA: green

LB: red

S1

LA: yellow

LB: red

S3

LA: red

LB: yellow

S2

LA: red

LB: green

TA

TA

TB

TB

Reset

=00 =01

=10=11

Outputs(Lights LA, LB)

State(S0, S1)

Inputs(Traffic Sensors TA, TB)

Current State Inputs Next State

S1 S0 TA TB DS1 DS0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

2. FSM State Transition Table

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Current State Inputs Next State

S1 S0 TA TB DS1 DS0

0 0 0 0 0 1

0 0 0 1 0 1

0 0 1 0 0 0

0 0 1 1 0 0

0 1 0 0 1 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 1 0

1 0 0 0 1 1

1 0 0 1 1 0

1 0 1 0 1 1

1 0 1 1 1 0

1 1 0 0 0 0

1 1 0 1 0 0

1 1 1 0 0 0

1 1 1 1 0 0

2. FSM State Transition Table

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DS1 = S1’S0+ S1S0’ = S1 S0

3. Map FSM Next State Logic

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01 1100

0 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1

S1S0 10

00

01

11

10

DS0 = S1’S0’TA’ + S1S0’TB’

TATB

01 1100

1 1 0 0

0 0 0 0

0 0 0 0

1 0 0 1

S1S0 10

00

01

11

10

TATB

Current State Outputs

S1 S0 LA1 LA0 LB1 LB0

0 0

0 1

1 0

1 1

Output Encoding

green 00

yellow 01

red 10

4. FSM Output Table

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Current State Outputs

S1 S0 LA1 LA0 LB1 LB0

0 0 0 0 1 0

0 1 0 1 1 0

1 0 1 0 0 0

1 1 1 0 0 1

Output Encoding

green 00

yellow 01

red 10

LA1 = S1

LA0 = S1’S0

LB1 = S1’

LB0 = S1S0

4. FSM Output Table

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S1

S0

S'1

S'0

CLK

state register

Reset

r

5. FSM Logic Design: State Register

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DS1

DS0

N Flip Flops for 2N states

S1

S0

S'1

S'0

CLK

next state logic state register

Reset

TA

TB

inputs

S1

S0

r

6. FSM Logic Design: Next State Logic

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DS1

DS0

DS1 = S1’S0+ S1S0’ = S1 S0 DS0 = S1’S0’TA’ + S1S0’TB’

S1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1

S0

r

7. FSM Logic Design: Output Logic

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DS1

DS0

LB1 = S1’

LB0 = S1S0

LA1 = S1

LA0 = S1’ S0

CLK

Reset

TA

TB

S'1:0

S1:0

LA1:0

LB1:0

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S1 (01) S2 (10) S3 (11) S0 (00)

t (sec)

??

??

S0 (00)

S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)

??

??

0 5 10 15 20 25 30 35 40 45

Green (00)

Red (10)

S0 (00)

Yellow (01) Red (10) Green (00)

Green (00) Red (10)Yellow (01)

S0

LA: green

LB: red

S1

LA: yellow

LB: red

S3

LA: red

LB: yellow

S2

LA: red

LB: green

TA

TA

TB

TB

Reset

8. FSM Timing Simulation

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• Binary encoding:

– i.e., for four states, 00, 01, 10, 11

• One-hot encoding

– One state bit per state

– Only one state bit HIGH at once

– i.e., for 4 states, 0001, 0010, 0100, 1000

– Requires more flip-flops

– Often next state and output logic is simpler

Improvement FSM State Encoding

ENGR 303