ESE 570 MOS TRANSISTOR THEORY – Part 2ese570/spring2015/ESE... · THEORY – Part 2 GCA (gradual...

1Kenneth R. Laker, University of Pennsylvania, updated 03Feb15

ESE 570 MOS TRANSISTOR THEORY – Part 2

GCA (gradual channel approximation) MOS Transistor ModelStrong Inversion Operation


CMOS = NMOS + PMOS


VGS

<< VT0

Two-Terminal MOS Capacitor -> nMOS Transistor

Substrate or Bulk B p

Depletion region

-

-

-

--

-

- - -

-

Immobile acceptor

ions

VS

VG V

D

NMOS TRANSISTOR IN CUTOFF REGION


Two-Terminal MOS Capacitor -> nMOS Transistor

VGS

= VT0n

+ δ Onset of INVERSION

QB0Q

I

-

- ---

- - - --

-- -

-

VG V

D


MOS Transistor Regions of Operation

n+ n+-

- --

- - --

- -

-



n+ n+-

- - -- - - -

-

- ---



VGD

= VGS

– VDS

< VT0

VCS

(y) = VDSAT

VDS

- VDSAT

n+n+

z-

--

- - - --

- --

-

VDS

= VD ≥ V

DSAT = V

GS - V

T0


VG = V

GS > V

T0

xy

VD = small

zn+

zy

n+

dR=−dyW

01

7nQ I 0 y 11

µn = U0 = electron mobility = cm2/{V sec}

.=V seccm2

cm2

C

and

MOSFET CURRENT – VOLTAGE CHARACTERISTICSV

GD > V

T0


VG = V

GS > V

T0

z

VD = V

DS

Mobile charge in inverted channel:

IV=

1R

Ey >> E

x, E

z

n+ n+

VCS

(y = 0) = VS = 0

VCS

(y = L) = VDS

QI(y) = -C

ox [V

GS – V

CS(y) - V

T0]

VCS

(y)


QI(y) = -C

ox [V

GS – V

CS(y) - V

T0]

VCS

(y = 0) = VS = 0

VCS

(y = L) = VD

0 ≤ VCS

(y) ≤ VDS

dVCS

dVCS

dVCS

VGS

- VCS

- VT0

(VGS

– VT0

)VCS

- V2CS

/2 VCS

= VDS

VCS

= 0

dV CS= I D dR=I D

W 7nQ I 0 y1dy


KP=7nCox=0cm2

Vs10CV

1cm2 1=

C / sV 2 =

AV 2

KP -> Transconductance Parameter


ID(V

DS = V

DSAT) and V

DSAT = V

GS - V

T0

Assumptions:


IN GENERALI

D(V

DS = V

DSAT) = I

D(sat)

@VDS

= VDSAT

= VGS

- VT0

I D 0 sat 1=7nCox

2WL0V GS−V T0 1

2

SATLINEARI

D(sat)


2 L

VDSAT

V DS−V DSAT

1

1−2 LL

≈1

1−6V DS≈1,6V DS

6V DS≪1for

n+ n+


ID = f(V

GS, V

DS)

6≠ 0

6≠ 06≠ 0

Compatible Eqs. ?


DISCONTINUOUS! @ V

DS = V

DSAT


6V DS≪1


6V DS≪1

V T=V T0,30/∣28F−V SB∣−/∣28F∣1


(VT = V

Tn > 0)

(VT = V

Tp < 0)

VGS

< VT, V

DS > V

GS - V

T

VGS

< VT, V

DS ≤ V

GS - V

T

VGS

> VT, V

DS ≥ V

GS - V

T

VGS

> VT, V

DS < V

GS - V

T

V GD.V T

V GD-V T

V GD-V T

V GD.V T


=> SATB

S

G

D


=> SAT


n+ n+


Eox=V GSt oxvolts /cm E= q

4siN A x volts /cm


2007

0.0450.80

2005200320011999199719951993

0.090.130.180.250.350.60Feature Size (µm)

Year

Historical reduction in min feature size for typical CMOS process

Eox=V GS

t oxvolts /cm E= q

4siN A x volts /cm


Load Capacitance (Ccap) – WL (1/tox)

Gate Delay (T) – V Ccap/I


n+n+

n+n+

LD LD


Depletion Region Capacitances

(nMOS, pMOS)Model


Wov

Wov

CGS0

(overlap) = Cox

WLD

CGD0

(overlap) = Cox

WLD

CGB0

(overlap) = Cox

Wov

LM

SPICE: Cox

LD = CGS0 = CGD0 in F/m; C

oxW

ov = CGB0 in F/m

Wn+ n+

LD

Recall Cox

= COX and tox

= TOX in SPICE

MOSFET CAPACITANCES


poly= =SiO

2 n+SiO

2

pWov

Wov

CBG0

Weff

CBG0

– Gate-to-Bulk Overlap Capacitance

CGB0

= Cox

Wov

LM

(conservative estimate)

Gate Extension Design Rule

C4 = 2λ = Wov


MOSFET – Saturation Region

Leff

Leff

Leff

n+ n+

n+n+

n+ n+

Cgb, Cgs and Cgd


Gate-to-Bulk, - Drain & - Source Oxide Capacitances Summary

Application of Oxide Capacitance Model:1. Approximate: For hand calculations, assume that Cgb, Cgd and Cgs are connected in parallel for each region of operation, i.e. Cg(tot) = C

oxWL

eff + 2C

GB0 + C

GD0 + C

GS0 Cut-off Region;

Cg(tot) = Cox

WLeff

+ 2CGB0

+ CGD0

+ CGS0

Linear Region;Cg(tot) = 2/3 C

oxWL

eff + 2C

GB0 + C

GD0 + C

GS0 Saturation Region.

and use the maximum value Cg(tot) = Cox

WLeff

+ 2CGB0

+ CGD0

+ CGS0

+ 2CGB0

0 + 2CGB0 0 + 2CGB0


Depletion Region Capacitances -> Cdb

, Csb

n+ n+



, Csb

C j 0V 1=∣dQ j

dV∣=

AC j0

01, V80

1m=

0AS , AD 1⋅CJ

01, VPB

1MJ

where

CJ=C j0=4Sixd

=/ q4Si20N AN D

N A,N D1 180

(F/cm2)

Qj = depletion-region charge A = junction area

V = Ext Bias --> VSB, VDB

(F)

m = MJ = grading coefficientm = ½ for abrupt junction

[AS, AD -> Source, Drain Areas in SPICE][CJ -> Cj0 in SPICE]

[PB -> O0 in SPICE]

[MJ -> m in SPICE]

+

n+n+N

D



, Csb

Assume Weff

= W


SUMMARY n+, p Junctions

C j 0V 1=AC j0

01, V80

1m=

0AS , AD1⋅CJ

01, VPB

1MJ (F)

(F/cm2)

Cj(0) = A Cj0 when V = 0

CJ=C j0=/ q4Si20N AN D

N A,N D1 180

[AS, AD -> Source, Drain Areas in SPICE][CJ -> Cj0 in SPICE]

[PB -> O0 in SPICE]

[MJ -> m in SPICE]

where SPICE Parameters


n+, p Junctions

EQUIVALENT LINEAR LARGE SIGNAL CAPACITANCE

C eq=2Q2V

=Q j 0V 21−Q j 0V 11

V 2−V 1=

1V 2−V 1

∫V 1

V 2C j 0V 1dV

C j 0V 1≈C eq=AC j0

V 2−V 1⋅

80

1−m[01,

V 2

8011−m

−01,V 1

8011−m

]

0 < Keq < 1 --> Voltage Equivalence Factorwhere V1 ≤ V ≤ V2

V = Ext Bias --> VSB, VDB for nMOS

C j 0V 1=AC j0K eq=0AS , AD1⋅CJ⋅K eq

VBS, VBD for pMOS

C j 0V 1=AC j0

01, V80

1m=

0AS , AD1⋅CJ

01, VPB

1MJ voltage

dependent

voltage independent

approximation

NOTE


K eq 0sw1=80sw

0V 2−V 1101−m0 sw11[01,

V 2

80sw11−m0 sw1

−01,V 1

80sw11−m0 sw1

]

m(sw) = ½ for an abrupt junction

[PS, PD -> Source, Drain Perimeters in SPICE][CJSW -> Cjsw in SPICE]

[PBSW -> O0SW in SPICE]

[MJSW -> m(sw) in SPICE]

[XJ -> xj in SPICE]

(F/cm2)

(F/cm)

C jsw0V 1=∣dQ jsw

dV∣=

PC jsw

01, V80sw

1m0sw 1=

0PS , PD1⋅CJSW

01, VPBSW

1MJSW (F)

C j 0V 1=∣dQ j

dV∣=

AC j0

01, V80

1m=

0AS , AD1⋅CJ

01, VPB

1MJ (F)

Recall for n+, p junctions


C jsw0V 1=∣dQ jsw

dV∣=

PC jsw

01, V80sw

1m0sw 1=

0PS , PD1⋅CJSW

01, VPBSW

1MJSW

where V1 ≤ V ≤ V2

V = Ext Bias --> VSB, VDB for nMOSVBS, VBD for pMOS

voltage dependent

voltage independent

approximation


4

CJ = 1.35 x 10-8 F/cm2

CJSW = 5.83 x 10-12 F/cmPB = 0.896 VPBSW = 0.975 VXJ = 1 x 10-4 cmMJ = MJSW = ½

n+ n+D S


CJ = 1.35 x 10-8 F/cm2

CJSW = 5.83 x 10-12 F/cmPB = 0.896 VPBSW = 0.975 VXJ = 1 x 10-4 cmMJ = MJSW = 1/2

C j 0V 1=AC j0K eq=AD⋅CJ⋅K eq

C jsw0V 1=PC jsw K eq0sw 1=PD⋅CJSW⋅K eq 0sw1

K eq 0sw1=PBSW

0V 2−V 1101−MJSW 1[01,

V 2

PBSW1

1−MJSW

−01,V 1

PBSW1

1−MJSW

]

K eq=PB

0V 2−V 1101−MJ 1[01,

V 2

PB11−MJ

−01,V 1

PB1

1−MJ

]

2⋅0.896V05V−0.5V 1

[01, 5V0.896V

11/2

−01, 0.5V0.896 v

11 /2

]=0.52=

= 2⋅0.975V05V−0.5V 1

[01, 5V0.975V

11 /2

−01, 0.5V0.975v

11/2

]=0.53≈K eq


CJ = 1.35 x 10-8 F/cm2

CJSW = 5.83 x 10-12 F/cmPB = 0.896 VPBSW = 0.975 VXJ = 1 x 10-4 cmMJ = MJSW = 1/2

C j 0V 1=AC j0K eq=AD⋅CJ⋅K eq=055 x 10−8cm21⋅01.35 x10−8F /cm21⋅0.52=3.86 fFC jsw0V 1=PC jsw K eq0sw 1=PD⋅CJSW⋅K eq 0sw1

02.5 x 10−3 cm1⋅05.83 x10−12F /cm1⋅0.53=7.72 fF=

Cdb=AD⋅CJ⋅K eq,PD⋅CJSW⋅K eq0sw 1=11.58 fF


Cgb

= COX WLeff

+ CGB0C

gd = (1/2) COX WL

eff + CGD0

Cgs

= (2/3) COX WLeff

+ CGS0

OXIDE CAPACITANCES

C j 0V 1=0AS , AD 1⋅CJ

01, VPB

1MJ ≈0AS , AD 1⋅CJ⋅K eq

C jsw 0V 1=0PS , PD1⋅CJSW

01, VPBSW

1MJSW ≈0PS , PD1⋅CJSW⋅K eq0sw1

DEPLETION CAPACITANCESC

sb = C

j(V

SB) + C

jsw(V

SB)

Cdb

= Cj(V

DB) + C

jsw(V

DB)

K eq=PB

0V 2−V 1101−MJ 1[01,

V 2

PB11−MJ

−01,V 1

PB1

1−MJ

]

K eq0 sw1=PBSW

0V 2−V 1101−MJSW 1[01,

V 2

PBSW1

1−MJSW

−01,V 1

PBSW1

1−MJSW

]

Assume: AS = AD

Assume: PS = PD

MOSFET CAPACITANCE SUMMARY

Leff

= LM

- 2LD


Short Channel Effects – Leff

→ xj

● Velocity saturation limit● Reduced electron, hole mobility● Reduced threshold voltage V

T0

Narrow Channel Effects – W → xdm

● Increased threshold voltage VT0

Sub-threshold Current – VGS

< VT0

● Non-zero drain current when VGS < VT0


7n 0eff 1≈7n0

1,50V GS−V T 1

v sat

I D 0sat 1=W v satCox 0V GS−V T 1

70=0cmsec

1/0Vcm

1=cm2

V sec

SHORT CHANNEL ISSUES

(Lvl 3)


n+ n+

pn+depletion

region

pn+depletion

regionVGS

induceddepletion

region

SG

D

n+ n+

SG

D

SHORT CHANNEL ISSUES - CONT.Short Channel Effect – L

eff → x

j (source, drain diffusion depth)

QB0

QB0(sc)

VT0

(short channel) = VT0

(long channel) - ΔVT0

V T00long channel 1=V FB−28F−Qox

C ox−QB0

CoxQ

B0(sc) << Q

B0

xj

Leff

Leff

22


Gate Extension design ruleW

NARROW CHANNEL ISSUES

Narrow Channel Effect – W → xdm

(depletion region depth)

gate-oxide field-oxidefield-oxide

V T00long channel 1=V FB−28F−Qox

C ox−QB0

Cox

QB0(nc)

QB0(nc)

> QB0


n≈1,4Si tox4ox t Si

sub-threshold swing coefficient:

[SPICE Parameter: N0 -> n sub-threshold swing coefficient

ID (sub-threshold) is leakage current for strong-inversion operation

NOTE:

ID (sub-threshold) is primary current for weak-inversion operation

I D 0 subthreshold 1=I S eV GSn kT /q 01−e

−∣V DS∣kT /q 101,6V DS 1

I S≈7CoxWL

0 kTq

2

1

+ J. Rabaey, A. Chandrakasan and B. Nikolic; Digital Integrated Circuits 2nd Edition, Prentice Hall, 2003, pp99.

+


(MOSIS: Level 3 model used for min feature size ≥ 1 µm)

(MOSIS: BISIM3 model used for min feature size < 1 µm)


EKV = Enz-Krummenacher-Vittoz (EKV) model is for low-power analog circuit simulation.

BSIM4v6.5 (2009)

Complexity of SPICE Models vs. Time

http://people.rit.edu/lffeee/Spice_Parameter_Calculator.XLSSPICE Parameter Calculator – Rochester Institute of Technology


Name Model Parameters Units LEVEL Model type (1, 2, or 3) L Channel length (designer input) mW Channel width (designer input) mLD Lateral diffusion length mWD Lateral diffusion width m

VTO Zero-bias threshold voltage VU0 Mobility cm**2/VsKP Transconductance A/V**2GAMMA Bulk threshold parameter V**1/2PHI Surface potential V LAMBDA Channel-length modulation 1/V (LEVEL = 1 and 2)

RD Drain ohmic resistance OhmsRS Source ohmic resistance OhmsRG Gate ohmic resistance OhmsRB Bulk ohmic resistance OhmsRDS Drain-source shunt resistance OhmsRSH Drain-source diffusion sheet Ohms/sq. ResistanceNRS Number of squares of RD, RS

IS Bulk p-n saturation current AJS Bulk p-n saturation/current area A/m**2PB Bulk p-n potential V

MOS SPICE MODEL PARAMETERS


Name Model Parameters Units LEVEL Model type (1, 2, or 3) CBD Bulk-drain zero-bias p-n cap (not used) FCBS Bulk-source zero-bias p-n cap (not used) FCJ Bulk p-n zero-bias bottom cap/area F/m**2CJSW Bulk p-n zero-bias perimeter cap/length F/mMJ Bulk p-n bottom grading coefficient MJSW Bulk p-n sidewall grading coefficient FC Empirical bulk p-n forward-bias cap coefficientCGSO Gate-source overlap cap/channel width F/m CGDO Gate-drain overlap cap/channel width F/m CGBO Gate-bulk overlap cap/channel width F/m NSUB Substate doping density 1/cm**3NSS Surface-state density 1/cm**2NFS Fast surface-state density 1/cm**2TOX Oxide thickness m TPG Gate material type:

+ 1 = opposite of substrate, - 1 = same as substrate, 0 = aluminum

XJ Metallurgical junction depth m

MOS SPICE MODEL PARAMETERS - CONT.


Name Model Parameters Units LEVEL Model type (1, 2, or 3) UCRIT Mobility degradation critical field V/cm

(LEVEL=2) UEXP Empirical mobility degradation exponent (LEVEL=2) VMAX Maximum carrier drift velocity (Level=2) m/sNEFF Empirical channel charge coefficient (LEVEL=2) XQC Empirical Fraction of channel charge attributed to drain (Level=2)DELTA Empirical channel width effect on V

T

THETA Empirical mobility modulation (LEVEL=3) 1/V ETA Empirical static feedback on V

T (LEVEL=3)

KAPPA Empirical saturation field factor (LEVEL=3) KF Flicker noise coefficient AF Flicker noise exponent

MOS SPICE MODEL PARAMETERS - CONT.


KP (in A/V2) = k'n (k'

p)

VT0 (in volts) = VTn

(VTp

)U0 (in cm2/{Vs}) = µ

n (µ

p)

Level 3 SPICE Parameters

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ESE 570 MOS TRANSISTOR THEORY – Part 2ese570/spring2015/ESE... · THEORY – Part 2 GCA (gradual...

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