AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 1/36
Evaluation of the AMS 0.35 µm CMOS Technology for Use in Space Applications
J. Ramos-Martos(1, A. Arias-Drake(2, A. Ragel-Morales(1, J. Ceballos-Cáceres(1, J. M. Mora-Gutiérrez(1, B. Piñero-García(2, M. Muñoz-Díaz(2, M. A. Lagos-Florido(1, S. Sordo-Ibáñez(2, S. Espejo-Meana(1,2
1)Instituto de Microelectrónica de Sevilla - Centro Nacional de Microelectrónica - Consejo Superior de Investigaciones
Científicas (IMSE) Avenida Américo Vespucio, s/n; Sevilla, Spain
2)Departamento de Electrónica y Electromagnetismo – Universidad de Sevilla (US)
Avenida Américo Vespucio, s/n; Sevilla, Spain
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 2/36
AMS 0.35 µm CMOS for Space Applications
Introduction The Characterization Plan
Low-Temperature Characterization
Equivalent Width for ELTs
TID Characterization
SEE Characterization
Conclusions and Future Work
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 3/36
Introduction Application of IMSE and US Mixed-Signal Design expertise to space
ASICs • Collaboration with Instituto Nacional de Técnica Aeroespacial (INTA)
started in 2008 • Selection of technology from an European foundry (AMS 0.35µm)
– Mature, reliable, long-life (automotive market) – Reduced prototyping and low-volume production cost – Suitable for moderate performance MS designs
• Start from the ground (technology evaluation and characterization)
Design, then try to see what happens….. or See what happens, then design!
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 4/36
Introduction
The Characterization Plan Low-Temperature Characterization
Equivalent Width for ELTs
TID Characterization
SEE Characterization
Conclusions and Future Work
AMS 0.35 µm CMOS for Space Applications
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 5/36
Objectives
Test Chips
Test Hardware
Test Software
Test Facilities
The Characterization Plan
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 6/36
Objectives
Evaluation • At low-temperature (-110ºC) • Radiation (TID, SEE)
Development • Models of Enclosed-Layout Transistors • RHBD Digital Library
Application • Two instrumentation chips for Mars missions • Future use in internal projects and in collaboration with other
interested groups
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 7/36
Test Chips (1)
•Geometry
•Temperature
•TID
•SEUs & SETs
•Latch-Ups
CHIP#1
CHIP#2
CHIP#3
MOS Transistors Bipolar Transistors Resistances Diodes Ring Oscillator Shift Registers Latch-Up Structures
Library Cells Shift Registers Combinational Logic
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 8/36
Test Chips (2) – CHIPS #1 & #2
CHIP#1 with five multiplexed arrays of 4 x
4 CMOS transistors
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 9/36
Test Chips (3) – Muxed Arrays MUX-D connects to DRAIN the drains of all transistors in its column, other columns have its drain open; MUX-S connects to SOURCE the source of all transistors in its column, other columns have its source to BULK; MUX-G connects to GATE the gates of all transistors in its row, other rows have its gate to BULK (GND (NMOS) or to VDD (PMOS)). SOURCE, GATE and DRAIN are connected externally to the measuring equipment.
RADIATE sets all transistors with gate to VDD and all other terminals grounded.
MUX-D
MUX-G
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 10/36
Test Chips (4) – CHIP#3
Dedicated to evaluation of SEU, SET and SEL in standard and RHBD digital cells.
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 11/36
Temperature & TID Characterization
Hardware
Switch Matrix Board
Connects measurement lines and stores the configuration bits for control of DUT.
PC
•Programming of configuration register
•Control of HP 4155A (test configuration, execution & data trace)
•Output-data local storage
•Test Automation
HP 4155A Semiconductor Parametric Analyzer
•Stimuli generation
•Output data sampling
ASIC board
Placed inside climatic chamber for controlled-temperature tests
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 12/36
SEE Characterization Hardware
ASIC board
ADCs to detect and resolve over-current in supply lines due to latch-ups
FPGA monitors SEU, SET & Latch-Up events and resets power lines if neccessary
Monitors up to six different supplies
PC
•Periodically reads SEU, SET & Latch-Up totals from the FPGA
•Output-data local storage
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 13/36
Postprocessing Software
Raw data visualization
Parameter extraction
Graphical data comparison among tests performed in different conditions
Export selected data to text files
MATLAB scripts
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 14/36
Data Post-processing
Raw data is compensated for: • Voltage drop in multiplexer switches • Body-effect due to increase in source voltage • Leakage currents in input pads and multiplexers
CMOS Parameters Extracted: Vth (linear (Vds=Vgs) and saturation (Vds=0.1 V)) Subthreshold leakage current Gain Factor (KP) Body effect Saturation current
Dint
Sint
BulkGate
Rsw
Rsw
Dext
Sext
ID
IS
ILD
ILD
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 15/36
Test Facilities
Low-Temperature • Instituto de Microelectrónica de Sevilla • Instituto Nacional de Técnica Aeroespacial (INTA)
TID • Laboratorio de Radiofísica – Univ. de Santiago de Compostela
SEE • Centre de Ressources du Cyclotron – Louvain-la-Neuve • Centro Nacional de Aceleradores - Sevilla
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 16/36
AMS 0.35 µm CMOS for Space Applications
Introduction
The Characterization Plan
Low-Temperature Characterization Equivalent Width for ELTs
TID Characterization
SEE Characterization
Conclusions and Future Work
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 17/36
Operation at Low Temperature
Instruments located in the outside of the main spacecraft body (masts, booms) have to stand temperatures below the range characterized by the foundries.
• Alternatives: – Heat the ASIC to keep it within the standard temperature range (complex
assembly and high power consumption) – Characterize the behaviour at lower temperatures, adapt the models if
needed, and take extra margins in the design.
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 18/36
Low Temperature Measurements
IMSE • Down to -55ºC using
Thermonics T-2650BV
INTA • Down to -110ºC using SUN
Systems liquid N2 cooled thermal chamber.
Low-Temperature (-110ºC) setup at INTA
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 19/36
Low Temperature Results
-110 -90 -70 -50 -30 -10 10 30 50 70
Resistances
RPOLY1RPOLY2RPOLY2PHRDIFFNRDIFFP
Temperature [ºC]
Res
ista
nce
[Ohm
]
-110 -90 -70 -50 -30 -10 10 30 50 700,40
0,45
0,50
0,55
0,60
0,65
0,70NMOS - 3.3V
Temperature [ºC]
Vth
[V]
Temperature dependence do not show unexpected behaviour beyond the range guaranteed by the foundry (-40ºC)
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 20/36
AMS 0.35 µm CMOS for Space Applications
Introduction
The Characterization Plan
Low-Temperature Characterization
Equivalent Width for ELTs TID Characterization
SEE Characterization
Conclusions and Future Work
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 21/36
Equivalent Width for ELTs
W3
W2
W
L3 L
2
L
d) Annular
a) Standard c) Double Ringed-Source
b) Ringed-Source
Accounts for extra S-D current by an effective width Weff • For Ringed-Source:
• For Double-Ringed Source:
⋅
+⋅
+⋅⋅+=3
3
2
2
432
2LWn
LWLWW c
eff
⋅
+
+⋅⋅+=3
3
2
2
65
4LWn
LWLWW c
eff
• Incorporated in transistor models and extraction tools.
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 22/36
AMS 0.35 µm CMOS for Space Applications
Introduction
The Characterization Plan
Low-Temperature Characterization
Equivalent Width for ELTs
TID Characterization SEE Characterization
Conclusions and Future Work
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 23/36
TID Tests Three TID Test Campaigns
• CHIP#1, preliminary test, 1 day, 65 krad(Si) • CHIP#1, 4 samples, 9 days, 350 krad(Si)
– From 0.02 rad/s to 2.5 rad/s, doubling at each step. – Annealing 6 weeks @RT, 84 hours @ 100ºC unbiased, 84 hours @ 100ºC
biased.
• CHIP#2, 4 samples, 6 irradiation steps of 42 hours each, reaching 1Mrad(Si) over 6 weeks, with delayed measurements.
– From 0.5 rad/s to 2 rad/s, increasing by 1.33 at each step. – Annealing 16 days @RT -> 95 hours @ 100ºC unbiased -> 73 hours @
100ºC unbiased.
• Irradiations performed at Laboratorio de Radiofísica (USC, Spain)
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 24/36
Irradiation CHIP#1 – NMOS/M
0 50 100 150 200 250 300 350-50
-40
-30
-20
-10
0
10
20
30
40
50TID - Delta_Vth - NMOS/NMOSM
NMOS-LongNMOSM-LongNMOSM-ShortNMOS-Short
TID [krad(Si)]
Del
ta_V
th [m
V]
Drift inmediately after irradiation negligible for thin-oxide gates. More significant for thick-oxide with short length Leakage important for short transistors. Negligible effect for long transistors with thin-oxide.
0 50 100 150 200 250 300 3501E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5TID - D_S Leakage - NMOS/NMOSM
NMOSM-ShortNMOS-ShortNMOSM-LongNMOS-Long
TID [krad]IL
DS
[A/u
m]
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 25/36
Annealing CHIP#1 – NMOS/M
0 10 20 30 40 50 60 70-90
-70
-50
-30
-10
10
30
50
70
90Annealing - NMOSM - Delta_Vth
Long (Avg)Short (Avg)Long (Worst)Short (Worst)
Time [Days]
Del
ta_V
th [m
V]
Irradiation: Days 0 to 9 (up to 350 krad(Si)) Annealing: Day 47, 6 wk @ RT; Day 54, 70h @100ºC unbiased, Days 61/ 63/ 64/ 69, after 90/ 112/ 133/ 157 hours @ 100ºC biased
0 10 20 30 40 50 60 701E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5Annealing - D_S Leakage - NMOS/NMOSM
NMOSM-ShortNMOS-ShortNMOSM-LongNMOS-Long
Time [days]
ILD
S [A
/um
]
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 26/36
Ids vs. Vgs – NMOS/M (0-1Mrad) – CHIP#2
0 0,2 0,4 0,6 0,8 1 1,2 1,41E-12
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03NMOSM, L=0.5, 0 - 1010 krad
w1/0.5 - 0 kradw1/0.5 - 1010 kradw2/0.5 - 0 kradw2/0.5 - 1010 kradw3/0.5 - 0 kradw3/0.5 - 1010 kradRw2/0.5 - 0 kradRw2/0.5 - 1010 kradRw3/0.5 - 0 kradRw3/0.5 - 1010 krad
Vgs = Vds [V]
Ids
[A]
0 0,2 0,4 0,6 0,8 1 1,2 1,41E-12
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02NMOS, L=0.35, 0 - 1010 krad
w1/0.35 - 0 kradw1/0.35 - 1010 kradw2/0.35 - 0 kradw2/0.35 - 1010kradw3/0.35 - 0 kradw3/0.35 - 1010 kradw4/0.35 - 0 kradw4/0.35 - 1010 kradw5/0.35 - 0 kradw5/0.35 - 1010 kradRw4/0.35 - 0 kradRw4/0.35 - 1010 kradRw5/0.35 - 0 kradRw5/0.35 - 1010 krad
Vgs = Vds [V]
Ids
[A]
Irradiation: 6 weekly steps of 42 hours each (up to 350 krad(Si)) Thin-oxide (NMOS): Little effect for standard layout, negligible for ringed layout Thick-oxide (NMOSM): Increase in zero bias leakage for standard transistors. Increased subthreshold swing in all types.
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 27/36
Dependence on Transistor Dimensions
0 1 2 3 4-120
-100
-80
-60
-40
-20
0
20
40Annealing NMOSMB
0.4/0.5 2.1/0.5 4/0.5 R2.12/0.5R4/0.5 0.8/1 2.10/1 4/1R2.12/1 R4/1 2.10/3 4/3R2.12/3 R4/3
Step
dVth
[mV]
∆Vth for thick-oxide NMOS after: 1) 1 Mrad(Si); 2) 16 days @25ºC; 3) 95 hours @ 100ºC; 4) 168 hours @ 100ºC Note clustering on transistor length: 0.5µm (red); 1µm (green); 3µm (blue); and stronger effect for narrow transistors
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 28/36
Comparison of Irradiation Campaigns
Comparison made using transistors of similar dimensions.
Upward shift of ∆Vth for NMOSM and PMOSM transistors in second TID test (up to 1 Mrad). Probably due to longer time between irradiation steps, combined with faster annealing of oxide charges (Not) than interface charges (Nit).
0 200 400 600 800 1000 1200-70
-60
-50
-40
-30
-20
-10
0
10NMOSM
2.1/0.5 1p65-0p5
TID [krad(Si)]
d_V
th [m
V]
0 200 400 600 800 1000 1200-100
0
100
200
300
400
500
600PMOSM
0.4/2 0p4-10
TID [krad(Si)]
d_V
th [m
V]
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 29/36
AMS 0.35 µm CMOS for Space Applications
Introduction
The Characterization Plan
Low-Temperature Characterization
Equivalent Width for ELTs
TID Characterization
SEE Characterization Conclusions and Future Work
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 30/36
SEE Tests
Eight-hours beam time using Heavy-Ion Cocktail #1 of Cyclone-UCL
• Normal incidence, room temperature.
• Measurements on 2 samples
Ion LET [MeV·cm2/mg]
DUT Energy[MeV]
Range [µm (Si)]
15N3+ 3.3 60 59 20Ne4+ 6.4 78 45 40Ar8+ 15.9 151 40 84Kr17+ 40.4 305 39
124Xe25+ 67.7 420 37
LET [MeV·cm2/mg]
Fluence [1/s·cm2] Standard Ringed Enclosed DICE
6.4 5.6·107 3 0 0 0
15.9 2.8·107 178 1 0 0
40.4 7.5·106 233 127 15 0
67.7 5.5·106 617 179 104 4 SEU Errors
Ion Cocktail #1
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 31/36
SEU & Latchup Results
0 10 20 30 40 50 60 701E-7
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
StandardRingedEnclosedDICEWeibull-StandardWeibull-RingedWeibull-Enclosed
LET [MeV/mg/cm2]
SEU
Prob
abili
ty
0 10 20 30 40 50 60 701E-7
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
LET [MeV/mg/cm2]
Latc
h-up
Pro
babi
lity
SEU Lth [MeV·cm2/mg] / σsat [cm2]
Standard: 5.5 2.8·10-6
Ringed: 16.0 3.3·10-7
Enclosed: 35.0 1 9·10-7
Latch-Up Lth [MeV·cm2/mg] / σsat [cm2]
Standard: 9 1.1·10-5
RHBD: > 67.7 ?
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 32/36
AMS 0.35 mm CMOS for Space Applications
Introduction
The Characterization Plan
Low-Temperature Characterization
Equivalent Width for ELTs
TID Characterization
SEE Characterization
Conclusions and Future Work
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 33/36
Summary of Tests CHIP#1
Temperature: -50, -25, 0, 25, 50, 75 ºC @ IMSE Temperature: -50, -70, -90, -110 ºC @ INTA TID: 1.15, 3.7, 8.9, 19.4, 40, 81, 167, 326, 366 krad(Si) @ USC SEE: N, Ne, Ar, Kr, Xe @ UCL Annealing @ IMSE
CHIP#2 Temperature / -50, 25, 100 ºC @ IMSE TID / 75, 175, 305, 480, 710, 1010 krad(Si) @ USC Annealing @ IMSE
CHIP#3 SEE: @ UCL (scheduled for October 2012)
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 34/36
Conclusions
Temperature Behaviour down to -110ºC in good agreement with the prediction of the standard foundry models.
TID Vth drift low (< 30 mV @ 300 krad(Si)) for thin-oxide transistors. Vth drift moderate (+180mV PMOSM, -30mV NMOSM @ 300 krad(Si)) for thick-oxide transistors Ringed-source layout is effective in reduction of TID induced S-D leakage in NMOS.
SEE SEU Lth [MeV·cm2/mg]: 5.5 (standard); 16 (ringed-source); > 68 (DICE) Latch-Up Lth [MeV·cm2/mg]: 9 (standard); > 68 (RHBD layout)
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 35/36
Future Work
RHBD Digital Library • Perform SEE Tests • Improve cell layout and add more cell types
Analog • Model dependence of Vth with radiation and transistor dimensions • Characterize bipolar devices for displacement damage using
proton source at CNA
AMICSA 2012
Evaluation of AMS 0.35mm CMOS for Space Applications
Universidad de Sevilla / IMSE-CNM 36/36
Thank you for your attention!