EVOLUTION OF VOLTAGE REGULATOR TO … · Low Drop out (CL-LDO) Voltage Regulator, since CL-LDO...

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International Journal of Advanced Research in Engineering and Technology

(IJARET) Volume 6, Issue 8, Aug 2015, pp. 42-56, Article ID: IJARET_06_08_005

Available online at

http://www.iaeme.com/IJARET/issues.asp?JTypeIJARET&VType=6&IType=8

ISSN Print: 0976-6480 and ISSN Online: 0976-6499

© IAEME Publication

___________________________________________________________________________

EVOLUTION OF VOLTAGE REGULATOR

TO SYSTEM ON CHIP APPLICATIONS

ANOOP KIRAN

Department of Telecommunication Engineering

Siddaganga Institute of Technology,

Tumakuru–572103, Karnataka, India

ABSTRACT

People demanding for smaller hand-held devices is increasing because of

the growing applications within these portable System on Chip (SoC)

applications, such as cellular phones, tabs, laptops, etc... Consequently

industry is also pushing towards miniaturization. New technologies are

emerging to make device smaller and smaller, by decreasing transistor length

only to few nano-meters. During the journey of miniaturization, voltage

regulator is being a key factor of discussion for SoC applications from many

years. Researchers have been working constantly to formulate a design for

voltage regulators. Many compensation methods have been emerging from

last two decades to overcome problems associated with precursor technique.

This paper insights the pathway which leads to development of Capacitor-Less

Low Drop out (CL-LDO) Voltage Regulator, since CL-LDO architecture is the

most suitable architecture for System on Chip applications.

Index Terms: Dropout voltage, Quiescent current, Miller capacitor,

Differential amplifier, Trans-conductance amplifier, Line regulation, Load

regulation, Line transient, Load transient, fast path, transient compensation,

Die area.

Cite this Article: Anoop Kiran. Evolution of Voltage Regulator to System on

Chip Applications. International Journal of Advanced Research in

Engineering and Technology, 6(8), 2015, pp. 42-56.

http://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=6&IType=8

_____________________________________________________________________

I. INTRODUCTION

Voltage regulator is one of the fundamental and essential parts of power management

system. Power management design is becoming a more frequent and challenging task

for system designers. The study of power management techniques has increased

spectacularly within the last few years corresponding to a vast increase in the use of

portable, handheld battery operated devices [1]. Voltage regulators are of two types:

Evolution of Voltage Regulator to System on Chip Applications


switching regulator and linear regulator. Switching regulator is having good

efficiency but it is having complex structure for design and it is more costly than

linear regulator [2]. Whereas in case of linear regulator, despite the fact of lesser

efficiency, it is most widely evolved because of reduction in cost, size, noise and

complexity; all of which helps to implement on SoC devices [3], [4]. First of all, let us

have a look how does a particular technique derived for designing of voltage

regulator. Observing the figure-1 indicates that it consists of a voltage divider circuit

followed by a 12V supply, which is then fed to an op-amp for driving purpose.

Considering basic methodology as used in figure-1, experiment results shows that,

this will not give a constant voltage all times and also have some limitations. First of

all if the 12V (input) supply voltage is not regulated properly supply to op-amp will

not be a constant voltage and second, if other op-amp demands different voltage then

this circuit is no longer used. These two drawbacks proved that this technique will

not be efficient in all variable condition and hence it does not serve for regulating

purpose.

Figure 1 A voltage divider circuit to drive an op-amp, which was experimented earlier to

check whether it gives a constant voltage

II. VOLTAGE REGULATOR BLOCK

Considering drawbacks of voltage divider regulator in mind scientists have developed

a new configuration, which is based on feedback system. Feedback means taking

some part of output and utilizing that to regulate the output voltage to a constant

value. Generally, from the output node feedback is taken because that is the point of

interest where a constant voltage has to be achieved. Series of efforts finally leads to a

system which defines the regulator properly as shown in Figure-2.

Figure 2 A block diagram of voltage regulator with all its components

Block diagram consists of three important components: a feedback circuit, an

error amplifier and a pass element. Feedback circuit is the voltage divider circuit

which helps to send the change in output signal as feedback thus helps to prevent the

Anoop Kiran


reflection at output node to change in input node. Voltage divider circuit is made up

of two resistors in series. The resistor values are selected to give the voltage that

required to error amplifier. We can also limit the amount of Quiescent current by

proper selection of resistor values [4].

A high gain multi-stage amplifier is used as the error amplifier, with a stable

voltage reference fed to one of its inputs. The voltage reference is usually derived

from a band gap reference circuit [5], [6]. Since the gain obtained by differential

amplifier is less, the output of the differential stage is given to common source

amplifier to achieve appreciable gain [7].

Figure 3 CMOS transistor structure of Error amplifier

CMOS circuit architecture of error amplifier is as shown in Figure-3 where it

consists of two stages [7]. First stage is an active loaded differential amplifier which

constitutes M1 to M5 transistors and M8 used to mirror the current. Second stage

consists of M7 and M6 which is a high trans-conductance amplifier which helps to

increase the gain. Cc is Miller capacitor added to improve frequency response [7].

The third and most important part of voltage regulator is pass element selection which

will be discussed in upcoming section.

The input voltage is applied to a pass element. The pass element operates to drop

the input voltage down to the desired output voltage. The resulting output voltage is

sensed by the error amplifier and compared to a reference voltage. The error amplifier

drives the pass element to the appropriate operating point to ensure that the output is

at the required constant voltage. As the operating current or input voltage changes, the

error amplifier modulates the pass element to maintain a constant output voltage.

Under steady state operating conditions, an LDO behaves like a simple resistor.

III. PASS ELEMENT SELECTION

Few important factors considered during selection of pass element are dropout

voltage, ground current, noise and input power loss. For SoC applications, there are

two basic factors that should be considered while selecting pass elements: dropout

voltage and ground current. Low ground current and low dropout voltage are required

to have more efficient voltage regulator [8]. So, it is pretty clear that pass element’s

drop-out voltage and ground current is directly related to efficiency of the regulator

[8], [9].

Lesser the dropout voltage is more the efficiency, therefore we need to search

for low drop-out pass element. Now the task is to which pass element has to be

selected, it cannot be a simple two terminal device diode, as current can’t controlled

in diode. Successor of diode is sandwiching two diodes that is transistor so; Bipolar



Junction Transistor (BJT) was first selected and implemented. For the period up to the

birth of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), it seems to

be good, but MOSFET advantages ruled out the use of BJT for many applications.

Advantages of MOSFET over BJT are shown in Table-1.

Table 1 Advantages of MSOFET over BJT.

BJT MOSFET

Input power loss >0 (IB>0) 0 (IG=0)

Dropout voltage More Lesser than BJT

Noise More Less

Fabrication area More Less

Total power loss More Lesser than BJT

Thermal Runaway Present Absent

The difference between these is how the pass element is driven. A BJT pass

element is a current-driven device, whereas the MOSFET is a voltage driven device.

As we know there are two types of transistors: N-type and P-type. N-type devices

require a positive drive signal with respect to the output, whereas P-type devices are

driven from a negative signal with respect to the input. Generating a positive drive

signal becomes more power requirement and less efficient. As a result, LDOs that

operate from low input signal typically are implemented with P-type devices. So,

either PNP type BJT or PMOS can be selected. Figure-4 shows the comparison of

Dropout voltage between PNP type BJT and P-type MOSFET [10].

Figure 4 Comparison of Dropout voltage of PNP LDO and PMOS LDO, which shows

Dropout voltage of PMOS LDO lesser than PNP LDO.

Graph in Figure-4 shows that Dropout voltage of PMOS LDO lesser than PNP

LDO. In lower-current applications, PMOS LDOs typically have a lower dropout

voltage than that of PNP LDOs. The result cogently proves that PMOS can be used to

increase efficiency; thereafter voltage regulator is termed as Low Drop-Out (LDO)

Regulator.

Ground current is the amount current flowing when current to the load becomes

zero. During this scenario, Pass element’s current is significantly higher than any

other component’s currents in LDO regulator. Now we shall have a look through

Anoop Kiran


collector current expression of BJT and drain current expression of MOSFET is as

shown in Eq- 1 and Eq- 2 respectively.

BEC S

VI I exp

VT

(1)

IC=Collector current Is=Saturation current

VBE=Base to emitter voltage VT=Thermal Voltage

21( )

2D ox GS Th

wI µ C V V

l

(2)

ID=Drain current µ =Mobility of charges

Cox=Oxide Capacitance W & L=Width & Length

VGS=Gate to Source Voltage VTh=Threshold voltage for MOSFET

Collector current variation of BJT is exponentially related to Base voltage,

whereas in MOSFET drain current is quadratic function of gate voltage. These

observations suggest that ground current after transistor reached ON state for BJT is

more than MOSFET.

We know that BJT is current driven device. As the load requires more current it

has to be provided by driving current at the base of transistor. So base current also

increases automatically. This additional base current constitutes ground current as

shown in figure-5(a).

(a) (b)

Figure 5 Current flow Comparison: (a) PNP-type BJT (b) P-type MOSFET, from which we

can be observed that ground current of P-type MOSFET is lesser than PNP-type BJT.

In case of MOSFET as it is voltage driven device, current required by load is

provided by increasing voltage at gate terminal. There is isolation between gate and

other two terminal for flow of charges, as capacitive action takes place in MOSFET to

drive. Hence there is no gate current here as shown in figure-5(b). So, comparatively

MOSFET losses lesser ground current than BJT does. Figure-6 clearly illustrates that



as load current increases PNP LDO losses more ground current than PMOS LDO

[10].

Figure 6 Comparison of Ground current of PNP LDO and PMOS LDO, which shows ground

current of PMOS LDO lesser than PNP LDO.

Two important advantages of MOSFET, namely, low dropout voltage and low

ground current will successfully replace the pass element from BJT to MOSFET. In

addition to these two advantages, MOSFET is also free from the problems such as

Thermal runaway, more noise and more fabrication area which BJT is suffering

from. Lesser fabrication area of MOSFET is most significant advantage over BJT,

which helps to increase fabrication technology and to make device size smaller as it is

a most important requirement of SoC applications [11].

IV. LDO VOLTAGE REGULATOR CIRCUIT

LDO Voltage regulator is having three important components. They are Pass element

as P-type MOSFET, Feedback circuit as voltage divider circuit having two resistors in

series and error amplifier as Multi-stage differential amplifier. Transistor level circuit

diagram taken from cadence tool is as shown in Figure-7.

Figure 7 Transistor level circuit diagram of LDO Voltage regulator.

Anoop Kiran


Having with some pre-assumptions and design equations, we can determine the

dimension of all transistors shown in Figure-7. This section explains the design of

LDO regulator for output voltage of 2.8V for a maximum current of 50mA and

having a dropout voltage equal to 200mV. Before going to design it is required to go

through the symbols given with parameters name shown in Table-2.

Table 2 Symbols with appropriate parameters

Symbol Parameter

Name Symbol

Parameter

name

gm Transconductance of a MSOFET CL Load Capacitance

ADC DC Voltage gain VDSat Saturation voltage

VOV Overdrive voltage CC Compensation capacitance

IQ Ground current via R1 & R2. VREF Reference voltage at error

VOUT Desired Output voltage at the

end VDropout

Dropout voltage of pass

element

VDS Drain to source voltage IDmax Maximum drain current

BWG gain bandwidth (3)

2m

BW

L

gG

C

(4)

(Slew Rate) LI C (5)

2 m D n ox

wg I µ C

l

(6)

21( )

2D ox GS Th

wI µ C V V

l

(7)

= OV GS ThV V V (8)

DS OVV V (9)

6 66

4 4

4

m

m

w

I gl

w I g

l

(10)



77

5

5

w

Il

w I

l

(11)

Design of Dimension of all MOSFETs starts from assuming some parameters

such as gain, bandwidth and load capacitance. Then it follows to calculate gm (Eq-4),

ID (Eq-5), and Dimensions of M1-M4 by using basic design equation of MOSFET (Eq-

6 to Eq-9). Second stage of error amplifier is needed to be designed to have high

trans-conductance to amplify signal coming from first stage differential amplifier.

Since, M6 is biased by gate voltage of M4, Eq-10 helps to determine the dimension of

M6. M8 is replica of M5 since it helps in mirroring current to M5. M7 dimensions can

be deduced by taking current flow in M6 and using Eq-11, as it is biased by M5. All

dimension of are tabulated in Table-3.

Table 3 Dimension of all MOSFETs and drain current flow

MOSFETs Width (µm) Length (µm) ID (µA)

M1 2.5 0.5 2.5

M2 2.5 0.5 2.5

M3 2.5 0.5 2.5

M4 2.5 0.5 2.5

M5 4.4 0.4 5

M6 40 0.4 200

M7 44 0.4 200

M8 4.4 0.4 5

Pass element 15120

(50µ×303) 0.4 50000

Pass element dimensions can be determined by Eq-12, followed by pre-assuming

dropout voltage of 200mV across it. Feedback circuit values can be calculated by

using Eq-13 and Eq-14 by knowing value of Reference voltage.

max

2

2 D

n ox DSat

w I

l µ C V

(12)

max

2 1

OUTD

VI

R R

(13)

2

2 1

REF OUT

RV V

R R

(14)

0.22C LC C (15)

Compensation capacitance value can be determined by Eq-15. This equation is

derived by solving and simplification transfer function of error amplifier followed by

pre-assuming phase margin of 60º. All the remaining parameter values are tabulated

in Table-4.

Anoop Kiran


Table 4 Value of all other components in LDO Regulator

Parameter Value

VOUT 2.8 V

IQ 5 µA

COUT 100 µF

ROUT 560 KΩ

ADC ≥50 dB

R1 312 KΩ

R2 248 KΩ

IDmax 50 mA

VREF 1.24 V

Design of LDO regulator is implemented in cadence tool and simulated to observe

the voltage regulation for wide range of input voltage. Then it is tested for Line

Regulation giving linear input voltage from 0-10V as shown in Figure-8, which shows

that output voltage remains constant at 2.8V. Output voltage remains constant after

input reaching 3V, irrespective of increase in input voltage. Load regulation is

observed by introducing a ramp current starting from 0-10A as shown in Figure-9,

which shows voltage regulated at 2.8V up to maximum current of over 600mA.

In spite of proper regulation been achieved in the LDO voltage regulator circuit, it

suffer from many limitations [12]. One of the most important problems is the size of

load capacitor (100 µF) connected to achieve good transient response. This increases

the die area required to fabricate an enormously large capacitor, which is a very big

problem associated to implement for SoC applications. When capacitor is removed

and tested with transient analysis which found to give irregular and undesirable

results. This can be proved by subjecting LDO regulator to transient response after

removing load capacitor. In order to overcome this issue many solutions have been

presenting by scientists [13]. Before going to solutions, let’s analyse the problem with

the absence of capacitor.

Figure 8 Line regulation: VIN Ramped from 0-10V, output voltage remains constant at 2.8V

after input voltage reached 3V.



Figure 9 Load Regulation: ILOAD Ramp is given from 50mA-1A, even then also output

voltage remains constant at 2.8V up to 688mA.

Huge capacitor, if present will help to store charges which will be used to deliver

to output whenever necessary. When load demands a step current, this huge amount

of instantaneous charges are supplied by capacitor as shown in Figure-10. Thus it

helps to provide some time for regulating loop thereby to provide required amount of

current by pass transistor [14]. In this case, transfer of charges from capacitor to load

corresponds to voltage drop variation at the output, hence violating rule of constant

output voltage. If capacitor is absent output voltage will not settle down for constant

value; instead, it keeps on varying continuously. Referring to Figure-11; in absence of

load capacitor, practically current demanded by load is as shown in lower graph and

oscillating output voltage which never settles down due to absence of capacitor shown

in upper graph. The same problem will also occur when input (Line) voltage is varied

since there is no time given for loop to react for change in input voltage, as shown in

Figure-12. Hence there exist big problem during fast transient of load current and line

voltage.

Figure 10 Capacitor releasing charges during step load current demand by load, hence giving

some time for regulation to happen.

Anoop Kiran


Figure 11 Load Transient: In absence of capacitor variation of output voltage for

instantaneous variation of load current, which does not settle down to a constant value

Figure 12 Line Transient: In absence of capacitor variation of output voltage for

instantaneous variation of input voltage, which does not settle down for a constant value.

The absence of large external output capacitor presents design challenges for load

transient response and also to AC response [14]. Removing the external capacitor

requires a sound compensation scheme for the transient response. This idea paved

way into the development of different compensation methods to overcome many

problems. One among them is presented in next section.

V. CAPACITOR-LESS LDO VOLTAGE REGULATOR WITH

COMPENSATION

Considering the drawback in transient response of previous structure, and then come

up with a solution by adding compensation circuit as shown in Figure-13.

Compensation circuit provides sufficient time for loop to regulate by providing fast

path for the flow of charges for a sudden demand of charges occurred at the load [15].



Figure 13 Block diagram of CL-LDO voltage regulator with compensation.

Transistor level diagram of CL-LDO with compensation circuit is as shown in Figure-

14 and parameter values are tabulated in Table-5 [15]. One extra capacitor is added in

compensation circuit which is of only few Pico-Farads which can be easily fabricated

in small area of chip. Researchers found a technique that even though capacitor value

is small, it can act as a bigger basin for the storage of charges within it. This can be

analysed by using Eq-16. Where gm,eff is total trans-conductance value offered by M9

and M10. Cf,total is total capacitance value. This equation can be derived by solving

transfer function of each of compensation circuit.

, ,f total m eff f fC g R C (16)

Figure 14 Transistor level diagram of CL-LDO voltage regulator taken from Cadence tool.

Careful observation of Eq-16 clearly shows that capacitor value is multiplied by

two factors: Resistance Rf and gm,eff. This technique surely helps to have a bigger

capacitor and hence more charges can be stored easily. These charges play role during

transient analysis giving time for loop to regulate.

Anoop Kiran


Table 5 Parameter value of compensation circuit

Parameter Value

IREF 10 µA

Rf 200 KΩ

Cf 2 pF

M9 L=0.4µm, W=1µm

M10 L=0.4µm, W=3µm

M11 L=0.4µm, W=3µm

M12 L=0.4µm, W=1µm

After having implemented the design in cadence, circuit is tested for transient

performance. It is subjected to a line transient of 3–5V and 5-3V with 0.5 µs rise and

fall times, as shown in Figure-15. An extra ringing, less than ±5 mV was experienced

at output, but the ringing quickly gets stable value within 4µs in the worst case. Then

circuit is subjected to load Transient by introducing a step load current from 5-50mA

and 50-5mA with 2 µs rise and fall times, as shown in Figure-16, which shows there

is only ±2mV ringing which settle down quickly in 4 µs. In addition to solving

transient response problem this architecture also solves AC response problem hence

can be implemented in SoC applications [15].

Figure 15 Line Transient Response: VIN varying from (a) 3-5V (b) 5-3V. Output voltage

settled down to 2.8V very quickly within 4 µs.

Figure 16 Load transient response: (a) 5-50mA (b) 50-5mA. Output voltage settled down to

2.8V very quickly within 4 µs.



VI. CONCLUSION

Voltage Regulator characteristics and requirements of SoC applications are discussed

in this paper. Architecture of basic voltage regulator is introduced, considering the

drawbacks of voltage divider circuit. Designing of each components of voltage

regulator is provided. Selection of most important component-Pass element is

presented with considering required characteristics such as less power loss, less

Fabrication area and low Noise. Finally structure of CL-LDO regulator is developed

by removing the bottleneck which is a huge load capacitor. Experimental results show

CL-LDO is having good transient response and hence it is suitable for SoC

applications.

ACKNOWLEDGEMENT

Author wish to thank Dr. K C Narasimhamurthy Ph.D. (IITG) Professor & Head of

Telecommunication engineering Department, Siddaganga Institute of Technology,

Tumakuru-572103,for his support and courage given to formulate this Paper.

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Anoop Kiran


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