Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal IC

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420 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28 . NO. 4. APRIL 1993

Experimental Results and Modeling Techniques for

Substrate Noise in Mixed-Signal Integrated Circuits

David K . Su , Student Member, I E E E , Marc J. Loinaz, Student Member, I E E E ,

Shoichi Masui, Member, I E E E , and Bruce A . Wooley, Fellow, I E E E

Abstruct- Switching transients in digital MOS circuits canperturb analog circuits integrated on the same die by means ofcoupling through the substrate. This paper describes an experi-mental technique for observing the effects of such substrate noise.Various approaches to reducing substrate crosstalk (the use ofphysical separation of analog and digital circuits, guard rings, anda low-inductance substrate bias) are evaluated experimentally fora CMOS technology with a substrate comprised of an epitax-ial layer grown on a heavily doped bulk wafer. Observationsindicate that reducing the inductance in the substrate bias ismore effective than either physical separation or guard rings inminimizing substrate crosstalk between analog and digital circuitsfabricated on epitaxial substrates. To enhance understanding ofthe experimental results, two-dimensional device simulations are

used to show how crosstalk propagates via the heavily dopedbulk. Device simulations are also used to predict the nature ofsubstrate crosstalk in CMOS technologies integrated in uniform,lightly doped bulk substrates, showing that in such cases thesubstrate noise is highly dependent on layout geometry. Finally,a method of including substrate effects in SPICE simulations forcircuits fabricated on epitaxial, heavily doped substrates has beendeveloped using a single-node substrate model.

I. INTRODUCTION

VER the past several years, the continued scaling of0 VLSI technologies has made possible the realization of

complete monolithic systems that integrate complex, high-

speed digital circuits together with high-performance analog

circuits [ I ] , [ 2 ] .In such mixed-signal systems, fast switching

transients produced in the digital circuits can couple intosensitive analog components, thereby limiting the analog pre-

cision that can be achieved. As a result of the demands for

higher clock rates and greater analog precision that accompany

progress in the underlying semiconductor technology, switch-

ing noise is an increasingly serious concern in the design of

mixed-signal integrated circuits [ 11, [3], [4].

Fast digital transients can produce switching noise in other

circuits on the same die through both direct capacitive coupling

between interconnect lines and interaction via the substrate.

Manuscript received August 24, 1992; revised November 3 . 1992. Thiswork was supported in part by the Semiconductor Rehearch Corporation underContract 92-DJ-112 and by the Department of Energy under Contract DE-AC03-76SF00S S .

D . K . Su, M. J. Loinaz, and B . A. Wooley are with the Center lor IntegratedSystems, Stanford University. Stanford, CA 94305.S. Masui was with the Center fo r Integrated Systems, Stanford University,

Stanford, CA 94305. He is now with the Semiconductor Basic TechnologyResearch Laboratory. Nippon Steel Corporation. 5- IO - 1 Fuchinobe. Sagam i-ham, Kanagawa 229, Japan.

IEEE Log Number 9206702.

The focus of this work is on substrate noise-perturbations

produced in analog circuits by switching transients in digital

circuits on the same die, with the coupling occurring through

the substrate.

The present trend in CMOS technologies is to use a substrate

comprised of a lightly doped epitaxial layer grown on a heavily

doped bulk substrate in order to minimize latch-up phenomena

[SI-[ 81. However, a significant fraction of current processes

continue to utilize a uniform, lightly doped substrate [9]. As

will be shown, the type of substrate has a crucial influence on

substrate noise effects. 'Experimental observations, along with two-dimensional de-

vice simulations, have been used in this work to study both themechanisms by which substrate excitations are produced and

the manner in which these excitations affect analog circuits.

A test chip was fabricated in a 2-pm CMOS technology with

a substrate consisting of a lightly doped epitaxial layer grown

on a heavily doped bulk wafer. This chip includes structures

for evaluating the effectiveness of various methods of reducing

substrate crosstalk, such as the use of guard rings and substrate

tie-downs. Device simulations carried out using the program

PISCES-IIB [ I O ] have been used to illustrate the current flow

paths within the substrate. While the experimental observations

presented in this work are germane to CMOS technologies

with heavily doped substrates, the experimental approach is

equally applicable to studying substrate noise in a technology

with a lightly doped substrate. Device simulations have been

used to predict substrate crosstalk effects for a CMOS process

with a uniform, lightly doped substrate.

In order to realize single-chip analog/digital systems that

are efficient in terms of die area, packaging, and development

time, designers of mixed-signal circuits must be able to

assess substrate noise effects prior to chip fabrication. The

experimental results presented in this paper provide the basis

for a single-node substrate model for heavily doped substrates

that can be readily employed in circuit simulations.

The test chip and experimental setup are described in

detail in Section 11 of this paper. The approach used for the

device simulations is then outlined in Section 111. In Section

IV , the results of both experimental observations and device

simulations are presented for a technology with a heavily

doped substrate. The use of physical separation between analog

' I n this paper. substrates consi.;ting of a lightly doped epitaxial layergrown o n a heavily doped bulk substrate are referred to as hemi / ! doped

.~h.s trute.s .Unifonn. lightly doped bulk wbstrates are referred to as / i g k t / ~

dO/JCl/.suhsrr.t~tct

0018-9200/93$03.00 G I993 IEEE



SU P I u/ ; SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED CIRCUITS 42 1

Oscilloscope

-5 v 3 v lgl -5 v

T T TSwitching Noise

Source Gate Drain0.2 pF I

Current Source Substrate

Transistor ContactFEpitaxial Layer (15 Q-cm)

IP+ChannelStop Implant(1&cm$

I IP+Bulk (0.05 M m )

Fig. I . Basic experimental setup.

and digital circuits, guard rings, and a low-inductance substrate

bias are evaluated as methods of reducing substrate crosstalk.

Section V explores, via device simulations, the effectiveness

of physical separation and guard-ring diffusions in reducing

substrate crosstalk in a CMOS technology with a lightly

doped substrate. A circuit simulation model for heavily doped

substrates is presented in Section VI , and circuit simulationresults are compared to experimental observations. In Section

VI1 a quantitative analysis of substrate crosstalk reduction in

heavily doped substrates is outlined. The impact of the single-

node substrate model on clocking and packaging choices for

circuits fabricated in such technologies is also discussed.

11. EXPERIMENTALSETUP

A 2-mm x 2-mm CMOS test chip was fabricated in a

2-pin n-well technology [SI employing a 15-prn. IS-IL.cm,

p-type epitaxial layer grown on a ~ O O - ~ I I ~0.05-12.cm, p-

type bulk substrate. Fig. 1 illustrates the basic test structure

used. The effective thickness of the lightly doped epitaxial

region, after processing is completed, is approximately 7 p r i

due to the upward diffusion of boron from the p+ bulk. Thesubstrate is excited by CMOS inverters with their outputs

coupled to the substrate by 0.2-pF capacitors. The inverters are

driven by an on-chip ring oscillator. A single-transistor NMOS

current source is used to measure the noise in the substrate.

Substrate voltage fluctuations affect the current flowing in the

current source via threshold voltage variations (body effect)

and capacitive coupling between the substrate and the gate,

drain, and source nodes. The drain of the current source

is connected off-chip to an oscilloscope with a 50-12 input

termination, while its source and gate terminals are biased

with dedicated power supplies. The substrate is biased using

p+ substrate contact diffusions that are connected to bonding

pads.

The test chip includes ten NMOS current sources with gate

dimensions W / L = 200 jini/2 jim distributed throughout the

die. Twelve CMOS inverters are switched at 5. 3 M H z by a

19-stage ring oscillator. Varying distances are used between

the current sources and the block of inverters to assess the

effects of physical separation. Seven of the current sources are

shielded from substrate noise by one of four different guard-

ring configurations: 1) a close pt guard ring, surrounding the

current source at a distance of 6 jmi, with a dedicated bias pad;

2) a distant p+ guard ring, surrounding the current source at

a distance of 22 pin; with a dedicated bias pad; 3) a close

I ) + guard ring (6-pn1 separation) connected to a large p+ ring

surrounding the chip; and 4) a distant p+ guard ring (22-

/m i separation) connected to the large p+ ring surrounding

the chip. All guard rings have 3 - / m diffusion widths. The

p+ diffusion ring surrounding the chip is 99-pni wide and

is connected to six bonding pads. Another large p+ substrate

contact, with an area of 1.6 mm2, is located in the center

of the die and connected to four bonding pads. The multiple

bonding pads for these two large substrate contacts are used

to study the effects of reducing the inductance in the substrate

bias. All p+ guard rings and substrate contact diffusions are

strapped with a polysilicon/tungsten local interconnect layer

and first-level metal (aluminum).

Separate pairs of positive and negative digital power supply

pads are provided for the inverter block and the ring oscillator.

The current-source transistors are divided into three groups,

each group sharing bonding pads for their drain and source

terminals. A separate bonding pad is provided for the gate to

each current source transistor. All testing is done with onlyone of the current sources tumed on at any given time.

The 44-pad test chip is packaged in a 68-pin J-leaded chip

carrier and attached to the cavity using a nonconductive epoxy.

The extra 24 package pins are wire bonded to the package

cavity and biased at circuit board ground. The test circuit is

operated between ground and -5 V so that a 50-R oscilloscope

termination can be used as the load resistor for the current

source being observed. Since the positive supplies are biased

at circuit board ground, the two positive digital supply pads

are connected to the package cavity through very short wires.

The negative supply of the inverter block is bypassed using

a 0.01-pF ceramic chip capacitor mounted in the package

cavity, with wire bonds made directly to the chip capacitor.

The chip capacitor serves to reduce the coupling of supply

bounce from the inverters' digital supply lead to other bondwires and package pins.

Special care is taken in the measurement setup to minimize

board-level noise. A two-sided etched copper board is used

with all routing done on the top side and the bottom side

serving as a ground plane. Metal is left in the unused areas

between the traces on the top side and connected to the ground

plane via through-holes. The chip package is mounted in a

short-lead PLCC surface mount socket. All supplies and bias

lines are bypassed to the ground plane at the feet of the socket

leads using 0.01-pF ceramic chip capacitors. The current

source output leads are soldered directly to RG174 coaxial

cables, each of which can be connected to a 50-12termination.

Three separate negative power supply traces are used on the

board: one for the ring oscillator and inverter block, one for

the sources of the current-source transistors, and one for all

substrate biasing. Each power supply trace is bypassed to the

ground plane using 0.1- and 1-j"F ceramic chip capacitors, and

a ~ ~ - L L Felectrolytic capacitor.

A second test chip was fabricated on the same wafer as the

substrate noise test chip described above. This die includes



42 2 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 28, NO. 4, APRIL 1993

fC1-5 v - 5 v

(for backsidecontactonly)

Fig. 2. Representative device/circuit structure for PISCES-lIB simulations.

a variety of structures for measuring spreading resistances

between substrate contacts at the chip surface, as well as the

capacitance between inverter outputs and the substrate.

111. DEVICESIMULATIONMETHODOLOGY

Although the experiments described in the preceding section

enable the observation of substrate effects at the circuit level,

they do not provide specific information on current flow

pattems in the substrate. To understand the mechanisms of

substrate crosstalk, a cross section similar to that shown in

Fig. 1 was simulated at the device level. A mixed-mode

device simulator that incorporates a circuit analysis capability,

PISCES-IIB, was used to investigate substrate phenomena,

including the effects of lumped inductances and capacitances

representing package parasitics. The device structures and

substrate composition were specified using doping profiles for

the CMOS technology in which the experimental test chip

was fabricated.

Fig. 2 shows the device structure/circuit simulated. The

device structure contains the following features: an equivalentdrain diffusion representing the drain diffusion at the output

of an inverter, an NMOS transistor current source with a

gate length of 2 pm, and p+ substrate contacts biased at the

negative supply. The substrate consists of a lightly doped (9 x

1014cm-3) p-type epitaxial layer grown on a heavily doped

(1 x 10" cuip3)p-type bulk. The thickness of the structure is

set at 200 pm (in the direction perpendicular to the page) in

order to give a transistor W / L ratio of 200 p m / 2 im.Because

the exact structure of the test chip is too complex for device

simulations, the circuit/device structure of Fig. 2 is the result of

simplifications meant to limit the number of finite-element grid

points and reduce the required simulation times. Specifically,

the bulk was modeled to a depth of only 90 im. and the

effects of very large-area substrate contacts and bonding

pad-to-substrate capacitances were not simulated. Because of

these simulation expediencies, the experimental and device

simulation results presented in the next two sections are not

compared quantitatively. Instead, similarities in trends are used

to validate and enhance understanding of the experimental

results.

The components L 1 .L2. and L:, in Fig. 2 represent the

inductances associated with bond wires and package traces.

L4 models the inductance in series with a backside substrate

contact, and the 5 0 4 resistor represents the oscilloscope input

impedance. In the device simulations, a -5-V to 0-V excitation

pulse with I-ns rise/fall times was applied at the equivalent

drain diffusion, and the response at Voutwas observed. The

dependence of the output response on the distance (1 between

the current-source transistor and the equivalent drain diffusion

was investigated, and various pf and n-well guard diffusions

were evaluated with respect to their ability to isolate the

current source from the substrate noise. These p+ and n-well

guard diffusions were placed 6 and 17 pm away from the

current source, respectively. In addition, when simulating the

effects of a backside contact, L1 and the two p+ substrate

contacts were removed and the value of La was varied to

study the dependence of substrate crosstalk on the substrate

bias impedance.

rv. RESULTSFOR HEAVILYDOPEDSUBSTRATES

A . Basic Mechanism

Fig. 3(a) shows an example of a noise waveform observed

at the output of a current source. The data for this figure were

taken with the substrate biased using a single package pin

connected to a 3-pin-wide p+ guard ring enclosing an area of

140 p i x 64 , m i . The response shown in Fig. 3(a) corresponds

to one ring-oscillator cycle. High-to-low transitions at the

outputs of the inverter block cause a negative-going voltage

transient in the substrate. This transient increases the threshold

voltage of the current-source transistor via the body effect,

thereby decreasing the current flowing in the current source

and inducing a positive spike in Vouout.Similarly, the negative

spike in Fig. 3(a) is the result of low-to-high transitions at the

outputs of the inverter block.2

Associated with the two main transients in Fig. 3(a) are

initial glitches of the opposite polarity. These are causedby capacitive coupling between the chip substrate and the

diffusions and interconnect that comprise the drain node of

the current-source transistor. This coupling is dominated by the

capacitance between the drain bonding pad and the substrate.

Fig. 3(b) shows the output voltage from a device simulation.

Because bonding pad capacitances are not included in the

device simulations, the glitches preceding the two principal

transients are reduced. The waveforms shown in Fig. 3 exhibit

very little ringing. As will be discussed in Section VII, the

amount of ringing is strongly dependent on the impedance of

the substrate bias.

For the purposes of this work, substrate noise is quantified

in terms of its peak-to-peak voltage and its settling time to

within 0.5 mV. The peak-to-peak voltage of the waveform

of Fig. 3(a) is 10.7 mV and the settling time is 6.8 ns. Allsettling time data presented in this paper represent the average

of the settling times of the positive and negative transients

associated with a ring-oscillator cycle.

'C i rcu i t hwla t ion? such as those described in Section VI have been usedto confirm the dependence of the noise waveforms on the body effect.



SU et al.: SUBSTRATE NOISE IN MIXED-SIGNA L INTEGRATED CIRCUITS

16

14>5 12

U)

z

10

x0

2 6 -c

L0 4 -

p" 2 -

42 3

-

-i * *

!I $*** *-x

-

x Distance to nearest invertermAverage distance to inverters

-0.434, . , . , . , . . . , . , . , . ,

L i mv

5 -0.440 -P-~+*

-0.442 .-0.444 -

v- - . - . . .

,f+

d . ' -

Time (ns)

(a)

-0.553

-0.555

-0.557hL3 -0.559

P-0.561

-0.563

20 40 60 80 100 120 140 160-0.5656. ' - ' . ' . ' . 1Time (ns)

(b )

(a ) Typical wave form obse rved experimentally at the current source

output. (b) Typical output voltage from device simulations.Fig. 3 .

B . EBect of Physical Separation

Fig. 4 shows the peak-to-peak noise voltages measured at

each current source as a function of distance between the

current source and the inverter block with all 12 inverters

active. Because of the large spatial distribution of the inverters

within the inverter block, the data points of Fig. 4 are plotted

both as the distance between the current source and the nearest

inverter and as the average distance between the current source

and the inverters. Fig. 4 shows that the peak-to-peak noise

amplitude is independent of the distance between the current

source and the noise sources. Increasing the separation from

40 to 850 p i does not reduce the measured noise. Moreover,

physical separation has no observable effect on the noise

settling time.

The experimental results of Fig. 4 can be explained with

device simulations. Fig. 5 presents the results of such a

simulation 0.1 ns after the initiation of a I-ns high-to-low

transition at the equivalent drain diffusion of Fig. 2 . Current

flow lines through the substrate are shown in this figure,

with the region between adjacent lines representing 5% of

the total substrate current. Fig. 5 indicates that most of the

lateral current from the digital noise source to the substrate

contacts flows in the heavily doped bulk. Because of the lowresistivity and thickness of the bulk, the injected noise current

flows almost directly down through the epitaxial layer into the

bulk and then up through the epitaxial layer to the substrate

contacts. These simulation results have been corroborated by

measuring the resistance between two substrate contacts as

a function of the distance between them. The measurements

C. Cur-rent-Sout-crGuard Ring5

As described in Section 11, four p+ guard-ring structures

were evaluated on the test chip: a close guard ring (6-pm

separation) with a dedicated bonding pad, a distant guard ring

( 2 2 - p i separation) with a dedicated bonding pad, a close



424 IEEE JOURNAL OF SOLID-ST ATE CIRCUITS. VOL. 2X. NO.4,APRIL 1993

150, I

Q 10

100 150 200

Distance (pm)

Fig. 6. Device simulation results for peak-to-peak noise a s a functiondistance between the digital noise source and current source.

No P+Guard Ring

With P* Guard RingvE 1 2 :

.-3 .

Q 8 :

3 4 -

2 2 -

0 102 .

Y

-

Q .

0

di %k e d& !e dit gc a dl%%e

(dedicated package pin) (connected to largesubstrate contact)

Guard Ring Configuration

Fig. 7. Measured influence of I>+ guard ring5

of

guard ring connected to a large substrate contact, and a distant

guard ring connected to large substrate contact. The latter two

cases are intended to emulate the situation in which a p+

guard ring is connected on-chip to all other substrate contacts,

and biased using a single common bonding pad. The noise

measured at the output of each guard-ring-shielded current

source is compared to that measured in a nearby current source

that is not protected by a guard ring.

Results of noise measurements illustrating the effects of

the various guard-ring structures are presented in Fig. 7. For

the tests involving a dedicated guard-ring package pin, the

substrate is biased using one of the package pins connected

to the 99-pm-wide p+ ring surrounding the chip. As shown

in Fig. 7 , a p+ guard ring (biased with a dedicated package

pin) placed close to the current source provides a reduction

of approximately 20% in the substrate noise, while a similar

but more distant ring has less of an effect. However, guard

rings connected to large substrate contacts actually result in

an increase in the observed noise. These experimental resultscan be explained with the aid of Fig. 8.

If a guard ring is to reduce the switching noise in the

current source, it must act to decouple the epitaxial layer in

the immediate vicinity of the current source transistor from the

noisy pi bulk. In Fig. 8, resistors R I .R2. and R; j represent

the spreading resistance of the epitaxial layer. In Fig. 8(a)

IP

Fig. 8. (a) Cross-section showing pf guard ring biased using dedicatedpackage pin. (b )P+ guard ring connected on-chip to large substrate contact.

the guard ring is biased with a dedicated package pin. This

structure can reduce switching noise at node A in the epitaxial

layer if resistor RI is made smaller than R2, which can be

accomplished by placing the guard ring as close to the current

source as possible. In Fig. 8(b) the guard ring is connected to

a large substrate contact diffusion. Because of the large size

of this diffusion, R3 is very small, thereby closely coupling

node B to the noisy heavily doped bulk.

Device simulation results for various guard diffusion struc-

tures are shown in Fig. 9. These results are consistent with

the experimental observations in that they also indicate that,

for heavily doped bulk substrates, a I)+ guard diffusion biased

with a dedicated package pin will provide a modest reduction

in substrate noise (about 30% in Fig. 9). Simulations also

indicate that an n-well guard diffusion, which breaks the p+

channel stop implant, has almost no effect because most of thesubstrate current flows in the heavily doped bulk and not in the

channel stop diffusion near the die surface. Device simulation

results for a lightly doped substrate, also shown in Fig. 9, are

discussed in Section V.

D . Inductance in the Siihstrute Bius

Because the p+ bulk behaves electrically as a single node,

attenuation of voltage fluctuations in the bulk through the

use of a low-impedance connection to the negative supply

voltage should reduce substrate crosstalk. Fig. 10 summarizes

the measured peak-to-peak noise and noise settling time as

functions of the number of package pins (10 nH per bound-

wire package pin) used to bias the two large p+ substratecontacts on the surface of the chip. Also included in this

figure are the results obtained from circuit simulations, which

are discussed in Section V I. The spreading resistance between

each of the large substrate contacts and the heavily doped

bulk is approximately 3 R. Increasing the number of package

pins connected to the substrate contacts decreases the series



SU et <,I: SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED CIRCUITS

Peak-to-Peak Noise (mV)

I I

No GuardDiffusion

PGuardDiffusion

N-well GuardDiffusion

P i and KwetlGuard Diffusions

No GuardDithrslon

Diffusion

N-wellGuardDiffusion

P+ and N-weltGuard Dlffusions

I - . . . . . . . - . - . . . . . . . .I0 1 2 3 4 5 6 7 8 9 10

Fig. 9 . Guard-ring effects as predicted by device simulations

r z z lU Circuit Simulation

O I i 2 3 4 5 6 i i

Number of Substrate ContactPackage Pins

(a )

1 I Measurement IU Circuit Simulation

LOC! 1 2 3 4 5 6 7 i

Number of Substrate ContactPackage Pins

(b )

Fig. IO . (a) Measured peak-to-peak noise as a function of the number ofpackage pins used 10 bias the substrate. The results of circuit simulations

are also shown. ( b ) Measured noise settling times and results of circuit

simulations.

inductance in the substrate bias, reducing oscillations in the

single-node substrate.

Fig. 1 1 summarizes the results of device simulations of the

peak-to-peak noise and noise settling time as functions of the

inductance in the substrate bias when the substrate is biased

using a backside contact to the heavily doped bulk. These

1 2 5

10 r

s

.-

Inductance (nH)

( a )

50 c

Inductance (nH)

( h )

Fig. 1 1. ( a ) Device simulation results fo r peak-to-peak noise as a function of

the inductance used to bias a backside substrate contact. (b ) Device simulation

results for noise settling time.

results are consistent with those of Fig. IO . With zero series

inductance, the backside contact virtually eliminates substrate

noise by keeping the bulk at ground potential. However if

the inductance is nonzero, substantial ringing is observed in

the output noise. The effects of substrate bias impedance on

switching noise are analyzed in Section VII.

V. DEVICESIMULATIONRESULTSFO R LIGHTLYDOPED SUBSTRATES

Device simulations indicate that the nature of substrate

crosstalk in lightly doped substrates differs significantly from

that in heavily doped substrates. Specific differences are ex-

amined in this section.

Results of simulations illustrating the dependence of the

noise voltage on the physical separation between the equiva-

lent drain diffusion and the NMOS transistor are included in

Fig. 6 for lightly doped, as well as heavily doped, substrates.

In the lightly doped case, the noise voltage decreases almost

linearly with the separation distance. These results can be

understood by comparing the current density lines for a

lightly doped substrate shown in Fig. 12 with those fo r a

heavily doped substrate presented in Fig. 5 . In the lightlydoped substrate. current flow is more uniform within the

substrate because there is no low-resistance bulk. Therefore,

the isolation between digital and analog circuits improves as

the physical separation is increased.

The effects of using a p' diffusion or n-well to shield

the current source from substrate noise in a lightly doped



426

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.: 30

40

50

lEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 2X. NO. 4, APRIL 1993

B..!-

Substrate NMOSContact Transistoi

Equivalent SubstrateDrain Diffusion Contact

Distance(w)

Fig. 12. Current flow lines in a lightly doped substrate.

substrate are included in Fig. 9. The simulation results show

that a p+ guard-ring diffusion can reduce the switching noise

by almost an order of magnitude because a p+ guard-ring

diffusion acts as a current sink that keeps the substrate in the

immediate vicinity of the current source quiet. The current

flow lines in Fig. 12 show that a significant amount of thesubstrate current flows near the die surface because of the p+

channel-stop implant. An n-well guard diffusion therefore acts

to isolate the current source by interrupting the channel-stop

implant and forcing substrate current to flow through the high-

resistance bulk. These device simulation results imply that in

a technology employing a lightly doped substrate, sensitive

analog circuits can be protected from substrate noise through

the use of concentric n-well and p+ guard rings.

Device simulations also show that low-inductance biasing

increases the effectiveness of guard rings and substrate con-

tacts. However, because substrate noise effects in a lightly

doped substrate are highly layout-dependent, device simu-

lations alone do not reveal additional general conclusions

regarding the effects of substrate bias inductance.

VI . CIRCUIT MODELINGFOR HEAVILYDOPEDSUBSTRATES

Experimental and device simulation results indicate that

when a switching noise source and a sensitive analog circuit

are separated by more than four times the effective thickness

of the epitaxial layer, substrate crosstalk occurs via the heavily

doped bulk. Circuit simulations can be used to predict substrate

effects in such cases if conventional schematics are augmented

by modeling the heavily doped bulk as a single node [ I ] . Fig.

13 shows how the interactions of transistors and substrate con-

tacts with the substrate node can be modeled. The transistors

and their associated junction capacitances are represented by

the appropriate SPICE models, while R P p l l - R e p , ~represent

spreading resistances through the epitaxial layer.

To characterize spreading resistance through the epitaxiallayer, p+ substrate contact diffusions of various sizes were

fabricated on a separate test chip. An empirical formula that

describes the epitaxial spreading resistance between a p+

substrate contact and the heavily doped bulk based on the

surface geometry of the substrate contact has been derived.

This formula corresponds to the parallel combination of two

Well SubstrateContact Contact

QPJpJ lpl

SubstrateContact

TBulkNode

Repi1 IFig. 13. Circuit representation of a heavily doped substrate

resistors, R.A.RE.A.and RPER.The area component of the

resistance, R.ARE-\.is based on uniform current flow through

a rectangular block and is given by

PTRARE.^ = -.

‘4(1 )

The parameters and T represent the resistivity and effectivethickness of the lightly doped epitaxial layer, respectively,

while A is the surface area of the substrate contact. The

resistance due to current flow at the perimeter of the diffusion,

R P E R .is based on uniform conduction in a hemisphere [ 1 11

(2 )P

RPER= -I’

where p is the resistivity of the epitaxial layer and P is the

perimeter of the substrate contact. The resultant spreading

resistance formula, based on the parallel combination of ( 1 )

and ( 2 ) , is

where the variables kl.k 2 , and h are empirical fitting param-

eters. Assuming T = 7pm. with k l = 0.96, k2 = 0.71. and

6 = 5 . 0 1 ~ ~ .the results from (3 ) are within 15% of measured

values.

Fig. 14 shows a simplified schematic used to model the

experimental setup described in Section 11. The p+ bulk is

represented by a single node. Capacitor C.51 represents an

n-well, while Cs2-Cs7 represent the capacitances between

interconnect lines (including bonding pads) and the substrate.

Drain and source junction capacitances are included in the

transistor SPICE models. Switching noise is injected into the

substrate by the CMOS inverter via Cs2 and the drains of

1111 and M 2 . Capacitor Cs8 models all capacitance between

the bulk and ac ground. Resistors Rs1-Rs.l model spreading

resistances through the epitaxial layer. Inductances L p l - L p ~

represent parasitic inductances of bond wires and packagetraces. The input impedance of the oscilloscope is modeled

by a 5042 resistor in parallel with a 7-pF capacitor.

Fig. 15 compares an experimentally observed noise wave-

form with the results of a circuit simulation. The top trace

is the output waveform of a current source as seen on a

digital oscilloscope and the bottom trace is the result of a



SU er a / : SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED CIRCUITS 42 1

4 LP3

SwitchingCircuits I -,,-,,,,,I I,I,,-,- ~

Oscilloscope

-5 vI.,,,,,,,,,,,,,,,,;-5 v

Fig. 14. Schematic representation of Fig. 1 for circuit simulations.

2 mVIdiv

0)

mc-8

Qc

2 mVldiva

0 20 40 60 80 100 120 140 160

Time (ns)

Fig. 15. Observed and simulated noise wavcform7.

SPICE simulation. The close agreement between simulation

and measurement is partially due to the use of experimentally

measured values for the spreading resistances and package

parasitics in Fig. 14. The circuit simulation results were found

to be highly dependent on the values used for CSU.R s ~ .

and L p j (5 5 pF, 3 f l . and 10 nH, respectively). C S ~is

dominated by the capacitance between the bulk and the IC

package cavity, through the nonconductive die attach epoxy.

The package cavity was held at ac ground as described in

Section 11. Depending on the chip layout, the contribution of

n-well capacitance to Cs8 may be significant. Rss represents

the spreading resistance from surface substrate contacts to

the bulk node. L p j is determined by the number of bonding

pads and package pins used to bias the substrate contacts at

the die surface. Circuit simulations using only Cs8:Rs3. and

Lpg (neglecting all other package parasitics and spreading

resistances in Fig. 14) yielded results for peak-to-peak noise

and noise settling time within 50% of measured values.Fig. 10 shows good agreement between circuit simulations

and experimental measurements for peak-to-peak noise volt-

ages and noise settling times as a function of the number of

package pins used to bias the substrate. Circuit simulations that

include substrate crosstalk effects may therefore be feasible for

chips fabricated on heavily doped substrates. A single-node

substrate model has been shown to give reasonable results

with modest additions to conventional circuit schematics.

Furthermore, the enhancements to conventional schematics

can be made in a straightforward manner, making use of

layout geometry, equation (3), and information about package

parasitics. A layout extractor could be modified to include

substrate effects, enabling designers to quantitatively assess

substrate crosstalkin a

given layout.For large circuits, including the entire chip in a SPICE

simulation is often impractical. In such cases, the switching

noise produced by a large logic block can be emulated using

chains of inverters driven by an ideal clock [12]. The sizes of

the inverters can be chosen to duplicate the transient current

injected into the substrate by the logic block. Using these

equivalent switching noise sources, simulations of sensitive

analog circuits can include substrate effects associated with

the entire chip. With the aid of a logic timing simulator, it

should be possible to generate such equivalent switching noise

sources from a layout.

VII. REDUCINGSUBSTRATECROSSTALK

IN HEAVILYDOPED SUBSTRATES

With the heavily doped bulk acting electrically as a single

node, any switching transient that excites the bulk will affect

the entire chip. For circuits fabricated on heavily doped

substrates, reducing substrate crosstalk is thus largely a matter

of silencing the bulk node.

In a p-type substrate, p+ guard rings can be used to decouple

local regions of the epitaxial layer from the heavily doped

bulk. These structures may be placed close to sensitive analog

circuits in an attempt to isolate them from the bulk node.

However, both experimental and device simulation results

have shown these techniques to be effective only when the

pt guard rings are placed very close to the sensitive analog

circuits and are biased using dedicated package pins.

A promising method of reducing excitation of the bulk

node is to modify the substrate bias impedance in order totie the substrate more closely to ac ground. Analysis of the

simplified schematic in Fig. 16 provides insight into how bulk

node perturbations caused by switching transients represented

by V&NS can be reduced. Capacitor Cc in this schematic

models diffusion and interconnect capacitances coupling the

switching noise sources (for example, logic gate outputs and

noisy power supply lines) to the substrate. To first order, the

switching noise voltage at the bulk node, V B U LK .is determined

by the voltage division between capacitor Cc and the substrate

bias impedance. The substrate bias impedance is comprised of

R,s .Ls . and Cs. which correspond to R s ~ ,L p j , and Cs8 in

Fig. 14.

The graph in Fig. 16 plots the magnitude of the frequency

response of the V B U L K / V T R . A N S transfer function, which is

given by

(4)



42 8 IEEE J O U R N A L OF SOLID-STATE CIRCUITS. VOL. 28 . NO. 4,APRIL 1993

0 . 2 0 , . , . , . , . , . ,U)

a

>’ 0.15.3

>”C.-0 0.10c

C

U,

L

1 0.05

C

;0.00

VTRANSA

I \Cs = 55PF,Cc 2.4pF)4

200 400 600 800 1WO

Frequency (MHz)

Fig. 16. Switching noise model for a heavily doped substrate.

A resonance in this response occurs at frequency WO .where

If the magnitude of the frequency response at WO is very large

(as shown in Fig. 16 for Ls = 10 nH), care must be taken

to ensure that all switching frequencies (e.g., clock rates) and

their low-order harmonics do not coincide with the substrate

resonance frequency [ 11.

If VTR.A.NSin Fig. 16 is represented as a square wave with

a period large enough so that all substrate transients die out

between the rising and falling edges, upper bounds for the

substrate noise amplitude and noise settling time can be found

by considering the step response of the circuit in Fig. 16.When

V & N ~ is a unit step, the substrate noise voltage response,

V B U L K ( ~ ) %is

where the damping coefficient N is

Rs

2LS(Y = ~

the frequency of the oscillations in the response, / I . is

(7 )

The settling behavior is governed by the damping factor <.Fo r

actual circuits, the rise and fall times of VTR.A.NSare nonzero.

A step response analysis that includes the effects of nonzero

transition times in VTR.A.N~is presented in the Appendix. The

analysis shows that the noise amplitude decreases slowly as

Ls is decreased, as was observed experimentally (see Section

IV). Equation ( I O ) should therefore be regarded as an upper

limit for the noise amplitude.Equations (6)-( 10) provide insight into how the relative

values of Rs. L s . Cs, and CC can be chosen to minimize the

substrate noise amplitude and settling time. These equations

show that the switching noise voltage may be overdamped

(C > 1) as in Fig. 3 or underdamped (C < 1) as indicated

by the oscillations in Fig. 15. Equations (6)-(IO), and the

results presented in the Appendix, suggest that the amplitude

of substrate noise can be reduced by decreasing the value of

Cc with respect to Cs and by decreasing the value of Ls with

respect to Rs. provided that the transition times of V T R A N ~are much smaller than the damping time constant, (k-’.

Unfortunately, the components in Fig. 16 cannot be ad-

justed arbitrarily. Cc is determined primarily by the process

technology, along with circuit performance and functionality

considerations. Rs is govemed by the size and number ofsubstrate contact diffusions, which are often dictated by latch-

up considerations. Increasing the capacitance Cs ~ by adding

on-chip decoupling capacitance. for example, may lower the

noise amplitude, but it also has the undesirable effect of

lowering the substrate resonance frequency. As seen in Section

IV , a practical means of minimizing substrate noise is to

reduce the inductance Ls relative to Rs. If the value of

L S is reduced by lowering parasitic inductance of the IC

package, both the amplitude and settling time of substrate

noise are reduced without compromising circuit performance.

When a conventional package is used. Ls can be reduced by

connecting multiple bond wires to the substrate contact. An

alternative approach is to use a custom package where the

package cavity can be held at ac ground through a very low-inductance lead. The backside of the die can be electrically

connected to the package cavity using a conductive epoxy.

The backside substrate contact configuration could then have

a very small L.7. However, because RS has also been greatly

reduced, the noise settling times may be much longer. The

resultant values of Rs. L s , C y . and CC must be considered

in conjunction with the analysis developed in the Appendix to

determine the effects of using a nonstandard package.

(8) VIII. CONCLUSION_ _ _R:1

= l / L s ( Q +CC) 4 L iThe experiments and simulations described in this paper

provide insight into the nature of switching noise in mixed-

signal integrated circuits. Propagation of switching noise

should be visualized as a three-dimensional phenomenon, withthe type of substrate playing a crucial role in crosstalk effects.

An experimental framework for studying substrate noise in

mixed-signal IC’s has been developed and used to observe

substrate crosstalk effects in a technology with a substrate

consisting of a lightly doped epitaxial layer grown on a heavily

doped bulk. Experimental observations and device simulations

and the damping factor ( is

( = “ J L S ( C S + Cc) . (9)

The maximum amplitude of the step response occurs at f = 0

and is given by

CC

cc + C‘S‘(VB ~ r L K( 1 l l aX)= ~



SU et U / . SUBSTRATE NOISE IN MIXED-SIGNAL IN TEGRATED CIRCUITS 42 9

indicate that switching noise that reaches the heavily doped

bulk spreads throughout the entire chip. If analog and digital

circuits are separated by four times the effective thickness of

the epitaxial layer, crosstalk between digital circuit blocks and

sensitive analog circuits occurs primarily by way of the heavily

doped bulk, and further increases in the physical separation

will not reduce substrate crosstalk. In an n-well process, ps

guard rings can partially shield sensitive analog circuits fromnoise in the bulk if the rings are placed very close to the analog

circuits and biased with dedicated package pins. Reducing the

inductance in the substrate bias was found to be the most

effective way of minimizing substrate noise.

Device simulations of substrate crosstalk in lightly doped

substrates indicate that substrate noise is highly dependent

on layout geometry. For circuits fabricated on lightly doped

substrates, physical separation and guard rings appear to be

effective ways of shielding sensitive analog circuits from

digital switching transients.

Although simple rules of thumb can be helpful, circuit

simulations that can quantitatively predict substrate crosstalk

effects are needed for the design of mixed-signal integrated

circuits. For technologies employing an epitaxial layer grown

and

l Rc\ 2

The quantities (Y and /j are specified in (7) and (8). Note that

as the rise time becomes small, p7.goes to infinity and (1 1)reduces to (4). Plots of (13) show that decreasing L S will

result in lower noise amplitude. as observed experimentally.

ACKNOWLEDGMENT

The authors wish to thank Dr. J . Shott and the staff of the

Integrated Circuits Laboratory at Stanford University for the

fabrication of the test circuits and for providing the doping

profiles used in the device simulations. A special acknowledg-

ment is extended to Technology Modeling Associates, Inc. for

providing the program PISCES-IIB. Thanks are also due to Dr.

B. Razavi, D. Wingard, and W. Wong for technical assistance

and numerous helpful discussions.

REFERENCES

on a heavily doped bulk substrate, a single-node model of

th e bulk substrate can be used to include substrate effectsI1I T. J . Schmerbeck. R. A. Richetta. an d L. D. Smith, “A 27 MHZ mixed

A/D magnetic re cording channel D SP using partial response signallingwith ma ximum likelihood detection.’’ in ISSCC D ~ R .Tech. Puprra. 1991.

121 S. Takeuchi et d.“A 30-M Hz mixed analog/digital signal processor.”I E E E J . So/id-.Srate Circ.irits. vol. 2.5. pp. 1458-1463, Dec. 1990.

131 B. P. Brandt and B. A. Woolev, “A SO-MHz multibit sigma-delta mod-

in circuit simulations. Analysis of the single-node substrate

model provides insight into how substrate noise amplitude and

settling time can be reduced.

APPENDIX

When considering the step response of the circuit of Fig.

16, the effects of a nonzero step rise time must be included

in order to accurately reflect the effects of changing Ls . A

nonzero rise time for the VTR.~NSsignal can be modeled using

a single-pole response. This can be accomplished by adding a

single-pole filter to (4), yielding

where

2.2

rise tiriicpr = -.

The step response of the above transfer function is

where

ulator for 12-b 2-MHi A/D conver\ion.” IEEE .I. Solrd-Srute Crrcrrits.

vol. 26 . pp . 17461756. Dec. 1991.(41 L. D. Smith er al., “A CMOS-based analog standard cell product family.”

/ € E € J . Solid-State Ciwrtitr , vol. 24, pp. 370-379. Apr. 1989.

151 Y. Taur et U / . , “A self-aligned I-ltm-channel CM OS technology withretrograde n-well and thin epitaxy.” IEEE Trans. Elec,tronDe1.ic.r.y.vol.

ED-32. pp. 203-209, Feb. 19x5.161 R . A . Chapman et U / . . ”An O.8mm CM OS technology for high perfor-

manc e logic applications.” in l E D M Tech. Dix.. 1987.171 G . J . Hu and R. H. Bruce, “A CMOS structure with high latchup holding

voltage,” IEEE Elrc,troriDe1,ic.eLe f r . .vol. EDL-5, pp. 21 1-214, June1084.

181 “The Stanford BI CMO S project annual report,” Center for Integrated

Syst.. Stanford Univ., Stanford, CA . pp , 7-24, 1990.101 H. Ooka r r U / , “High \peed CMOS technology for ASIC application,”

in IEDM Tech. Dr,q. , 1986.

I I O ] T M A PISCES-I IR . A T~~o-Diniet7sronuIDr1,ic.eAnulysrs Progran7 WrthA M . Technology M odeling Associate.; Inc., July 1991.C o m m 4th ed. New York: Springer Verlag, 1967.

I12 ) L. D. Smith, “Circuit model for \ub\trate noise on mixed analogflogicproducts,” presented at the IEEE SSCTC Workshop on Noise in MixedAnalog/Digital IC‘s, Sept. 199 I .

David K. Su (S’X I ) was born in Kuching, Malaysia,on September 16. 1961. He received the B.S. an dM.E. degrees in electrical engineering from theUniversity of Tennessee, Knoxville, in 1982 and1985, respectively. He is currently a Ph.D. candi-

date in electrical engineering at Stanford University,Stanford, CA.

From 19x5 to 1989 he worked as an IC designengineer at Hewlett-Packard Company in Corvallis,O R , an d Singapore where he designed full-customand semi-custom application-specific integrated cir-

cuits. During the summer of 1991,he worked on the design of an oversampling

DIA converter at IBM Corporation. Research Triangle Park, NC. His currentresearch interests include the design of analog, mixed-signal, and data con-version integrated circuits.

Mr . Su i \ ;1 member of Tau Beta Pi. Eta Kappa Nu. and Phi Eta Sigma.



430 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 28, NO. 4, APRIL 1993

Marc J. Loinaz (S’89) was bom in Manila. thePhilippines, on August 20, 1 967. He received the

B.S. degree in electrical engineering from the Uni-

versity of Pennsylvania, Philadelphia. in 1988 an dthe M.S. degree from Stanford University. Stanford.CA, in 1990. He is currently a Ph.D. candidate in

electrical engineering at Stanford University.

During the summer of 1990, he worked at Na-tional Sem iconductor C orporation, Santa Clara, CA ,where he was involved in the design of an over-s a m u li n e A D converter. Over the summ er of 1991,. -

he was employed at the Digital Equipment Corporation Western Research

Laboptory, Palo Alto, CA, where he participated in the design of anECL RISC microprocessor. His research interests are in the area of high-performance analog and digital circuit design, with emphasis on mixed-signalintegrated circuits in CMOS and BiCMOS technologies.

Mr. Loinaz was a recipient of the E. Stuart Eichert Memorial Prize fromthe University of Pennsylvania in 1987, and is a member of Tau Beta Pi an d

Eta Kappa Nu.

P

Shoichi Masui (M’89) was bom in Nagoya, Japanon February 14, 1960. He received the B.S. andM.S. degrees in electrical engineering from Nagoya

University, Nagoya, Japan. in 1982 and 1984, re-spectively.

In 19 84 he joined Nippon Steel Corp oration,

Kanagawa, Japan. where he is currently a SeniorResearcher in the Electronics Research Laborato-ries. From 1990 to 1992 he was a Visiting Scholarat Stanford University. His research interests includethe design and testing of mixed-signal integrated

circuits

Bruce A. Wooley (S’64-M’7GSM’76-F382) wa sbom in Milwaukee, WI, on October 14. 1943. He

received the B.S., M.S. and Ph.D. degrees in elec-

trical engineering from the University of Califomia,Berkeley. in 1966, 1968, and 1970. respectively.

From 1970 to 1984 he was a member of the re-search staff at Bell Laboratories in Holmdel, NJ. In1980 he was a Visiting Lecturer at the University of

Califomia, Berkeley. In 1984he assumed his presentposition as Professor of Electrical Engineering atStanford University. Stanford, CA. His research is

in the field of integrated circuit design and technology where his interestshave included monolithic broad-band amplifier design, circuit architecturesfor high-speed arithmetic, analog-to-digital convers ion, digital filtering, high-speed memory design, high-performance packaging and test systems, and

high-speed instrumentation interfaces.Prof. Wooley was the Editor of the IEEE J O U R N A L O F SOLID-STATEC I R C U I T S

from 1986 to 1989. He was the Program Chairma n of the 1 990 Symposiumon VLSI Circuits and the Co-chairman of the 1991 Symposium on VLSI

Circuits. He was the Chairman of the 1981 lntemational Solid-state CircuitsConference, and he is a former Chairman of the IEEE Solid-State Circuits and

Technology Com mitte e. He has also served on the IEEE So lid-state CircuitsCouncil and the IEEE Circuits and Systems Society Ad Cam. In 1986 hewas a member of the NSF-sponsored JTECH Panel on TelecommunicationsTechnology in Japan. He is a member of Sigma Xi, Tau Beta Pi, and Et aKappa N u. In 1966 he wa\ aw arded the University Medal by the Universityof Califomia, Berkeley, and he was the IEEE Fortescue Fellow for 196 61 967 .

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Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal IC

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