Substrate Coupling and Interconnect Noisein Mixed-Signal and High Speed Digital ICs
Eby G. Friedman
Department of Electrical and Computer EngineeringUniversity of Rochester
IEEE CAS Workshop on Mixed-Signal Integrated Circuit Design
December 2, 1999
Presentation Outline
� Introduction to noise in high speed CMOS integrated circuits
� Substrate coupling in mixed-signal integrated circuits
� On-chip inductance
� Peak noise estimation of coupled lossy transmission lines
� On-chip simultaneous switching noise voltage in the powerdistribution network
� Repeater insertion for driving� ���
interconnect
� Conclusions
MSICD’99 Univer sity of Rochester
Presentation Outline
➱ Introduction to noise in high speed CMOS integrated circuits
� Substrate coupling in mixed-signal integrated circuits
� On-chip inductance
� Peak noise estimation of coupled lossy transmission lines
� On-chip simultaneous switching noise voltage in the powerdistribution network
� Repeater insertion for driving� ���
interconnect
� Conclusions
MSICD’99 Univer sity of Rochester
Design Challeng e in VDSM CMOS ICs
� Moore’s law – exponential increase in circuit integration andclock frequency
�����
� ������� ����������������
��� �! ����"# �$�%"�! �$�%�%# �����%! &#�#%#
��#�'��# (��# )��#�*��# +
, - .�.�-, /%.�/%01325476%6�8 ., /%.�/ 6
, - 9 8 .;: 1325476 /%.%<, /�. 8 /%0=>0�.�?�= 6 ., /%0�. =>/%., - /�0
2A@B$C ,ED�FG�HEI J%K 8 :%:�0- 2A@B$C ,ED�FMLNLG�HEI J%K 8 : 8 0-LPO3QR?9%<�. SUT
V$WX Y
Z7[ \A]�^`_ YaW�b�c�W�d ] Vfehg7i�j
k�l�mn k�l%op k�l%on k�llp k�l%l%n qp%p%p
krp�s
krp t
krp�u
krp�v
w x y%y$x
w z%yz%{ w z%y|%z%{}7~%y
�����$��w�����>� � ��|��%��{�x ����$��wE� ���N��>� � ��|���|%{$x���3�����%y �5�
� Gap between design productivity and semiconductormanufacturing capability
�r��$� �r���� ������ ������ ������ ����$� ������ �������
���
�����
�r����
� �¢¡5£
¤¦¥§¨© ª «¬ ®¯ °± ²´³¥µ¶ · £¸¡3¹»º�¼�º%½%¾3£À¿Á��¹¢ºA¼ ½�Â
¿Á��º�¼ÄÃ>¹MÅ ½Æ¼aÇN¼�ÈÉ¡�½�¼�¾>¹
Nat
iona
lTe
chno
logy
Roa
dmap
for
Sem
icon
duct
or’9
7
Tech
nolo
gyC
hara
cter
istic
s
Year
ofF
irstP
rodu
ctS
hipm
ent
1997
1999
2001
2003
2006
2009
2012
Den
seLi
nes
(DR
AM
half
pitc
h)(n
m)
250
180
150
130
100
7050
Isol
ated
Line
s(M
PU
gate
s)(n
m)
200
140
120
100
7050
35In
tegr
atio
nD
ensi
ty(tr
ansi
stor
s/cm
Ê )hi
ghvo
lum
eM
PU
3.7
M6.
2M
10M
18M
39M
84M
180
Mlo
wvo
lum
eA
SIC
8M
14M
16M
24M
40M
64M
100
MC
hip
Freq
uenc
y(M
Hz)
On-
chip
-loca
lhig
hpe
rfor
man
ce75
01,
250
1,50
02,
100
3,50
06,
000
10,0
00O
n-ch
ip-a
cros
sch
iphi
ghpe
rfor
man
ce75
01,
200
1,40
01,
600
2,00
02,
500
3,00
0C
hip
Siz
e(m
m
Ë )D
RA
M28
040
044
556
079
011
2015
80M
PU
300
340
385
430
520
620
750
AS
IC48
080
085
090
010
0011
0013
00S
uppl
yV
olta
ge
Ì$ÍÍ (V
)1.
8-2.
51.
5-1.
81.
2-1.
51.
2-1.
50.
9-1.
20.
6-0.
90.
5-0.
6P
ower
(W)
Hig
hpe
rfor
man
cew
ithhe
atsi
nk70
9011
013
016
017
017
5B
atte
ryha
ndle
d1.
21.
41.
72.
02.
42.
83.
2
Speed/Performance Issue – Technical Problem
Gate and interconnect delay versus technology generation
ÎÉϢРϻÐÉÐ ÑÉϢРÒÉϢРÓ�ÔÉÐ Ó�ÑÉÐ Ó�ÐÉÐÕ×Ö�ØAÖÚÙÜÛ�ÝÞEßUØáà$Ø»âfãÐÏ
Ó�ÐÓÆÏÒ¢ÐÒÉÏÑ¢ÐÑÉÏä Ðä Ï
å�æç�è éêÜëìí
îðï¢ñ�ò
îóï¢ñ�òõô`ö÷ñ$øúùfûýüÿþ ö����îóï¢ñ�òðô`ö�ñ$ø����ü��Úô �
Õ Û�Ý�Ö�� Ö�� Û�����»â ß���� Ö��EÛ������ ���"! �7Þ$# ����»â ß���� Ö��EÛ������&%'�(!*)Úß,+ �- Ø�Ý�Ö�Ù/.;ßUØ»ØAÖ�.�Ý0� Ö��EÛ���� ���"! � Þ1# �- Ø�Ý�Ö�Ù/.;ßUØ»ØAÖ�.�Ý0� Ö��EÛ����&%2�3!*)Úß,+ �
�4�5!%'�6) ÞPØAÖ ä Ñ87 )ÚßUØ�9�4�5!%'� Ð5:�Ô87<;>= Þ .�?)Úß,+ � �A@CB"DFE�7Þ$# � �A@HG DFE%'� I DKJ 7MLON .Úâ�4� P DQE 7MLON .Úâ
The National Technology Roadmap for Semiconductors, 1997
MSICD’99 Univer sity of Rochester
2000
’s19
90’s
1980
’s19
70’s
Are
a
Pow
er
Spee
d/A
rea
Spee
d
Spee
d/Po
wer
Ultr
a-lo
w P
ower
Spee
d/Po
wer
/Noi
se
Des
ign
Goa
ls in
CM
OS
Inte
grat
ed C
ircu
its
Tim
e
MSICD’99 Univer sity of Rochester
Noise Coupling – The General Case
� Noise
NOISESOURCE Transmission medium
NOISERECEIVER
– Generation
– Transmission
– Reception
� General applications– Digital Influencing Digital– Analog Influencing Analog
� Mixed-signal applications– Digital Influencing Analog– Analog Influencing Digital
MSICD’99 Univer sity of Rochester
Concept of Noise in Digital CMOS ICs
� Definition of noise
“The word noise in the context of digital circuits means un-wanted variation of voltages and currents at the logic nodes.”
— Jan Rabaey, UC Berkeley
“Noise in a digital CMOS VLSI chip is predominantly due tocoupling from other digital nodes, and not caused by intrinsicnoise generated by FETs or by any other active devices.”
— Masakazu Shoji, AT&T Bell Labs
� Aggressor and victim interconnects
RTSU S
V S
RXWU W
V W
U S�WV S�W
Active signal Coupling noise
Aggressor Victim
MSICD’99 Univer sity of Rochester
Noise Margins in CMOS Digital Circuits
� Noise margin of a CMOS inverter
Y�Z$[]\�^2_6`ba
Y�Z$[]\�^8_6`ba
c�dfehg
cjiFkc�l/m cjlonc�p�m
c�p�nc�qrq
sttu ttv
sttu ttv
wyx]z
w a z
c�p�mcjl/m
c�p�nc l/n{}|,~ ^�� | ^ ~� ^��]�$[ |
� Decreasing noise margins
���y����h������
����������
��������b����b��8��������������2���,�Q�,�
�¡ £¢ �¥¤§¦ ¢�¨ ¦ ¢©,¢ª �,�4« �� �¢ �4¬� ¨ ¦ ¢©j¢ª ���4«¯® �
°�±¯²
°�±´³
��µ,¶·�h�� ���
�¸������,�
���]����y����y��8��������������2���,�K���
�� �¢ �¥¤8¦ ¢�¨ ¦ ¢©j¢ª �,�4« �¡ £¢ �4¬y� ¨ ¦ ¢©,¢ª �,�4«´® �
°�±¯²°�± ³
MSICD’99 Univer sity of Rochester
Noise in Mixed-Signal Integrated Circuits
Digital Influences Analog
� Analog circuits and signals
InOut
Common chip substrate
Noise
Digital Analog
Vid
Vdd
Vout
Zload Z load
-Vee
– Sensitive analog circuits can be highly susceptible to noise� Digital circuits and signals
– More tolerant to noise– The noise threshold is the noise that induces a change
of logical state� Typical examples
– Digital to Analog Converters– Analog to Digital Converters
MSICD’99 Univer sity of Rochester
Noise in Mixed-Signal Integrated Circuits
Analog Influences Digital
� In smart-power circuits
– High substrate noise levels are present
– A noise threshold can be surpassed
Common chip substrate
Noise
Vdd
In
Power GND
Analog
InOut
Digital
MSICD’99 Univer sity of Rochester
On-Chip Noise Sources in Integrated Circuits
� Substrate coupling noise (substrate crosstalk)
� Interconnect related coupling noise
– On-chip inductance– degradation of signal quality
–� �
/� � �
transmission lines– reflections due to impedance mismatch
– Capacitively and inductively coupled interconnect
� On-chip and off-chip simultaneous switching noise
� Transient ¹ �drops in the power distribution network
� Device related noise– inherent to the FETs
MSICD’99 Univer sity of Rochester
Design for Noise (DFN)
� Overall objective:
– Incorporate substrate and interconnect noiseinto the design process
� Provide a capability for estimating noise at thesystem (or chip) level
� Develop design strategies to reduce substrateand on-chip interconnect noise
MSICD’99 Univer sity of Rochester
Integrate Noise Informationinto the IC Design Flow
Noise Information
Application Specification
Architecture Definition
Logic Design
Circuit Design
Physical Layout
Extraction,
Simulation and Verification
Simulation and Verification
Simulation, and Verification
Fabrication
Simulation and Verification
MSICD’99 Univer sity of Rochester
Presentation Outline
� Introduction to noise in high speed CMOS integrated circuits
➱ Substrate coupling in mixed-signal integrated circuits
� On-chip inductance
� Peak noise estimation of coupled lossy transmission lines
� On-chip simultaneous switching noise voltage in the powerdistribution network
� Repeater insertion for driving� ���
interconnect
� Conclusions
MSICD’99 Univer sity of Rochester
Noise Flow Within Substrate
Noisy drain
P- Bulk
P+ N+ P+
0 50 100 150 200 250 300 350 400 450
10
0
50
40
30
20
Dis
tanc
e
N+ P+
P- Epi Layer
P+ Bulk
Substrate contact
P+
Substrate contact
0
50
40
30
20
Dis
tanc
e
10
Sensitive transistor
Substrate current flow in a lightly doped substrate
Substrate current flow in a highly doped substrate
(mic
rom
eter
s)(m
icro
met
ers)
Distance (micrometers)
* Wooley – IEEE JSSC’93
MSICD’99 Univer sity of Rochester
Classic Substrate Noise Waveforms
Volts
Time0 V
Vp-
p
0 V
(input signal)
Time
Noise generating signal transitions
Noise Voltage
Settling time
º Influence of
– Technology
– Process variables
– Physical layout
– Circuit design
* Wooley – IEEE JSSC’93Rubio – IEE PCDS’95Masui – IEEE IS VLSI’92Wooley – IEEE IEDM’96Fukuda – IEEE JSSC’96
MSICD’99 Univer sity of Rochester
Semiconductor Technologies
N+ N+
S G D G DS
P
P+ P+
D
P+
G
S G D
N+ N+P N-
P-DMOS
S G D
VMOSP
N+ N+
L
P P PN+ P
NN+
N
N+
N
N+
N
N+P+ P+P+
E B C C E C B
NPN Lateral PNP
P <100>
N+
N+
N
N+ N+P P
N
DSGS
P
N
N+ N+
S G D
P
S
P+
N
P+ P+
P+
Poly
P+
SiO2
P-N-well
N-
SiO2/Si3N4/SiO2
WordlineBitline
N+ N+ N+ N+
S G D G DS
P-
S G D G DS
P+
P
N+ N+
N
P+ P+
N
N+ N+
S G D G DS
P
P+ P+
S G D DS
P
N+ N+
N
P+ P+
G
P+ (N-)
P <111>
P P PN+ P
NN+
N
N+
N
N+
N
N+P+ P+P+
E B C C E C B
NPN Lateral PNP
N-
DMOS CMOS
NMOS (PMOS) DRAM Technology
CMOS P-well, no-epi CMOS N-well, epi layer
CMOS double-well High-Voltage CMOS
Bipolar technologies DMOS, VMOS technologies
BCD - Bipolar, CMOS, DMOS technologies
MSICD’99 Univer sity of Rochester
Process Variab les
» Process variables
– Substrate doping[Wooley1, Rubio]
– Noise reduction techniques[Wooley1, Rubio, Masui, Allstot]
– Substrate (epitaxial layer) thickness[Rubio]
– Backplane substrate contact[Wooley1, Rubio, Masui, Wooley2, Allstot]
– Bonding wires and number of pads[Wooley1, Rubio, Masui, Allstot]
* Wooley1 – IEEE JSSC’93Rubio – IEE PCDS’95Masui – IEEE IS VLSI’92Wooley2 – IEEE IEDM’96Allstot – IEEE JSSC’94
MSICD’99 Univer sity of Rochester
Circuit and Physical Design
» Circuit design
– Switching speed and transition times[Wooley1, Rubio, Wooley2]
– Interaction among different types of transistors[Rubio]
– Size of the logic circuits[Wooley2]
» Physical layout
– Distance between the noise source and receiver[Wooley1, Rubio, Lewis, Troutman]
– Placement of the substrate contacts[Wooley2]
– Routing of power lines[Allstot1, Vulih]
– Relative placement of the logic and analog blocks[Rubio, Allstot2]
* Wooley1 – IEEE JSSC’93Rubio – IEE PCDS’95Wooley2 – IEEE IEDM’96Lewis – IEEE IEDM’86Troutman – IEEE IEDM’84Allstot1 – IEEE JSSC’94Vulih – IEEE CICC’87Allstot2 – IEEE CICC’94
MSICD’99 Univer sity of Rochester
Appl ying Classic Noise Reduction Techniques
» Specially optimized technologies with increasedisolation [Bierman, Korec, Lanca, Baliga]
D S SG CEB
D S B E C C CE B
D
G
G S
P-
P+
N-
N+
N+
N+ N+P P
P+
N+P
N-
N+
N+
N-
NPNDMOS
P-
N+ P N+ P+
N-
P+ N+
N+
N+N+P P+
N-N- N- N- N-
N+
P+ P+ P+ P+
DMOS NPN PNP
N+ P+ P N+
N- TUB
SiO2
P-
N+ N- P
P+
N+ N+ N+P
P+ P+
N
D G S S G D S G D
The self-isolation technique
High VoltageLateral DMOS
NMOS PMOS
RESURF junction isolation technique
Dielectric isolation technique
POLYSILICON
The thick epitaxial layer junction isolation technique
* Bierman – Electronics’85Korec – SSMAT’95Lanca – ISIE’97Baliga – IEEE TED’86
MSICD’99 Univer sity of Rochester
Appr oach for System on a Chip (SOC)
» Constituent blocks of an SOC– Digital circuit blocks– Analog circuit blocks– Smart-power circuit blocks
» Presently, special technologies are used to mitigate noisein mixed-signal applications
» Primary research objectives:
– Eliminate the need for specialized technologies
– Permit low cost monolithic SOC integration withhigh performance
– Develop– Circuit and physical design solutions to improve
circuit noise immunity
– Create– Low cost smart-power circuitry
MSICD’99 Univer sity of Rochester
Circuit Characteristics» NMOS implementation - Thermal Ink Jet (TIJ) printer
– An analog high-power noise source– A digital noise receptor
[Verdonckt-Vandebroek – IEEE CDM’97]
In
In
Digital Input
Heater
PowerVdd
inverter1 inverter2
Out
Vcc
NMOS power driver
Out
In
ck
ckbar
clear
Q
Vdd
NMOS static slave latch
In
Vdd
Out
In
ckbar
ck
Q1 (small)
Q2 (large)
Vdd
NMOS dynamic latch
13 volt predriver
NMOS Inverter
MSICD’99 Univer sity of Rochester
Test cir cuits
¼ 50 NMOS test circuits have been fabricated in a 3.5 ½ m technologyto analyze the influence of
– Digital influencing analog issues [Wooley1, RubioWooley2, Allstot1, Lewis, Troutman, Vulih, Allstot2]
¾ Distance¾ Noise reduction techniques¾ Placement of substrate contacts¾ Switching speed and transition times¾ Interaction among different transistors¾ Routing of the power lines¾ Logic blocks placement and orientation
– Smart-power specific issues¾ Power driver supply voltage and current¾ Size of the noise source¾ Clock and signal conditioning¾ Power drivers “on-off” timing with respect to registerclocking¾ Duration of noise pulse¾ Chip temperature
* Wooley1 – IEEE JSSC’93Rubio – IEE PCDS’95Wooley2 – IEEE IEDM’96Allstot1 – IEEE JSSC’94Lewis – IEEE IEDM’86Troutman – IEEE IEDM’84Vulih – IEEE CICC’87Allstot2 – IEEE CICC’94
MSICD’99 Univer sity of Rochester
Physical Layout of Test Circuits
» Microphotograph of test circuit used to evaluateeffect of noise in digital registers from high-poweranalog drivers
» Floorplan
Pads
Sensitive registers
312927252321191715131197531
Drivers and heaters
Group 1 Group 2 Group 3 Group 8
8...321 8...32 8...321 8...3211
...
Predrivers
Select registers
MSICD’99 Univer sity of Rochester
Architectural Aspects
» Noise source
– High voltage and high current power drivers
» Noise medium
– Common substrate region
» Noise receptor
– Static and dynamic latches
Pads
Sensitive registers
312927252321191715131197531
Drivers and heaters
Group 1 Group 2 Group 3 Group 8
8...321 8...32 8...321 8...3211
...
Predrivers
Select registers
MSICD’99 Univer sity of Rochester
Physical Layout of Test Circuits
» Test circuit used to evaluate noise waveformswithin the substrate
MSICD’99 Univer sity of Rochester
Physical Layout Detail
» Microphotograph of the latch-predriver-driverinterface
MSICD’99 Univer sity of Rochester
Noise Distrib utions for Epi andNon-Epi Technologies
» Distributions for Epi technologies
» Distributions for Non-Epi technologies
MSICD’99 Univer sity of Rochester
Issues Specific to Noise Coupling
¼ Technology
– Substrate doping
– Substrate (epitaxial layer) thickness
– Backplane substrate contact
¼ Physical Design
– Distance between the noise sour ce and receiver
– Noise reduction techniques¾ Rings¾ Substrate contacts
– Placement of the substrate contacts
– Routing of the high current power lines
– Relative placement of the logic and analog bloc ks
¼ Circuit Design
– Switching speed and transition times
– Interaction among different types of transistors
– Size of the logic circuits
– Static vs. dynamic register s
MSICD’99 Univer sity of Rochester
Dependence of Noise on the Input Data
» A parasitic transition is induced at the registeroutput
– For static master-slave registers
¿ Only if input data is logic high
– For dynamic registers
¿ For both input logic high and logic low
¿ Input low is more sensitive than input high
Out
In
ck
ckbar
clear
Q
Vdd
Out
In
ckbar
ck
Q1 (small)
Q2 (large)
Vdd
NMOS Static Slave Latch NMOS Dynamic Latch
MSICD’99 Univer sity of Rochester
Dependence of Noise on Register Clocking
» Static registers– 4, 3, 2, 1 where 4 = best, 1 = worst
» Dynamic registers– 1, 2, 3, 4 where 1 = best, 4 = worst
Driver pulse
on
off
Input clock
1
2
3
4
5 (same as 4)
(same as 1)6
7 (same as 4)
t1 t2 t3 t4 t5 t6
8
t1t2
t7 t8
MSICD’99 Univer sity of Rochester
Dependence of Noise on Register Clocking(Cont.)
100
90
80
70
60
50
40
30
20
10 s-4
s-3
s-2
s-1
d-1
d-2
d-3
d-4
Noise level (%)
¼ Relative dependency shown in number of affectedregisters
¼ The number of affected dynamic registers (d-4) is 1.3X largerthan the number of affected static registers (s-1)
¼ Noise tolerance further improved with
– Substrate contact placement
– Ground routing
– Register orientation¾ Depletion transistors placed closer to the noise source
MSICD’99 Univer sity of Rochester
Dependence of Noise on Distance
100
77
91
Noise level (%)
static500
static350dynamic350
dynamic500
» Relative dependency shown in number of affectedregisters
» The number of affected dynamic registers (dynamic350) is1.15X larger than the number of affected static registers(static350)
» Two distances evaluated– 350 À m– 500 À m
MSICD’99 Univer sity of Rochester
Noise Spreading Effects
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
34
30
26
22
18
14
10
6
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 3134
30
26
22
18
14
10
6
Clocking regime No. 2. Static registers.
Power driver power supply (Volts)
Register number
Clocking regime No. 3. Static registers.
Power driver power supply (Volts)
Register number
» Specific registers are affected depending on– Clocking regime– Ground bias– Active power driver group
MSICD’99 Univer sity of Rochester
Influence of Analog Power Suppl y
» More registers are affected as
– The driver power supply increases
– The clocking regime changes
– The noise pulse duration increases
0
5
10
15
20
25
30
35
0 5 10 15 20 25 30 35 40
No.
of a
ffect
ed r
egis
ters
Á
Drivers applied voltage (V)
"static1""static2""static3""static4"
» Slight dependency with chip temperature is noted
– Less than 5% for a 25 Â to 55 Â C temperature sweep range
MSICD’99 Univer sity of Rochester
Influence of the Size of the Noise Source
100
90
80
70
60
50
40
30
20
10
76
5
4
3
7
6
Noise level (%) clocking situation 1 clocking situation 4
» Relative dependency shown in number of affectedregisters
» The number of registers is 30X smaller forclocking regime 4 (seven active drivers) thanfor clocking regime 1 (seven active drivers)
» The noise tolerance improves for on-chip connecteddigital and analog ground lines
MSICD’99 Univer sity of Rochester
Related Publicationson Substrate Coupling
à R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Mor-ton, W. Staub, T. Tellier, and E. G. Friedman, “Substrate Noise Distribution andPlacement of Substrate Contacts to Alleviate Substrate Noise in Epi and Non-Epi Technologies,” Proceedings of the 23rd Annual IEEE EDS/CAS Activities inWestern New York Conference, pp. 10-11, November 1999.
à R. M. Secareanu, I. S. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub,T. Tellier, and E. G. Friedman, “The Behavior of Digital Circuits under SubstrateNoise in a Mixed-Signal Smart Power Environment,” Proceedings of the IEEEInternational Symposium on Power Semiconductor Devices and ICs, pp. 253-256, May 1999.
à R. M. Secareanu, I. S. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub,T. Tellier, and E. G. Friedman, “Noise Immunity of Digital Circuits in Mixed-SignalSmart Power Systems,” Proceedings of the IEEE Great Lakes Symposium onVLSI, pp. 314-317, February 1999.
MSICD’99 Univer sity of Rochester
Presentation Outline
» Introduction to noise in high speed CMOS integrated circuits
» Substrate coupling in mixed-signal integrated circuits
➱ On-chip inductance
» Peak noise estimation of coupled lossy transmission lines
» On-chip simultaneous switching noise voltage in the powerdistribution network
» Repeater insertion for driving Ä ÅÇÆ interconnect
» Conclusions
MSICD’99 Univer sity of Rochester