A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate
Transistors, Enhanced Channel Strain and 0.171um2 SRAM Cell Size in a 291Mb Array
S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C-H Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani,
O. Golonzka, W. Han, J. He*, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S-H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg,
J. Neirynck, P. Packan, S. Pae*, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger,
C. Weber**, M. Yang, A. Yeoh, K. Zhang
Logic Technology Development, *QRE, ** TCADIntel Corporation
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Outline
• Process Features• Transistors• Interconnects• Circuits• Conclusions
3
Process Features
• 32nm Groundrules• 193nm Immersion Lithography• 2nd Generation High-K + Metal Gate • 4th Generation Strained Silicon• 9 Cu Interconnect Layers
– Low-k CDO / SiCN dielectric
• Cu bump with Lead-free Packaging
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32nm Design Rules
~0.7x linear scaling from 45nm
Layer Pitch (nm) Thick (nm) Aspect RatioIsolation 140.0 200 --Contacted Gate 112.5 35 --Metal 1 112.5 95 1.7Metal 2 112.5 95 1.7Metal 3 112.5 95 1.7Metal 4 168.8 151 1.8Metal 5 225.0 204 1.8Metal 6 337.6 303 1.8Metal 7 450.1 388 1.7Metal 8 566.5 504 1.8Metal 9 19.4um 8um 1.5
5
100
1000
250nm 180nm 130nm 90nm 65nm 45nm 32nmTechnology Node
Cont
acte
d G
ate
Pitc
h (n
m)
Contacted Gate Pitch0.7x every 2 years
Contacted Gate Pitch• Transistor gate pitch of 112.5nm • Continues 0.7x per generation scaling
Tightest contacted gate pitch reported for 32nm generation
Pitch
6
0.1
1
10
250nm 180nm 130nm 90nm 65nm 45nm 32nmTechnology Node
SRAM
Cel
l Are
a (u
m2 ) SRAM Cell Area0.5x every 2 years
SRAM Cells• 0.171 um2 SRAM cell
Transistor density doubles every two years
7
0.1
1.0
10.0
90nm 65nm 45nm 32nm
SRA
M A
rray
Den
sity
(Mb/
mm
2 )
SRAM Array Density• SRAM array density achieves 4.2 Mb/mm2
– Includes row/column drivers and other circuitry
Array density scales at ~2X per generation
4.2 Mb/mm2
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Outline
• Process Features• Transistors• Interconnects• Circuits • Conclusions
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Key Transistor Features• 30nm gate length with 112.5nm contacted gate
pitch
• 2nd generation Hi-k + Metal Gate– 0.9nm EOT Hi-K with dual workfunction metal gate
electrodes– Continued use of Replacement Metal Gate approach
• Metal gate deposition after high temperature anneals• Integrated with strained silicon process
– Transistor mask count same as 45nm– Adds ~4% process cost over non hi-k/MG
• 4th generation of strained silicon
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Device Characteristics
Excellent Vt roll-off and DIBLWell controlled short channel effects Subthreshold slope ~100 mV/decade
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
1E-2
-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00Vgs (V)
Id (A
/um
)
SS ~ 98mV/decDIBL ~130mV/V
SS ~ 98mV/decDIBL ~160mV/V
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
25 30 35 40 45Lgate (nm)
Vt (V
)
Vt, Vds=0.05V
Vt, Vds=1.0V
NMOS
PMOS
Vt, Vds=-1.0V
Vt, Vds=-0.05V
NMOSPMOS
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Vdd=1.0V
1
10
100
1000
1 1.2 1.4 1.6 1.8 2Idsat (mA/um)
Ioff
(nA
/um
)NMOS IDSAT vs. IOFF
1.55 mA/!m at IOFF = 100 nA/!m14% better than 45nm
112.5 nm
45nm: Mistry, 2007 IEDM
45nm
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Vdd=1.0V
1
10
100
1000
0.8 1 1.2 1.4 1.6 1.8|Idsat| (mA/um)
Ioff
(nA
/um
)PMOS IDSAT vs. IOFF
1.31 mA/!m at IOFF = 100 nA/!m22% better than 45nm
32nm PMOS Idsat almost equal to 45nm NMOS Idsat!
112.5 nm
45nm: Mistry, 2007 IEDM
45nm
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1
10
100
1000
0.17 0.19 0.21 0.23 0.25 0.27Idlin (mA/um)
Ioff
(nA
/um
)
Vdd = 1.0VVds = 0.05V
NMOS IDLIN vs. IOFF
0.228 mA/!m at IOFF = 100 nA/!m19% better than 45nm
112.5 nm
45nm: Mistry, 2007 IEDM
45nm
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Vdd = 1.0VVds = 0.05V
1
10
100
1000
0.14 0.16 0.18 0.2 0.22 0.24 0.26|Idlin| (mA/um)
Ioff
(nA
/um
)PMOS IDLIN vs. IOFF
0.228 mA/!m at IOFF = 100 nA/!m28% better than 45nm
Average 20% NMOS/PMOS Sat/Lin drive current gain over 45nm
45nm: Mistry, 2007 IEDM
45nm
112.5 nm
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Transistor Performance vs. Gate Pitch
Highest reported drive current at tightest reported gate pitchSimultaneous performance and density improvement
90nm: Mistry, 2004 VLSI65nm: Tyagi, 2005 IEDM45nm: Mistry, 2007 IEDM
1001000 Contacted Gate Pitch (nm)
IDSA
T (m
A/u
m)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
PMOS
NMOS
160nm (45nm)
220nm (65nm)
320nm (90nm)
1.0V, 100 nA/!m
Gate Pitch (Generation)
112.5nm (32nm)
1001000 Contacted Gate Pitch (nm)
IDSA
T (m
A/u
m)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
PMOS
NMOS
160nm (45nm)
220nm (65nm)
320nm (90nm)
1.0V, 100 nA/!m
Gate Pitch (Generation)
112.5nm (32nm)
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1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
4 6 8 10 12 14 16
Field (MV/cm)
TDD
B (s
ec)
45nmHK+MG
32nmHK+MG
Transistor Reliability - TDDB
32nm supports 10-15% higher E-fieldEnables same voltage with lower EOT
45nm: Mistry, 2007 IEDM
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Outline
• Process Features• Transistors• Interconnects• Circuits• Conclusions
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Interconnects
• Metal 1-3 pitches match transistor pitch• Graduated upper level pitches optimize density &
performance• Extensive use of low-k ILD and SiCN
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Outline
• Process Features• Transistors• Interconnects• Circuits• Conclusions
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32nm shuttle with SRAM and key Logic circuitsAllows early co-optimization of process and design
291 Mbit SRAM arrayPROM arrayHigh speed register fileHigh speed I/O circuitsHigh frequency PLL/Clock
Discrete test structures
32nm Shuttle
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SRAM Test Vehicle• 291 Mb, 0.171um2 SRAM Cell
– >1.9B transistors– First reported functional operation in Sep ‘07
• Process learning vehicle demonstrates– High yield– High performance– Stable low voltage operation
1.300V +**********************************************.....
1.250V |******************************************** .
1.200V |******************************************* .
1.150V |***************************************** .
1.100V |*************************************** . .
1.050V +***********************************...............
1.000V |******************************** . .
0.950V |**************************** . . .
0.925V +*********.****.*.****..............................
+---------+---------+---------+---------+---------+
2GHz 2.29GHz 2.66GHz 3.2GHz 4GHz 5.33GHz
3.8GHz
1.300V +**********************************************.....
1.250V |******************************************** .
1.200V |******************************************* .
1.150V |***************************************** .
1.100V |*************************************** . .
1.050V +***********************************...............
1.000V |******************************** . .
0.950V |**************************** . . .
0.925V +*********.****.*.****..............................
+---------+---------+---------+---------+---------+
2GHz 2.29GHz 2.66GHz 3.2GHz 4GHz 5.33GHz
3.8GHz
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SRAM Vmin
Vmin distribution for 3.25Mb sub-arraysHealthy 770mV median Vmin
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Def
ect D
ensi
ty (l
og s
cale
)
SRAM Yield
32nm SRAM yield maintains 2-year cadence
2 Years
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Outline
• Process Features• Transistors• Interconnects• Circuits• Conclusions
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Conclusions• An industry leading 32nm logic technology is presented• Continues Moore’s law relative to 45nm:
– 0.7x contacted gate pitch scaling– 0.5x SRAM cell size scaling– 2.2x array density scaling
• Record linear and saturated transistor drive currents achieved – Average of 20% improvement in drive current over 45nm
• Healthy yield achieved on 291Mb SRAM with 0.171 um2
SRAM cell size and excellent low voltage operation• Completed development phase on 32nm CMOS
– On track for production readiness in H2’09
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Acknowledgements
• The authors gratefully acknowledge the many people in the following organizations at Intel who contributed to this work:– Logic Technology Development – Quality and Reliability Engineering– Technology CAD– Assembly & Test Technology Development
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