Femto Base Station Technology, Featuring a Single … · BSC913x SoC Partner L2 / L3 Stack ......

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,

ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,

Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of

Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,

CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and

Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

.

Michael Liu

Senior Staff Application Engineer

August 2012

TM 2

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

• Introduction

• BSC913x product overview

• Reference Board overview

• LTE L1 Software Architecture

• Femto API usage

• System Testing environment

• Conclusion

3 TM






Tested Integration

Commercial LTE L1 Software

Reference Board Design

BSC913x SoC Partner L2 / L3 Stack

Complete LTE Femto

Solution

4 TM






Single Chip Femto Basestation • Home Femtocell up to 8 users – BSC9130

• SMB Femtocell up to 16 users – BSC9131

• Multimode

Multi Standard Architecture • Standards support: LTE (Rel. 9), WCDMA (Rel. 99/7/8)

• LTE - 20MHz single sector -100Mbps / DL 50 Mbps UL

• HSPA+ - 5MHz single sector 42Mbps / DL 11 Mbps UL

• Processing Layers: PHY-MAC-RLC-PDCP-NTP

• Enabled with 2x2 MiMO

• 2G/3G Sniffing and GPS Support

SoC Architecture • PowerTM e500 Core subsystem (800MHz - 1GHz)

• Starcore SC3850 Core subsystem (800MHz - 1GHz)

• MAPLE-B2F Baseband Accelerators Platform

• eTVPE – Turbo/Viterbi Decoder

• DEPE – Turbo Encoder w/ rate match

• CRCPE – CRC check & insertion

• FTPE – FFT/DFT

• PDPE, PUPE

• UMTS Chiprate

• Security engine - IPSec, Kasumi, Snow-3G

• Secured boot

• Single DDR3 Controller 32b 800MHz

• IEEE1588 v2, NTP

• USB 2.0

• 2x Ethernet RGMII and IEEE1588v2

• 3x JESD207/ADI/MAXPHY RF transceiver interfaces

Multicore Fabric

MAPLE-B2F

Baseband

Accelerators

LTE/UMTS/CDMA2K

DMA Security

Engine

v4.4

Power™

e500 Core

D-Cache I-Cache 32 KB 32 KB

Starcore

SC3850 DSP Core

D-Cache I-Cache

512KB

Backside

L2 Cache 32 KB 32 KB

JE

SD

207/A

DI/

MA

XP

HY

US

B 2

.0

32-bit

DDR-3

800MHz 256 KB L2 cache

Clocks/Reset

I2C

SPI

GPIO

DUART Ethernet

1GE IEEE 1588

1GE

5 TM






Single Chip - Pico Basestation • Standards support: LTE (Rel. 8/9), WCDMA

(Rel. 99/7/8/9), 802.16e

• Bandwidth: 20MHz or 2x 10MHz

• 100 LTE or 64/96 HSPA/AMR active users

• Multimode support

• LTE throughputs: 150Mbps DL / 75Mbps UL

with 2x4 ant.

• HSPA+ throughputs: Dual carrier - 84MbpsDL

/23Mbps UL

• WiMAX 802.16e: up to 50Mbps DL/13Mbps UL

• 2G/3G Sniffing and GPS Support

• Secured Boot & Trust Architecture support

• Proc. Layers: PHY-MAC-RLC-PDCP-Transport

Architecture • Dual PowerTM e500mc core (1GHz/1.2GHz)

• Dual Starcore SC3850 DSP (1GHz/1.2GHz)

• MAPLE-B2P Baseband Accelerators Platform

• Security engine - IPSec, Kasumi, Snow-3G

• Dual DDR3/3L, 32b,1.333GHz, w/ ECC

• IEEE1588 v2, NTP

• USB 2.0

• 4 SerDes lanes, combining:

• 2x Ethernet 1G SGMII

• 2x CPRI v4.1 @ 6.144G antenna

interface

• 1x PCIe @ 5G x2 lanes

• Quad JESD207/ADI RF transceiver interfaces

• NAND/NOR Flash controller, eSDHC, USIM

• I2C, eSPI

• Package – FCPBGA, 23mmx23mm, 0.8mm

Multicore Fabric

32 KB

Shared

M3

Clocks/Reset

2x I2C

SPI

GPIO

DUART

Power™

e500 Core


32-bit

DDR-3

1.3GHz

Shared 512 KB L2 cache

32-bit

DDR-3

1.3GHz

Coherency module

Starcore

SC3850 DSP Core


512KB L2 cache

x2

MAPLE-B2P

Baseband

Accelerators

LTE/UMTS /WiMAX

DMA Security

Engine

v4.4

US

B 2

.0

CP

RI 4

.1

x2

Ethernet

1GE

SGMII

IEEE 1588

4 - lanes SerDes

1GE PCIe

JE

SD

20

7/A

DI

x4

IFC

USIM

eSDHC

6 TM






Debug Header

UART Header

DSP Debug Header A/D

Temperature

Sensors

BSC9131

RJ45

RJ45

RGMIIPHY

RGMIIPHY

USB PHY

USB Mini

Type AB Conn

1GB DDR3-

800 SDRAM

128 MB NAND Flash

GPS Module

SIM Socket

Indicator LEDs

Power Regulation

TDM SLIC

RJ11

DDRC IFC GPIO

DUART DSP JTAG

JTAG

SIM

TDM

VeTSEC

VeTSEC

USB

ANT3

MaxPhy

SPI4

ANT1

SPI3

SPI1

ANT2

SPI2

DUART

RF

Card 1

RF

Card 2

I2C

1588

LTE

RADIO

WCDMA

RADIO

7 TM






• Performance optimization

Target performance requires appropriate software architecture and optimal usage of

accelerators.

Long development cycle to achieve code optimization on the last 20% of improvement

• Reusability and migration

The software architecture should scale from Femto to Macro

Should cover different flavors of MAPLE accelerators and multicore environments

Typically Femto PHY with ~ 100 KLOC

• Test and validation

Femto business model requires fully validated PHY including 3GPP conformance tests

T&V investment has to move from component testing to full system integration testing

• Ease of integration with L2 Stack

Use of standardized interfaces (ex. FAPI)

Smart support functionality for debug, error reporting, statistics, etc.

8 TM






Reduced Scheduling Overhead

• Run-to-completion scheduler with deterministic scheduling intervals

• Reduced cost for runtime decisions as worst case sequence is always scheduled

• Simplified multicore aware scheduler engine

SDOS

DL

ctrl PDSCH

PUSCH

Data

PUSCH

CQI

PUSCH

RSP

RACH

PUCCH

1/1a/1b

PUCCH

2/2a/2b

SRS Meas.

L1 / L2 Interface

RT Scheduler Framework Antenna IF Man

Simplified Control Layer

• Removed overhead of multiple

control and translation layers

• L2 FAPI messages are directly

parsers by each component

• Zero memcopy for L2 ctrl /

payload

Seamless MAPLE Access

• Components access MAPLE

directly through SDOS

• No additional communication

layer

9 TM






• High data rate shared channel operations on MAPLE:

− DL-SCH/PCH on DEPE

− PDSCH on PDPE + eFTPE

− PUSCH descrambling and demodulation on PUPE

− UL-SCH on eTVPE+PUPE

• Remaining UL channels and signals on StarCore:

− PUSCH

StarCore support on Equalization and CE

− RACH and Sounding with DFT / FFT support on MAPLE

− PUCCH

− Addional measurements

• Remaining low data rate control channels on StarCore:

− Data encoding and mapping for first control symbols (CFI, HI, DCI, PCFICH, PHICH, PDCCH) excl. IFFT

− BCH / PBCH

DL

UL

Data Control

DL-SCH PCH BCH MCH

PDSCH PBCH PMCH

CFI HI DCI

PHICH PDCCH PCFICH

UL-SCH RACH

PUSCH PRACH

UCI

PUCCH

+ DL synchronization signal on StarCore

SRS

SC3850

MAPLE

10 TM






eFTPE FFT GR

CP Rem FFT

Guard R.

eFTPE

eFTPE

2/2 tfje

IDFT eTVPE

CE TOE FOE

PUSCH_EDF MAPLE – B2F

PUSCH Ref. Symbols (Frequency domain CE)

CE

PUCCH, all formats

IDFT UE

separation TOE

ZC

FIR Delay profile compute

RACH

SRS

ZC

Antenna Data

TB out

Control output

RACH output

PUPE

cores Maple

legend N

est.

EQ DTX / RMDec

Delay profile analyze

f

eFTPE

IFFT

eFTPE DFT GR

f

SNR est

SRS output

f

EQ

H N

CRCPE

PUSCH_EDF MAPLE – B2P

11 TM






• MAPLE accelerates the full downlink data path

• Core intervention is only needed for the control symbols

• Higher data rate has hence no impact on the core loading

TB input

Control intput

PDCCH

DEPE PDPE

PDSCH_EDF

Downlink controls symbols in SW

eFTPE

Guard insert IFFT

CP insert

Ant Data

CRCPE

PBCH, RS

cores Maple

legend

PHICH

PCFICH

12 TM






• L1 scheduling follows run-to-

completion model.

• The component definition and

scheduling is driven by memory

footprint optimization.

• The scheduling scheme is

tailored for the worst case load.

• Each component is statically

tiggered based on the symbol

intervals

• The FAPI control information

will determine which

components are actually

executed in each subframe

• RACH processing is spread out

over the subframe with filtering

operations every symbol.

Sym Id Tasks

0 FAPI_Parser (N), PUCCH_Copy (N-1), EQU(N-1)

1 RACH_TDP(N), PUSCH_EDF(N-1),

PUCCH_F1(N-1), PUCCH_F2(N-1)

2 RACH_TDP(N)

3 RACH_TDP(N)

4 RACH_TDP(N), RSP(N)

5 EQU(N), SRS_AP(N-1)

6 2xRACH_TDP(N)

7 RACH_TDP(N), PUCCH_Copy(N), EQU(N)

8 RACH_TDP(N), PDSCH(N+1), PDCCH(N+1)

9 SRS_UM(N-1)

10 2xRACH_TDP(N)

11 RACH_TDP(N), RSP(N)

12 RACH_TDP(N), RACH_FDP(N), EQU(N),

RACH_DPP(N)

13 FAPI_Indications(N)

13 TM






• FAPI defines 4 relevant interfaces for the LTE L1:

− P4 for all network listening operations (radio sniffing)

− P5 for L1 mode control (start, stop etc)

− P7 for the main data path

− P8 for diagnostics

14 TM






• FAPI defines 4 PHY states:

− IDLE: PHY is ready to be configured

for a certain deployment

− CONFIGURED: PHY is configured

and ready for reconfiguration or for

subframe operation

− RUNNING: PHY is in running state.

Every TTI, the PHY receives UL and

DL subframe requests that configure

all operations within this coming TTI.

− NMM: Network listening mode. The

PHY is ready to listen to other radio

signals for measurements.

• The FAPI spec supports the

implementation of a stateless PHY

where all user information is stored on

the L2

15 TM






• The L1/L2 interface follows the FAPI standard

• Some minor changes were added for performance optimization (padding, payload pointers)

• Additional vendor specific fields are used for advanced measurements and additional control options

• The FAPI messages are mapped on a set of interprocessor communication channels (IPC) that handle all communication between the cores

16 TM






• HARQ round trip delay of 8 ms • The eNB has a budget of 4 ms before sending a response:

• 1 ms of data reception • < 1 ms for the UL L1 processing • < 1 ms for L2 • 0.3 ms for DL L1 processing

17 TM






• L1/L2 Wireshark Trace

− All FAPI events are sent to a host and can be analyzed using the

Wireshark tool

− Same information is logged in DDR memory for post mortem debug

• Offline analysis of DDR trace

− Logs of all real time events

− Uses CodeWarrior tools to read from memory

− Primarily used in lab environment

• Deput Print Agent: Runtime trace on debug host

− Extracts and displays the trace information on the host while target

is running in real time.

− Currently the same scope of events as the DDR trace

18 TM






CodeWarrior PC

PC2, Windows XP

CodeWarrior for L1

9131 RDB

RF Card

PSC 9131

eNodeB

L1

eNodeB

L2/L3

RF

JTAG

Linux BSP PC

PC3, Linux FC11

(L2/L3 build, Wireshark and Minicom)

EPC PC

PC4, Linux FC11EPC Core Network Simulator (MME/

S-GW/P-GW)

LAN 2

172.16.118.144

172.16.118.18

172.16.118.151

SERIAL

Antenna

UTRAN - FAP EPC

User 1Laptop with Pantech data card

User 0Laptop with PanTech data card

UE

19 TM






• 3GPP Release 8 standard compliancy

• Band support

5 / 10 / 15 / 20 MHz support

Support for band 1,7,13. Can easily be extended to other bands without L1 changes

• Downlink 2x2 MIMO Support

• Localized and Distributed PDSCH, Localized PUSCH

• Downlink Control Channel Support (PDCCH, PHICH, PFICH, BCH,SSH)

• All PUCCH Formats (1/1a/1b/2/2a/2b)

• Sounding channel support

• Handover and Measurements Support

• Closed Loop Power Control (PUCCH, PUSCH)

• FAPI Compliant (Partial and Full Reconfiguration)

• Cell Search support for LTE

• Interoperability with Test and Commercial UEs (PanTech, FFA, Signalion, AeroFlex)

TM 20






Session materials will be posted @ www.freescale.com/FTF

Weibo? Please use hashtag

#FTF2012#

Freescale on Kaixin Tag yourself in photos

and upload your own!

• The BSC913x provides an architecture for a scalable and

efficient implementation of the eNode-B functionality on a single

chip

• Along with the SoC, Freescale offers a commercial LTE L1

software that is designed to make best use of the available

hardware functionality

• The L1 functionality can be treated as a black box controlled

through an API that follows the Femto API recommendations

• Freescale has integrated the L1 with L2/L3 stacks from Aricent

and Radisys to enable end-to-end system testing

http://www.freescale.com/FTF

TM

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