Date post: | 31-Oct-2014 |
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B Sravani 09B81A0491 K Tejaswi 09B81A04A6 Sudheer 09B81A0494
Internal Guide assoc prof Mrs. Ester Rani
To design low power radix-2 FFT processor using MTCMOS technique.
The Fast Fourier Transform (FFT) is a critical block and widely used in digital signal Processing.
With the advent of semiconductor processing technology in VLSI system, it has enabled the performance of FFT design to increase steadily and applied in portable application design.
However, as semiconductor technologies move toward finer size and geometries FFT design has also faced challenges in power increment in the design.
Leakage power has become a major concern for the CMOS circuits in deep sub-micron process.
This project deals with technique which reduces the leakage power in fft processor.
MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode.
The simple FFT processor is to be designed with MTCMOS to reduce its standby power.
sleep
sleep
LOW VT LOGICHIGH VT
Header and/or Footer
• Low VT gates for speed• High VT gates for low leakage
The leakage power consumptions of the individual blocks in FFT are to be compared with those of using MTCMOS.
Comparisons are to be made between leakage power of FFT in fine grain FFT and CMOS FFT.
The designing and comparisons are to be done using the 90nm CMOS technology
RADIX 2 RADIX 2
RADIX-2 RADIX -2
MUL 1
MUL 1
Real x(1)
Img x(1)
Img x(0)
Img x(2)
Img x(3)
Real x(2)
Real x(3)
Real x(0)
MUL
MUL
Real X(0)
Img X(0)
Real X(1)
Img X(1)
Real X(2)
Img X(2)
Real X(4)
Img X(4)
Cadence tools Design and comparisons are to be
made using 90nm CMOS technology.
ADDER
ADDER
SUB
SUB
i/p Real x0
i/p Img x0
i/p Real x1
i/p Img x1
O/p _x0 real
o/p_x0 img
o/p real x1
o/p img x1
MUL
MUL
MUL
MUL
SUB
ADDER
o/p_Real x1
o/p_Img x1
Real
img
tiddle factor(W)
o/p_x1 real
o/p_x1 Img