Training Project of VLSI

7/31/2019 Training Project of VLSI

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Training Report

On

Title of the Training

Submitted in the partial fulfillment of the requirement for the award of degree

of

Bachelors of Technology

In

Electronics & Communication Engineering

Submitted by:

Name: Syed Mohammad Faiz

Reg. Number:10902647Name and Location of Company: DKOP Labs Pvt. Ltd.,Sector-2,Noida

Period Training: 01/06/2012- 14/07/2012

Department of Electronics & Comm. Engg

Lovely Professional University

Phagwara140401, Punjab (India)Ph. (01824-506960-61)

Department of Electronics & Communication Engineering

Lovely Professional University Phagwara (Distt. Kapurthala)Punjab India 144001


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Ref:______________ Dated: __________

Certificate

Certified that this Training entitled VLSI Design submitted by Syed Mohammad Faiz

(10902647), students of Electronics & Communication Engineering Department, Lovely

Professional University, Phagwara Punjab in the partial fulfillment of the requirement for the

award of Bachelors of Technology (Electronics & Communication Engineering) Degree of

LPU, is a record of students own study carried under my supervision & guidance.

Mr. Sandeep Gupta

Name and Signature of Training Supervisor

Designation:- Chief Learning Officer


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Acknowledgement

In my six weak industrial training it is a wonderful experience to be a part of DESIGN KOPLABSwhere I have opportunity to work under brilliant minds. I owe my deep regards for thesupporting and kind staff authorities who are helping me in my lean patches during these sixweak. The knowledge I am gaining throughout my studies have the practical implementationduring this period. I am grateful to all the staff of DKOP LABS and for their timely supportand sharing of their experience with me. I would like to express my heartiest concern for Mr.Ajeet Kumar Singh for his able guidance and for his inspiring attitude, praiseworthy attitudeand honest support. Not to forget the pain staking efforts of our college training and placementcell and specially my training and placement officer.Last but not the least I would express myutmost regards for the electronics and communication department of our Institute.


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Attachment

Of

Training Certificate issued from training institute

with specific training area


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TABLE OF CONTENTS

S. NO. TITLE PAGE NO.

1. INTRODUCTION 7 to 92. ORGANIZATION AND REQUIREMENT 10 to 15

2.1. VLSI Design Flow2.2. HDL(Hardware Description Language)2.2.1. Design using HDLs2.2.2. Simulating and Debugging HDL code2.2.3. Design verifications with HDLs2.3. HDL and programming languages2.4. Importance of HDLs2.5. Advantages of HDL2.6. Disadvantages of HDL

3. EXECUTION OF WORK 16 to 443.1. VERILOG(Verify Logic)3.1.1. History of verilog3.1.2. Design methodology3.1.3. General syntax for writing VERILOG program3.1.4. What is MODULE in verilog3.1.5. First verilog program3.1.6. Language elements3.2. Different types of modeling used in verilog3.2.1. Gate level modeling3.2.2. Data flow modeling

3.2.2.1.Operators3.2.3. Behavioral modeling3.2.3.1.Types of Statements3.2.4. Switch level modeling3.2.4.1.... Cmos(complimentary metal oxide semiconducator)3.2.4.2.Cmos inverter3.3. FPGA(Field Programmable Gate Array)3.3.1. FPGA Comparisons3.3.2. FPGA Architecture3.3.3. FPGA Design and Programming3.4. CPLD(Complex Programmable Logic Device)

4. HARDWARE/ SOFTWARE IMPLIMENATION 45 to 484.1. EDA(Electronic Design Automation) tools4.1.1. History of EDA tools4.1.2. Current status4.2. Software focuses on Design4.3. Modelsim simulator4.3.1. Introduction4.3.2. Creating the working library

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4.3.3. Project flow4.3.4. Multiple library flow

5. SIMULATIVE/ HARWARE ANALYSIS 49 to 505.1. UART5.2. UART Specifications

5.3. UART Receiving Subsystem5.4. UART Transmitting Subsystem5.5. Entire UART System

6. REFERENCES 517. FUTURE SCOPE OF TRAINING 52

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1. INTRODUCTION

What is an IC (integrated circuit)?

A chip or die where many circuit components and the wiring that connects them aremanufactured simultaneously.

Integrated circuits are used in almost all electronic equipment in use today and haverevolutionized the world of electronics.

A hybrid integrated circuit is a miniaturized electronic circuit constructed of individualsemiconductor devices, as well as passive components, bonded to a substrate or circuit board.

Integrated circuits were made possible by experimental discoveries which showed thatsemiconductor devices could perform the functions of vacuum tubes and by mid-20th-century

technology advancements in semiconductor device fabrication the integration of large numbersof tiny transistors into a small chip was an enormous improvement over the manual assembly ofcircuits using electronic components. The integrated circuit's mass production capability,reliability, and building-block approach to circuit design ensured the rapid adoption ofstandardized ICs in place of designs using discrete transistors.

There are two main advantages of ICs over discrete circuits: cost and performance. Cost is lowbecause the chips, with all their components, are printed as a unit by photolithography and notconstructed as one transistor at a time. Furthermore, much less material is used to construct acircuit as a packaged IC die than as a discrete circuit. Performance is high since the componentsswitch quickly and consume little power (compared to their discrete counterparts) because the

components are small and close together

Generations of IC (Integrated Circuits)

The first integrated circuits contained only a few transistors. Called "Small-Scale Integration"(SSI), digital circuits containing transistors numbering in the tens provided a few logic gates forexample, while early linear ICs such as the Plessey SL201 or the Philips TAA320 had as few astwo transistors.SSI circuits were crucial to early aerospace projects, and vice-versa. Both the Minuteman missileand Apollo program needed lightweight digital computers for their inertial guidance systems; theApollo guidance computer led and motivated the integrated-circuit technology

The next step in the development of integrated circuits, taken in the late 1960s, introduceddevices which contained hundreds of transistors on each chip, called "Medium-Scale Integration"(MSI).

They were attractive economically because while they cost little more to produce than SSIdevices, they allowed more complex systems to be produced using smaller circuit boards, less

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assembly work (because of fewer separate components), and a number of other advantages.Further development, driven by the same economic factors, led to "Large-Scale Integration"(LSI) in the mid 1970s, with tens of thousands of transistors per chip.

Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that

began to be manufactured in moderate quantities in the early 1970s, had under 4000 transistors.True LSI circuits, approaching 10000 transistors, began to be produced around 1974, forcomputer main memories and second-generation microprocessors

The final step in the development process, starting in the 1980s and continuing through thepresent, was "very large-scale integration" (VLSI). The development started with hundreds ofthousands of transistors in the early 1980s, and continues beyond several billion transistors as of2009.

There was no single breakthrough that allowed this increase in complexity, though many factorshelped. Manufacturers moved to smaller rules and cleaner fabs, so that they could make chips

with more transistors and maintain adequate yield.

Advances of Integrated circuits

Among the most advanced integrated circuits are the microprocessors or "cores", which controleverything from computers to cellular phones to digital microwave ovens. Digital memory chipsand ASICs are examples of other families of integrated circuits that are important to the moderninformation society.

While the cost of designing and developing a complex integrated circuit is quite high, whenspread across typically millions of production units the individual IC cost is minimized. The

performance of ICs is high because the small size allows short traces which in turn allows lowpower logic (such as CMOS) to be used at fast switching speeds.

ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry tobe packed on each chip. This increased capacity per unit area can be used to decrease cost and/orincrease functionalitysee Moore's law which, in its modern interpretation, states that thenumber of transistors in an integrated circuit doubles every two years.

Only a half century after their development was initiated, integrated circuits have becomeubiquitous. Computers, cellular phones, and other digital appliances are now inextricable parts ofthe structure of modern societies. That is, modern computing, communications, manufacturing

and transport systems, including the Internet, all depend on the existence of integrated circuits.

VLSI (Very Large Scale Integration)

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Very-large-scale integration (VLSI) is the process of creating integrated circuits by combiningthousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complexsemiconductor and communication technologies were being developed. The microprocessor is aVLSI device. The term is no longer as common as it once was, as chips

have increased in complexity into billions of transistors

Uses photolithography to fabricate transistors, wires, on silicon wafers.Common technologies used used in VLSI are CMOS, Bipolar, Bi Cmos, etc.

Challenges faced by VLSI

As microprocessors become more complex due to technology scaling, microprocessor designershave encountered several challenges which force them to think beyond the design plane, andlook ahead to post-silicon:

Power usage/Heat dissipation As threshold voltages have ceased to scale with advancingprocess technology, dynamic power dissipation has not scaled proportionally. Maintaining logiccomplexity when scaling the design down only means that the power dissipation per area will goup. This has given rise to techniques such as dynamic voltage and frequency scaling (DVFS) tominimize overall power.

Stricter design rules Due to lithography and etch issues with scaling, design rules for layouthave become increasingly stringent. Designers must keep ever more of these rules in mind whilelaying out custom circuits. The overhead for custom design is now reaching a tipping point, withmany design houses opting to switch to electronic design automation (EDA) tools to automatetheir design process.

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2. ORGANIZATION AND REQUIREMENT2.1 VLSI Design Flow

Basic VLSI design flow is shown in the above figure.

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This design is usually used by the VLSI designers who uses HDLs (Hardware DescriptionLanguage).in any design, specifications are written first.Specifications describe abstractly the functionality, interface, and overall architecture of thedigital circuit to be designed. At this point the architects do need to think about how they willimplement this circuit. A behavioral is then created to analyze the design in terms of

functionality, performance, compliance to standards and other high level issues. Behavioraldescriptions are written with HDLs.

The behavioral description is manually converted to an RTL description in an HDL.Thedesigners have to describe the dataflow that will implement the desired digital circuit. From thispoint onward, the design process is done with the help of EDA tools.

Logic synthesis tools convert the RTL description to a gate level net list. A gate level net list is adescription of circuit in terms of gates and connections between them. Logic synthesis toolsensure that gate level net list meets timing, area and power specifications. The gate level net listis a input to the place and route tool, which creates a layout. The layout is verified and then

fabricated into the chip.

Thus, most digital design activity is concentrating manually on optimizing the RTL descriptionof the circuit.. After the RTL description is frozen, EDA tools are available to assist the user forthe further processes. Designing at RTL level has shrunk the design cycle times from years tofew months. It is also possible to do many design iterations in a short period of time.

Behavioral synthesis tools have been emerged recently. These tools can create RTL descriptionfrom a behavioral or algorithmic description of the circuit. As these tools mature, digital circuitdesign will become similar to high level computer programming. Designer will simplyimplement the HDL in algorithm in an HDL at a very abstract level. EDA tools will help the

designers convert the behavioral descriptions to the final IC chip.

It is note that although EDA tools are available to automate the processes and cut design cycletimes, the designer is still the person who controls how the tool will work. EDA tools aresusceptible to the GIGO: garbage in garbage out phenomenon. If used improperly the EDA toolswill lead to inefficient designs. Thus, the designers still needs to understand the nuances ofdesign methodologies, using EDA tool to obtain optimize design.

2.2 HDL(Hardware Description Language)

In electronics, a hardware description language or HDL is any language from a class of computer

languages and/or programming languages for formal description of electronic circuits, and morespecifically, digital logic. It can describe the circuit's operation, its design and organization, andtests to verify its operation by means of simulation.

HDLs are standard text-based expressions of the spatial and temporal structure and behavior ofelectronic systems. Like concurrent programming languages, HDL syntax and semantics includesexplicit notations for expressing concurrency. However, in contrast to most softwareprogramming languages, HDLs also include an explicit notion of time, which is a primary

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attribute of hardware. Languages whose only characteristic is to express circuit connectivitybetween a hierarchy of blocks are properly classified as net list languages used on electriccomputer-aided design (CAD).

HDLs are used to write executable specifications of some piece of hardware. A simulation

program, designed to implement the underlying semantics of the language statements, coupledwith simulating the progress of time, provides the hardware designer with the ability to model apiece of hardware before it is created physically. It is this executability that gives HDLs theillusion of being programming languages. Simulators capable of supporting discrete-event(digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available.

It is certainly possible to represent hardware semantics using traditional programming languagessuch as C++, although to function such programs must be augmented with extensive andunwieldy class libraries. Primarily, however, software programming languages do not includeany capability for explicitly expressing time and this is why they do not function as a hardwaredescription language. Before the recent introduction of SystemVerilog, C++ integration with a

logic simulator was one of the few ways to use OOP in hardware verification. SystemVerilog isthe first major HDL to offer object orientation and garbage collection.

2.2.1 Design using HDLs

Efficiency gains realized using HDL means a majority of modern digital circuit design revolvesaround it. Most designs begin as a set of requirements or a high-level architectural diagram.Control and decision structures are often prototyped in flowchart applications, or entered in astate-diagram editor.The process of writing the HDL description is highly dependent on the nature of the circuit andthe designer's preference for coding style . The HDL is merely the 'capture language'often

begin with a high-level algorithmic description such as MATLAB or a C++ mathematical model.Designers often use scripting languages (such as Perl) to automatically generate repetitive circuitstructures in the HDL language. Special text editors offer features for automatic indentation,syntax-dependent coloration, and macro-based expansion of entity/architecture/signal declarationThe HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDLdescription is subject to an array of automated checkers.

The checkers report deviations from standardized code guidelines, identify potential ambiguouscode constructs before they can cause misinterpretation, and check for common logical codingerrors, such as dangling ports or shorted outputs. This process aids in resolving errors before thecode is synthesized.

In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis toolhas mapped the HDL description into a gate net list, this net list is passed off to the back-endstage. Depending on the physical technology (FPGA, ASIC gate array, ASIC standard cell),HDLs may or may not play a significant role in the back-end flow.In general, as the design flow progresses toward a physically realizable form, the design databasebecomes progressively more laden with technology-specific information, which cannot be storedin a generic HDL description.

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2.2.2 Simulating and Debugging HDL code

Essential to HDL design is the ability to simulate HDL programs. Simulation allows a HDLdescription of a design (called a model) to pass design verification, an important milestone thatvalidates the design's intended function (specification) against the code implementation in the

HDL description. It also permits architectural exploration. The engineer can experiment withdesign choices by writing multiple variations of a base design, then comparing their behavior insimulation. Thus, simulation is critical for successful HDL design.

To simulate an HDL model, an engineer writes a top-level simulation environment (called atestbench). At minimum, a testbench contains an instantiation of the model (called the deviceunder test or DUT), pin/signal declarations for the model's I/O, and a clock waveform. Thetestbench code is event driven: the engineer writes HDL statements to implement the (testbench-generated) reset-signal, to model interface transactions (such as a hostbus read/write), and tomonitor the DUT's output. An HDL simulator the program that executes the testbench maintains the simulator clock, which is the master reference for all events in the testbench

simulation. Events occur only at the instants dictated by the testbench HDL (such as a reset-toggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events.Modern HDL simulators have a full-featured graphical user interfaces, complete with a suite ofdebug tools. These allow the user to stop and restart the simulation at any time, insert simulatorbreakpoints (independent of the HDL code), and monitor or modify any element in the HDLmodel hierarchy. Modern simulators can also link the HDL environment to user-compiledlibraries, through a defined PLI/VHPI interface. Linking is system-dependent(Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled and link

Design verification is often the most time-consuming portion of the design process, due to thedisconnect between a device's functional specification, the designer's interpretation of the

specification, and the imprecision of the HDL language. The majority of the initial test/debugcycle is conducted in the HDLsimulatorenvironment, as the early stage of the design is subjectto frequent and major circuit changes. An HDL description can also be prototyped and tested inhardware programmable logic devices are often used for this purpose. Hardware prototypingis comparatively more expensive than HDL simulation, but offers a real-world view of thedesign. Prototyping is the best way to check interfacing against other hardware devices andhardware prototypes.

2.2.3 Design verifications with HDLs

Design verification was a laborious, repetitive loop of writing and running simulation test cases

against the design under test. As chip designs have grown larger and more complex, the task ofdesign verification has grown to the point where it now dominates the schedule of a design team.Looking for ways to improve design productivity, the EDA industry developed the PropertySpecification Language.

In formal verification terms, a property is a factual statement about the expected or assumedbehavior of another object. Ideally, for a given HDL description, a property or properties can beproven true or false using formal mathematical methods. In practical terms, many properties

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cannot be proven because they occupy an unbounded solution space. However, if provided a setof operating assumptions or constraints, a property checker can prove (or disprove) moreproperties, over the narrowed solution space.

The assertions do not model circuit activity, but capture and document the "designer's intent" in

the HDL code. In a simulation environment, the simulator evaluates all specified assertions,reporting the location and severity of any violations. In a synthesis environment, the synthesistool usually operates with the policy of halting synthesis upon any violation. Assertion-basedverification is still in its infancy, but is expected to become an integral part of the HDL designtoolset.

2.3 HDL and programming languages

A HDL is analogous to a software programming language, but with major differences. Manyprogramming languages are inherently procedural (single-threaded), with limited syntactical andsemantic support to handle concurrency. HDLs, on the other hand, resemble concurrent

programming languages in their ability to model multiple parallel processes (such as flipflops,adders, etc.) that automatically execute independently of one another. Any change to theprocess's input automatically triggers an update in the simulator's process stack. Bothprogramming languages and HDLs are processed by a compiler (usually called a synthesizer inthe HDL case), but with different goals. For HDLs, 'compiler' refers to synthesis, a process oftransforming the HDL code listing into a physically realizable gate netlist. The netlist output cantake any of many forms: a "simulation" netlist with gate-delay information, a "handoff" netlistfor post-synthesis place and route, or a generic industry-standard EDIF format (for subsequentconversion to a JEDEC-format file).

On the other hand, a software compiler converts the source-code listing into a microprocessor-

specific object-code, for execution on the target microprocessor. As HDLs and programminglanguages borrow concepts and features from each other, the boundary between them isbecoming less distinct. However, pure HDLs are unsuitable for general purpose softwareapplication development, just as general-purpose programming languages are undesirable formodeling hardware. Yet as electronic systems grow increasingly complex, and reconfigurablesystems become increasingly mainstream, there is growing desire in the industry for a singlelanguage that can perform some tasks of both hardware design and software programming.SystemC is an example of suchembedded system hardware can be modeled as non-detailedarchitectural blocks (blackboxes with modeled signal inputs and output drivers). The targetapplication is written in C/C++, and natively compiled for the host-development system (asopposed to targeting the embedded CPU, which requires host-simulation of the embedded CPU).

The high level of abstraction of SystemC models is well suited to early architecture exploration,as architectural modifications can be easily evaluated with little concern for signal-levelimplementation issues.

In an attempt to reduce the complexity of designing in HDLs, which have been compared to theequivalent of assembly languages, there are moves to raise the abstraction level of the design.

2.4 Importance of HDLs

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A Hardware Description Language (HDL) is a software programming language used to modelthe intended operation of a piece of hardware

EDA tools are computer based software systems to design Very Large Scale Integrated circuits.

Now EDA tools are available for almost every stage of VLSI design flow. But to start with wemust convey design idea (that is in our mind) to EDA tool in such a way that the tool is able tounderstand that and generate a highly optimized design implementation.

This transfer of idea from human beings to machines is called Design Entry. There are twomethods of design entry: graphical and textual. Graphical method includes schematic entry andstate diagram entry while textual method implies use of HDL's (Hardware DescriptionLanguages). Graphical method works fairly well up to a certain level of circuit complexity but inlarger circuits they become cumbersome and time consuming.

2.5 Advantages of HDL

Compact description.

Easy to edit.

Highly portable.

Supports a higher level of abstraction.

Rapid prototyping of design.

Availability of extensive vendor libraries.

Increasing capability of synthesis tools.

2.6 Disadvantages of HDL

No support for analog behavior.

Need to learn coding styles that ensures synthesizable results.

Support for hardware concurrency and time frame are two main features thatdistinguishes HDLs from other programming language.

3. EXECUTION OF WORK

3.1 VERILOG(Verify Logic)

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In the semiconductor and electronic design industry, Verilog is a hardware description language(HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL, is mostcommonly used in the design, verification, and implementation of digital logic chips at theregister transfer level (RTL) of abstraction. It is also used in the verification of analog andmixed-signal circuits.

3.1.1 History of verilog

Beginning

Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 atAutomated Integrated Design Systems (renamed to Gateway Design Automation in 1985) as ahardware modeling language. Gateway Design Automation was purchased by Cadence DesignSystems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.

Verilog-95

With the increasing success of VHDL at the time, Cadence decided to make the languageavailable for open standardization. Cadence transferred Verilog into the public domain under theOpen Verilog International (OVI) (now known as Accellera) organization. Verilog was latersubmitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

In the same time frame Cadence initiated the creation of Verilog-A to put standards supportbehind its analog simulator Spectre. Verilog-A was never intended to be a standalone languageand is a subset of Verilog-AMS which encompassed Verilog-95.

Verilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users hadfound in the original Verilog standard. These extensions became IEEE Standard 1364-2001known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2'scomplement) signed nets and variables. Previously, code authors had to perform signed-operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the boolean-algebra to determine its correct value).

The same function under Verilog-2001 can be more succinctly described by one of the built-inoperators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL'sgenerate/endgenerate) allows Verilog-2001 to control instance and statement instantiationthrough normal decision-operators (case/if/else). Using generate/endgenerate, Verilog-2001 caninstantiate an array of instances, with control over the connectivity of the individual instances.File I/O has been improved by several new system-tasks. And finally, a few syntax additionswere introduced to improve code-readability (eg. always @*, named-parameter override, C-stylefunction/task/module header declaration).

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Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDAsoftware packages.

Verilog 2005

Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists ofminor corrections, spec clarifications, and a few new language features (such as the uwirekeyword).

A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixedsignal modelling with traditional Verilog.

SystemVerilog

SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aiddesign-verification and design-modeling.

3.1.2 Design methodology

TOP

MODULE

SUB

MODULE1

SUB

MODULE3

SUB

MODULE2

Sub

Module5Sub

Module 4cellcellcell cellcell

cellcell cellcellcell

3.1.3 General syntax for writing VERILOG program

module Module_Name (Port_List) ;

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...

...

...

...

Endmodule

Syntax :

module Module_Name(Port_List) ;endmodule

The port list in module definitions contains names of ports (terminals) only and wemust specify whether they are input, output or bi-directional terminals. So port declarations arethe first thing we write in module internals. Ports are declared using Verilog keywords input,output and inout. Keyword inout is used for bi-directional ports.

All internal signals between various hardware units must be assigned some nameand declared its type. So second thing we write in module internals is internal signal declaration.

Then follows the actual module functionality.

3.1.4 What is MODULE in verilog

Module is a basic functional unit in Verilog. A module can be seen as a design blockwith some inputs and outputs. How that block works is written inside that module. All thedistinct blocks in design tree corresponds to a module in Verilog. So module is just like black

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box with input and output terminals and that black box interacts with the outside environmentthrough these terminals only. The relationship between these input and output terminals is hiddenfrom the environment.

Every module definition begins with a keyword module and ends with keywordendmodule. Only within these two keywords functionality of a module is specified. Each modulehas a module name and port list. Module name is an identifier for that particular module and portlist contains the list of all input and output terminals for the module.

To build a full adder from the half adder defined just now we have to create an instanceof halfadder module in fulladder module. This instance is given a name and ports are connectedappropriately. Certain predefined modules of basic hardware elements are provided in Verilogand we call them as primitives. These primitives can be instantiated inside modules in same waybut giving them names is optional. So a module may contain instances of primitives and othermodules.

3.1.5 First verilog program

Program of the half adder using verilog:

module half_adder(sum, carry, in1, in2) ;output sum, carry ;input in1, in2 ;xor (sum, in1, in2) ;and (carry, in1, in2) ;endmodule

Program of the half adder using verilog:

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carry


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HALF

ADDER

HALF

ADDER

a

b

carry_in

carry_out

sum

module full_adder(sum, carry_out, a, b, carry_in) ;output sum, carry_out ;input a, b, carry_in ;wire w1, w2, w3;half_adder ha1(w1, w2, a, b);half_adder ha2(sum, w3, w1, carry_in);or (carry_out, w2, w3);

endmodule

3.1.6 Language elements

White space

Blank spaces - \bTabs- \t

New lines- \nWhite spaces have no syntactical significance and can be inserted for betterreadability.Whitespace is not ignored in strings.

Comments

// The rest of the line is a comment.

/* Multiple linecomments *//* Nesting /* comments */ is NOT allowed */

Comments make life easier for you and others also. So insert a lot of meaningful comments inyour code

Operators

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Operators are of three types:

Unary,binary and ternary.

a=~b;a= b && c;

A=b ? c:d ;

Signal Values

0 Logic Zero1 Logic Onex or X Unknownz or Z High Impedance

Representation of Number

Decimal d or DHex h or HOctal o or OBinary b or B

Syntax '

size specifies number of bits to be occupied by number and is written only in decimal.radix determines the arithmetic base of number.number is the value expressed in the indicated base only.

Number #Bits Base Storage2'b10 2 Binary 103'd6 3 Decimal 1106'o57 6 Octal 1011113'O4 3 Octal 1008'H2d 8 Hex 00101101

32'haA19 32 Hex 10101010000110015'B110x0 5 Binary 110x06'ozz 6 Octal zzzzzz12'hZXb 12 Hex zzzzxxxx1011

Number Format

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If we do not specify the size it takes default value which is machineand simulation dependent but is at least 32 bits.Also if we do not specify radix default is decimal base.

Number #Bits Base Storage

'bz >= 32 Binary zz..zzz'h9 >= 32 Hex 0000..10013 >= 32 Decimal 000...011

If the size is greater than the value of number, the number in themost significant bit is extended for MSB = 0, x or zzero extended if MSB = 1.

Number #Bits Base Storage8'bx001 8 Binary xxxxx0015'o1 5 Octal 0000115'hzf 15 Hex zzzzzzzzzzz11119'd5 9 Decimal 000000101

For negative numbers we place a minus sign before the number representation.Negative numbers are stored as 2's complement.Number #Bits Base Storage

-6'd3 6 Decimal 111101-3'b11 3 Binary 101

Underscores can be inserted in numbers to enhance readability and are ignored byVerilog.12'b00011101010012'b000_111_010_100

Identifiers are names given to different objects so that they can be referenced indesign. An identifier is any sequence of letters [A-Z] and [a-z], digits [0-9], underscore [ _ ] and

$ character. Cannot begin with $ or digits and are case sensitive. An identifier may contain up to1024 characters.

myid - validm_y_id - valid3my_id - invalid$myid - invalid_myid4 - valid

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Keywords

Keywords are special words reserved by language, their meaning is

Predefined and cannot be used as identifiers. All keywords are in lowercase.

always for pmos supply1and force posedge tableassign forever primitive task begin fork pull0 timebuf function pull1 tranbufif0 highz0 pulldown tranif0bufif1 highz1 pullup tranif1

case if rcmos tricasex initial real tri0casez inout realtime tri1cmos input reg trianddeassign integer release trior default join repeat triregdefparam large rnmos vectoreddisable rpmos wait wireedge medium rtran xor else module rtranif0end nand rtranif1

endcase negedge scalaredendfunction nmos smallendmodule nor specifyendprimitive not xnor endspecify notif0 strengthendtable notif1 strong0endtask output strong1event parameter supply0

Data types

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Verilog contains predefined datatypes:

Nets Registers

(connectivity) (storage)

wire reg

tri integer

wand real

wor time

triand realtime

trior

supply0+

supply1

tri0

tri1

trireg

NetsNets represent the interconnection between hardware elements. Value of a net variable is

determined throughout the simulation by output of the components they are connected to (calledDrivers). If no driver is connected to a net, the net defaults to a value of Z. Most commonly usedtype of net is wire.

module my_ckt (f, a, b, c, d, e);

output f ;

input a, b, c, d, e ;

wire n1;

wire m1, x0, x1 ;

endmodule

In above circuit n1, m1, x0, x1 are nets. They are declared inside module bykeyword wire.

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Some other type of nets will be discussed later in advance Verilog concepts. Any undeclared netsdefault to type wire.

a

b

c

d

e

n1

m1

x0

x1

f

Registers

Register Type Usage

reg Stores a logic value

integer Supports computation

time Stores time as a 64-bit unsigned quantity

real Stores values (e.g. delays) as real numbers

realtime Stores time values as real numbers

Registers are variables that store values. It is an abstraction of a hardware storage element, but itneed not correspond directly to physical storage elements in a circuit. Registers retain value untilanother value is placed onto them.Unlike a net, a register does not need a driver. A register objectmay be assigned value within a procedural statement, a user sequential primitive,task, orfunction.

REG

The reg kind of register data type is the one most commonly used. A reg data type models thefeature of hardware that allows a logic value to be stored in a flip-flop or a latch. A reg objectmay never be the output of primitive gate or the target of a continuous assignment. The defaultvalue for a reg data type is X.

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INTEGER

The integer data type supports numeric computation in procedural code. Integers are representedinternally to the word length of the host machine (at least 32 bits). A negative number is stored in2s complement format. Registers declared as data types reg store values as unsigned

quantities,whereas integers store values as signed quantities.

REAL

Accurate modeling of delay values might require the use of real data types. Real objects arestored in double precision, typically a 64-bit value. Real values can be specified in decimal andexponential notation. An object of type real may not be connected to a port or terminal of aprimitive.Real numbers cannot have a range declaration and their default value is 0.

TIME

The data type time supports time-related computations within procedural code in Verilog

models. Time variables are stored as unsigned 64-bit quantities. A variable of type time may notbe used in a module port; nor may it be an input or output of a primitive. Data type realtimestores time values in real number format. The system function $time is invoked to get the currentsimulation time.

Constants

A constant in Verilog is declared with the keyword parameter, which declares andassigns values to the constant. The value of a constant may not be changed during simulation butparameters (or constants) can be changed at module instantiation or by using the defparam

statement.

parameter high_index = 22 ;

parameter av_delay = (min_delay + max_delay) / 2 ;

parameter initial_state = 8b1011_1000 ;

3.2 Different types of modeling used in verilog

Gate level modeling

Data flow modeling

Behavioral modeling

Switch level modelling

3.2.1. Gate level modeling

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Primitives

Verilog provides a robust set of built-in gate primitives. Primitives are like predefined modules. Alogic circuit is described on gate to gate basis using these primitives. Primitives can be instantiated

only within modules and use of identifier name with primitive instantiation is optional. The port listof a primitive have output(or outputs) written first, followed by inputs.

AND

if any of the input is 0, output is 0

else if any of input is x or z , output is x

else if all inputs are 1, output is 1

NAND




OR




NOR




XOR

if any of the input is x or z, output is x

else if odd number of inputs are 1, output is 1

else output is 0

XNOR

if any of the input is x or z, output is x

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else if even number of inputs are 1, output is 1

else output is 0

BUF

if input is 1, output is 1

else if input is 0, output is 0

else if input is x or z, output is x

NOT

if input is 1, output is 0

else if input is 0, output is 1

else if input is x or z, output is x

We can instantiate multiple primitives of same type by a single statement usingcomma-separated lists e.g.

nand G1(y1, a1, a2, a3), (y2, b1, b2, b3), M2(d3, e1, e2);

Verilog gate level description of a and-or-invert logic gate

module AOI(out, in1, in2, in3, in4) ;

output out ;

input in1, in2, in3, in4 ;

wire y1, y2 ;

and (y1, in1, in2) ;

and a1(y2, in3, in4) ;

nor (out, y1, y2);

endmodule

in1

in2

in3

in4

y1

y2

out

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3.2.2. Data flow modeling

Data flow modeling describes the design in terms of expressions instead of primitivegates. A continuous assignment statement is the most basic statement in the dataflow modeling. It

is used to assign a value to a net. It starts with the keyword assign followed by actual assignmente.g.

assign A = x | (Y & ~Z) ;

assign B[3:0] = 4b10xx ;

assign C[15:0] = F[15:0] ^ E[15:0] ;

Left hand side of the assignment must be nets(scalar or vector), but right hand sideexpression can have registers, nets or function calls as operands.

The continuous assignment statement are continuously active and they all execute inparallel. Whenever value of any operand on right side changes expression is reevaluated and newvalue is assigned to the corresponding net.

Continuous assignments can be made implicitly by associating the right hand sideexpression with the declaration of target net e.g.

Instead of

wire cout ;

assign cout = cin1 + cin2 ;

we can write

wire cout = cin1 + cin2

Multiple assignments can be made with one assign keyword using comma-separatedlists e.g.

assign y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a3 ;

assign data = s[3:0] + r[5:2], m = a & g ;

Verilog dataflow style description of a 1-bit full adder

module f_add_1bit ( sum, cout, a, b, cin) ;

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output sum, cout ;

input a, b, cin ;

assign sum = a ^ b ^ cin ;

assign cout = (a & cin) | (b & cin) | (a & b) ;

endmodule

Verilog has a robust set of built-in operators that manipulate the various types of dataimplemented in the language to produce values on nets and registers. Some of the operators areused within expressions on right-hand side of continuous assignment statements and procedural

statements; others are used in Boolean expressions in conditional statements or with conditionaloperators.

3.2.2.1 Operators

Functional Group Operator Name

Logical

&& Logical and

|| Logical or

! Logical not

Bitwise

& Bitwise and

| Bitwise or

~ Bitwise not

^ Bitwise xor

~^ or ~ Bitwise xnor

Reduction

& Reduction and

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~& Reduction nand

| Reduction or

~| Reduction nor

^ Reduction xor

~^ or ~ Reduction xnor

Shift

>> Right Shift

Greater than

< Less than

>= Greater than or equal to


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Arithmetic

+ Add

- Subtract

* Multiply

/ Divide

% Modulus

Logical Operators

&& - logical AND

|| - logical OR

! - logical NOT

Logical operators evaluates to one bit value 0, 1, or x. These operators gives resulton the basis of logical values of operands I.e.

If operand has zero value, it is taken as logical false (0)

If operand has non-zero value, it is taken as logical true (1)

If a bit in any of the operand is x or z, whole operand is treated as x

A = 6 A && B 1 && 0 0

B = 0 A || (!B) 1 || 1 1

C = x C || B x || 0 x

C && B x && 0 0

Reduction Operators

& Reduction AND

| Reduction OR

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^ Reduction XOR

~& Reduction NAND

~| Reduction NOR

~^ or ^~ Reduction XNOR

Reduction operators are unary operators i.e. they act on single operands. Theycreate a single-bit result by operating on a multibit operand.

&(010101) 0 & 1 & 0 & 1 & 0 & 1 0

a = 4b1001

b = ^a b = 1 ^ 0 ^ 0 ^ 1 b = 1

|(010x10) 0 | 1 | 0 | x | 1 | 0 1

Bitwise Operators

& - bitwise AND

| - bitwise OR

~ - bitwise NOT

^ - bitwise XOR

~^ - bitwise XNOR

Bitwise operators acts on individual bits of the operands. The operands may bescalar or vector. If one of the operand is shorter than the other, it will be zero extended to matchthe length of the longer operand. The bitwise not operator negates the individual bits of anoperand.

a = 4b1010

b = 4b1100

c = ~a c = ~(1010) c = 0101

d = a & b d = 1010 & 1100 d = 1000

e = (101011) b e = 101011 ^ 1100 e = 101011 001100 e = 100111

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Shift Operators

>> shift right

> 2 d = 0010

c = a greater than

< less than

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The Verilog relational operators compare operands and produce a Boolean 0 or 1 (trueor false) result. If any bit in one of the operands is unknown (x), the result is unknown.

1 > 0 1

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must be enclosed withinSequential begin - endblockParallel fork-joinblockWhen using begin-end, we can give name to that group. This is calledNamed blocks.

Sequential statement

The begin - end keywords:Group several statements together.Cause the statements to be evaluated in sequentially (one at atime).

Any timing within the sequential groups is relative to theprevious statement.

Delays in the sequence accumulate (each delay is added tothe previous delay)

Block finishes after the last statement in the block.

Conditional statement:

The if - else statement controls the execution of other statements, Inprogramming language like c, if - else controls the flow of program.if(condition)statements;if(condition)statements;else

statements;if(condition)statements;else if(condition)statements;................

................else

statements;

Case statement:

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The case statement compares a expression to a series of cases andexecutes the statement or statement group associated with the firstmatching case? case statement supports single or multiple statements.? Group multiple statements using begin and end keywords.

case () : : .....default : endcase

Looping statement:

Looping statements appear inside a procedural blocks only, Verilog has

four looping statements like any other programming language.

forever

repeat

while

for

Continuous assignment statements:

Continuous assignment statements drives nets (wire data type). Theyrepresent structural connections.

They are used for modeling Tri-State buffers.

They can be used for modeling combinational logic.

They are outside the procedural blocks (always and initial blocks).

The continuous assign overrides and procedural assignments.

The left-hand side of a continuous assignment must be net datatype.

syntax : assign(strength, strength) # delay net = expression;

Modeling the flip flops with always statement

Very basic: an edge-sensitive flip-flop

reg q;always @(posedge clk)q = d;

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q = d assignment runs when clock rises: exactly theBehavior you expect

Modeling FSM(Finite State Machine) behaviorally

There are many ways to do it:

-Define the next-state logic combinationally and definethe state-holding latches explicitly-Define the behavior in a single always @(posedgeclk) block-Variations on these themes

3.2.4 Switch level modeling

We have learnt about the digital design and simulations at a higher level of abstractions such asgates, data flow, and behavior. However, in rare cases designers will choose to design the leaflevel modules, using transistors. Verilog provides the ability to design at a MOS-transistor level.Design at this level is becoming rare with the increasing complexity of circuits(millions oftransistors) and with the availabity of sophisticated CAD tools. Verilog HDL currently providesonly digital design capability with logic values 0,1,x,z and the drive strengths associated withthem. There is no analog capability. Thus is analog transistors are known as switches that eitherconduct or ar open.

3.2.4.1 Cmos(complimentary metal oxide semiconducator)

Complementary metaloxidesemiconductor (CMOS) is a technology for constructingintegrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM,and other digital logic circuits. CMOS technology is also used for several analog circuits such asimage sensors, data converters, and highly integrated transceivers for many types ofcommunication. Frank Wanlass successfully patented CMOS in 1967 (US patent 3,356,858.

CMOS is also sometimes referred to as complementary-symmetry metaloxidesemiconductor(or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digitaldesign style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal

oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static powerconsumption. Significant power is only drawn while the transistors in the CMOS device areswitching between on and off states. Consequently, CMOS devices do not produce as muchwaste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic,which uses all n-channel devices without p-channel devices. CMOS also allows a high density of

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logic functions on a chip. It was primarily this reason why CMOS won the race in the eightiesand became the most used technology to be implemented in VLSI chips

3.2.4.2 CMOS inverter

An inverter (also referred to as NOT gate) is a logic gate with an output that isthe complement of its input. Transistor level structure of this gate, its logicsymbol, its algebraic notations, and its truth table are shown in Figure 2.2.In the transistor structure shown in this figure, ifa is 0, the uppertransistor conducts and wbecomes 1. Ifa is 1, there will be a conduction pathfrom w to Gnd which makes it 0. The table shown in Figure 2.2 is called thetruth table of the inverter and lists all possible input values and theircorresponding outputs. The inverter symbol is a bubble that can be placed oneither side of a triangle representing a buffer.

CMOS Inverter (NOT gate)

3.3 FPGA(Field Programmable Gate Array)

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured bya customer or a designer after manufacturinghence "field-programmable". The FPGAconfiguration is generally specified using a hardware description language (HDL), similar tothat used for an application-specific integrated circuit (ASIC) (circuit diagrams werepreviously used to specify the configuration, as they were for ASICs, but this is increasinglyrare). FPGAs can be used to implement any logical function that an ASIC could perform. Theability to update the functionality after shipping, partial re-configuration of a portion of thedesign and the low non-recurring engineering costs relative to an ASIC design(notwithstanding the generally higher unit cost), offer advantages for manyapplications.FPGAs contain programmable logic components called "logic blocks", and ahierarchy of reconfigurable interconnects that allow the blocks to be "wired together"somewhat like many (changeable) logic gates that can be inter-wired in (many) differentconfigurations. Logic blocks can be configured to perform complex combinational functions,or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks alsoinclude memory elements, which may be simple flip-flops or more complete blocks ofmemory.In addition to digital functions, some FPGAs have analog features. The mostcommon analog feature is programmable slew rate and drive strength on each output pin,allowing the engineer to set slow rates on lightly loaded pins that would

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otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow.Another relatively common analog featureis differential comparators on input pins designed to be connected to differentialsignaling channels. A few "mixed signalFPGAs" have integrated peripheral analog-to-digitalconverters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning

blocks allowing them to operate as a system-on-a-chip.[5]

Such devices blur the line betweenan FPGA, which carries digital ones and zeros on its internal programmable interconnectfabric, and field-programmable analog array (FPAA), which carries analog values on itsinternal programmable interconnect fabric.

3.3.1 FPGA ComparisonsHistorically, FPGAs have been slower, less energy efficient and generally achieved lessfunctionality than their fixed ASIC counterparts. A study has shown that designs implementedon FPGAs need on average 40 times as much area, draw 12 times as much dynamic power,and are three times slower than the corresponding ASIC implementations.Advantages include the ability to re-program in the field to fix bugs, and may include a

shorter time to market and lower non-recurring engineering costs. Vendors can also take amiddle road by developing their hardware on ordinary FPGAs, but manufacture their finalversion so it can no longer be modified after the design has been committed. Xilinx claimsthat several market and technology dynamics are changing the ASIC/FPGA paradigm:

Integrated circuit costs are rising aggressively.

ASIC complexity has lengthened development time.

R&D resources and headcount are decreasing.

Revenue losses for slow time-to-market are increasing.

Financial constraints in a poor economy are driving low-cost technologies.These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company

attributes the growing number of FPGA design starts. Some FPGAs have the capabilityof partial re-configuration that lets one portion of the device be re-programmed while otherportions continue running.

3.3.2 FPGA ArchitectureThe most common FPGA architecture consists of an array of logic blocks (calledConfigurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/Opads, and routing channels. Generally, all the routing channels have the same width (numberof wires). Multiple I/O pads may fit into the height of one row or the width of one column inthe array.

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An application circuit must be mapped into an FPGA with adequate resources. While thenumber of CLBs/LABs and I/Os required is easily determined from the design, the number ofrouting tracks needed may vary considerably even among designs with the same amount oflogic. For example, a crossbar switch requires much more routing than a systolic array withthe same gate count. Since unused routing tracks increase the cost (and decrease the

performance) of the part without providing any benefit, FPGA manufacturers try to providejust enough tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOscan be routed. This is determined by estimates such as those derived from Rent's rule or byexperiments with existing designs.In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Sliceetc.). A typical cell consists of a 4-input LUT, a Full adder (FA) and a D-type flip-flop, asshown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode thoseare combined into a 4-input LUT through the left mux. In arithmetic mode, their outputs arefed to the FA. The selection of mode is programmed into the middle multiplexer. The outputcan be either synchronous or asynchronous, depending on the programming of the mux to theright, in the figure example. In practice, entire or parts of the FA are put as functions into the

LUTs in order to save space.

Simplified example illustration of a logic cell.

ALMs and Slices usually contains 2 or 4 structures similar to the example figure, with

some shared signals.CLBs/LABs typically contains a few ALMs/LEs/Slices.In recent

years, manufacturers have started moving to 6-input LUTs in their high performance parts,

claiming increased performance.

Since clock signals (and often other high-fanout signals) are normally routed via special-

purpose dedicated routing networks in commercial FPGAs, they and other signals are

separately managed.

For this example architecture, the locations of the FPGA logic block pins are shown below.

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Logic Block Pin Locations

Each input is accessible from one side of the logic block, while the output pin can connect

to routing wires in both the channel to the right and the channel below the logic block.

Each logic block output pin can connect to any of the wiring segments in the channels

adjacent to it.

Similarly, an I/O pad can connect to any one of the wiring segments in the channel

adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W

wires (where W is the channel width) in the horizontal channel immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one

logic block before it terminates in a switch box. By turning on some of the programmable

switches within a switch box, longer paths can be constructed. For higher speed

interconnect, some FPGA architectures use longer routing lines that span multiple logic

blocks.

Whenever a vertical and a horizontal channel intersect, there is a switch box. In this

architecture, when a wire enters a switch box, there are three programmable switches that

allow it to connect to three other wires in adjacent channel segments. The pattern, or

topology, of switches used in this architecture is the planar or domain-based switch box

topology. In this switch box topology, a wire in track number one connects only to wires in

track number one in adjacent channel segments, wires in track number 2 connect only to

other wires in track number 2 and so on. The figure below illustrates the connections in a

switch box.

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Switch box topologyModern FPGA families expand upon the above capabilities to include higher level

functionality fixed into the silicon. Having these common functions embedded into the

silicon reduces the area required and gives those functions increased speed compared to

building them from primitives. Examples of these include multipliers, generic DSP blocks,

embedded processors, high speed IO logic and embedded memories.

FPGAs are also widely used for systems validation including pre-silicon validation, post-

silicon validation, and firmware development. This allows chip companies to validate their

design before the chip is produced in the factory, reducing the time-to-market.

To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx

have introduced new 3D or stacked architectures. Following the introduction of its 28 nm7-series FPGAs, Xilinx revealed that several of the highest-density parts in those FPGA

product lines will be constructed using multiple dice in one package, employing

technology developed for 3D construction and stacked-die assemblies. The technology

stacks several (three or four) active FPGA dice side-by-side on a silicon interposer a

single piece of silicon that carries passive interconnect.

3.3.3 FPGA Design and Programming

To define the behavior of the FPGA, the user provides a hardware description

language (HDL) or a schematic design. The HDL form is more suited to work with largestructures because it's possible to just specify them numerically rather than having to draw

every piece by hand. However, schematic entry can allow for easier visualisation of a

design.Then, using an electronic design automation tool, a technology-mapped netlist is

generated. The netlist can then be fitted to the actual FPGA architecture using a process

called place-and-route, usually performed by the FPGA company's proprietary place-and-

route software. The user will validate the map, place and route results via timing

analysis, simulation, and other verificationmethodologies. Once the design and validation

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process is complete, the binary file generated (also using the FPGA company's proprietary

software) is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via

a serial interface (JTAG) or to an external memory device like an EEPROM.The most

common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of

designing in HDLs, which have been compared to the equivalent of assembly languages,

there are moves to raise the abstraction level through the introduction of alternativelanguages. National Instrument's LabVIEW graphical programming language (sometimes

referred to as "G") has an FPGA add-in module available to target and program FPGA

hardware.To simplify the design of complex systems in FPGAs, there exist libraries of

predefined complex functions and circuits that have been tested and optimized to speed up

the design process. These predefined circuits are commonly calledIP cores, and are

available from FPGA vendors and third-party IP suppliers (rarely free, and typically

released under proprietary licenses). Other predefined circuits are available from developer

communities such as OpenCores (typically released under free and open source licenses

such as the GPL, BSD or similar license), and other sources.

In a typical design flow, an FPGA application developer will simulate the design atmultiple stages throughout the design process. Initially the RTL description

in VHDL or Verilog is simulated by creating test benches to simulate the system and

observe results. Then, after the synthesis engine has mapped the design to a netlist, the

netlist is translated to a gate level description where simulation is repeated to confirm the

synthesis proceeded without errors. Finally the design is laid out in the FPGA at which

point propagation delays can be added and the simulation run again with these values back-

annotated onto the netlist.

3.4 CPLD(Complex Programmable Logic Device)

The primary differences between CPLDs (Complex Programmable Logic Devices) and

FPGAs are architectural. A CPLD has a somewhat restrictive structure consisting of one or

more programmable sum-of-products logic arrays feeding a relatively small number of

clocked registers. The result of this is less flexibility, with the advantage of more

predictable timing delays and a higher logic-to-interconnect ratio. The FPGA architectures,

on the other hand, are dominated by interconnect. This makes them far more flexible (in

terms of the range of designs that are practical for implementation within them) but also far

more complex to design for.In practice, the distinction between FPGAs and CPLDs is often

one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically

only FPGA's contain more advanced embedded functions such as adders, multipliers,

memory, serdes and other hardened functions. Another common distinction is that CPLDs

contain embedded flash to store their configuration while FPGAs usually, but not always,

require an external flash.

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4. HARDWARE/ SOFTWARE IMPLIMENATION

4.1 EDA(Electronic Design Automation) tools

Electronic design automation (also known as EDA or ECAD) is a category of software tools fordesigning electronic systems such as printed circuit boards and integrated circuits. The tools

work together in a design flow that chip designers use to design and analyze entiresemiconductor chip.

4.1.1 History of EDA tools

1981 marks the beginning of EDA as an industry. For many years, the larger electroniccompanies, such as Hewlett Packard, Tektronix, and Intl, had pursued EDA internally. In 1981,managers and developers spun out of these companies to concentrate on EDA as a business.Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time,and collectively referred to as DMV. Within a few years there were many companies specializing

in EDA, each with a slightly different emphasis.

In 1986, Verilog, a popular high-level design language, was first introduced as a hardwaredescription language by Gateway Design Automation. In 1987, the U.S. Department of Defensefunded creation of VHDL as a specification language. Simulators quickly followed theseintroductions, permitting direct simulation of chip designs: executable specifications. In a fewmore years, back-ends were developed to perform logic synthesis.

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4.1.2 Current status

Current digital flows are extremely modular (see Integrated circuit design, Design closure, andDesign flow (EDA)). The front ends produce standardized design descriptions that compile intoinvocations of "cells,", without regard to the cell technology. Cells implement logic or other

electronic functions using a particular integrated circuit technology. Fabricators generallyprovide libraries of components for their production processes, with simulation models that fitstandard simulation tools. Analog EDA tools are far less modular, since many more functions arerequired, they interact more strongly, and the components are (in general) less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling ofsemiconductor technology.Some users are foundry operators, who operate the semiconductorfabrication facilities, or "fabs", and design-service companies who use EDA software to evaluatean incoming design for manufacturing readiness. EDA tools are also used for programmingdesign functionality into FPGAs

4.2 Software focuses on Design

High-level synthesis(syn. behavioural synthesis, algorithmic synthesis) For digital chips

Logic synthesis translation of abstract, logical language such as Verilog or VHDL into adiscrete netlist of logic-gates

Schematic Capture For standard cell digital, analog, rf like Capture CIS in Orcad byCADENCE and ISIS in Proteus

Layout like Layout in Orcad by Cadence, ARES in Proteus

4.3 Modelsim simulator

Modelsim simulator is used for the designing and simulation of circuit design.

4.3.1 Introduction:

ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, andmixedlanguage designs.This lesson provides a brief conceptual overview of the ModelSimsimulation environment.It isdivided into fourtopics, which you will learn more about insubsequent lessons.

Basic simulation flow. Project flow . Multiple library flow

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Debugging tools

Basic simulation

1. Create a working library

2. Compile design files

3. Load and Run simulation

4. Debug results

4.3.2 Creating the working library

In ModelSim, all designs are compiled into a library. You typically start a newsimulation in ModelSim by creating a working library called "work". "Work" is thelibrary name used by the compiler as the default destination for compiled design units.

Compiling Your DesignAfter creating the working library, you compile your design units into it. The ModelSimlibraryformat is compatible across all supported platforms. You can simulate yourdesign on anyplatform without having to recompile your design.

Loading the Simulator with Your Design and Running the SimulationWith the designcompiled, you load the simulator with your design by invoking thesimulator on a top-level

module (Verilog) or a configuration orentity/architecture pair(VHDL).

Assuming the design loads successfully, the simulation time is set to zero, and you entera runcommand to begin simulation.

Debugging Your ResultsIf you dont get the results you expect, you can use ModelSims robust debuggingenvironment to track down the cause of the problem.

4.3.3 Project flow

A project is a collection mechanism for an HDL design under specification or test. Even thoughyou dont have to use projects in ModelSim, they may ease interaction with the tool and areuseful for organizing files and specifying simulation settings.

The following flow shows the basic steps for simulating a design within a ModelSimproject.

Create a project

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Add files to the project

Compile design files

Run simulations

Debug results

As you can see, the flow is similar to the basic simulation flow. However, there are twoimportantdifferences: You do not have to create a working library in the project flow; it is done for youautomatically. Projects are persistent. In other words, they will open every time you invoke ModelSim unlessyou specifically close them.

4.3.4 Multiple library flow

ModelSim uses libraries in two ways: 1) as a local working library that contains the compiled

version of your design; 2) as a resource library. The contents of your working library willchange as you update your design and recompile. A resource library is typically static andserves as a parts source for your design. You can create your own resource libraries, or theymay be supplied by another design team or a third party (e.g., a silicon vendor).You specify which resource libraries will be used when the design is compiled, and there arerules to specify in which order they are searched. A common example of using both a workinglibrary and a resource library is one where your gate-level design and testbench are compiledinto the working library, and the design references gate-level models in a separate resourcelibrary.

The flow below shows the basic steps for simulating with multiple libraries.

1. Create the working library2. Compile the design files3. Link to resources library4. Run simulations5. Debug results

You can also link to resource libraries from within a project. If you are using a project, youwould replace the first step above with these two steps: create the project and add the testbench

to the project.

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5. SIMULATIVE/ HARWARE ANALYSIS

5.1 UART

Universal Asynchronous Receiver and Transmitter.A serial communication protocol that sends parallel data through a serial line.Typically used with RS-232 standard.Your FPGA boards have an RS-232 port with a standard 9-pin connector.

The voltages of the FPGA and serial port are different, and therefore a levelconvertercircuit is also present on the board.The board handles the RS-232 standard and therefore our focus is on the UART.The UART includes both a transmitter and receiver.The transmitter is a special shift register that loads data in parallel and thenshifts it out bit-by-bit.The receiver shifts in data bit-by-bit and reassembles the data byte.The data line is 1 when idle.

5.2 UART Specifications

Transmission starts when a start bit (a 0) is sent, followed by a number of data bits(either 6, 7 or 8), an optional partity bit and stop bits (with 1, 1.5 or 2 1s).This is the transmission of 8 data bits and 1 stop bit.Note that no clk signal is sent through the serial line.This requires agreement on the transmission parameters by both the transmitterand receiver in advance.This information includes the band rate (number of bits per second), the number

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of data bits and stop bits, and whether parity is being used.Common baud rates are 2400, 4800, 9600 and 19,200.

5.3 UART Receiving SubsystemAn oversampling scheme is commonly used to locate the middle position of the transmitted

bits, i.e., where the actual sample is taken.The most common oversampling rate is 16 timesthe baud rate. Therefore, each serial bit is sampled 16 times but only one sample is savedas we will see.The oversampling scheme using N data bits and M stop bits:Wait until the incoming signal becomes 0 (the start bit) and then start the samplingtick cnter. When the cnter reaches 7, the incoming signal reaches the middle position of thestart bit. Clear the cnter and restart. When the cnter reaches 15, we are at the middle of the first data bit. Retrieve it andshift into a register. Restart the cnter. Repeat the above step N-1 times to retrieve the remaining data bits.

If optional parity bit is used, repeat this step once more. Repeat this step M more times to obtain the stop bits.

The oversampling scheme replaces the function of the clock.Instead of using the rising edge to sample, the sampling ticks are used to estimatethe center position of each bit.Note that the system clock must be much faster than the baud rate for oversamplingto be possible.The receiver block diagram consists of three components.

The interface circuit provides a buffer and status between the UART and the computeror FPGA.

5.4 UART Transmitting SubsystemThe UART transmitting subsystem is similar to the receiving subsystem.It consists of UART transmitter, baud rate generator and interface circuit.Roles are reversed for the interface circuit, i.e., the system sets the flag FF or writesthe buffer interface circuit while the UART transmitter clears FF or reads the buffer.The transmitter is essentially a shift register that shifts out data bits.Since no oversampling is involved, the frequency of the ticks are 16 timesslower than that of the receiver.

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However, instead of introducing another cnter, the transmitter usually shares thebaud rate generator and uses an internal cnter to cnt through the 16 ticks.

5.5 Entire UART SystemBlock diagram of whole system

6. REFERENCES

Wikipedia

Verilog HDL Samir Palnitkar

www.verilog.com

www. fpgacpu.org

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7. FUTURE SCOPE OF TRAINING

In the era of rapid change in technologies the Indian electronics and communicationlandscape is expanding every year and more and more new projects are emerging in the

field of VLSI Design. It requires a large pool of highly skilled and technically soundengineers who can execute these projects. This is an area of concern at PG Level. TheVLSI Design is an advanced level course in the field of Electronics & Communicationengineering in masters with specialization in terms of technology and application to fulfillthe requirements of the industry.VLSI design a huge scope for Indian engineers. Students who have strong electronicsbackground and an engineer degree either in electronics, computer science,electrical etc.are eligible for a career in VLSI design.

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