Field Effect Transistors (1) Dr. Wojciech Jadwisienczak EE314 Q: How we can do this? A: A new generation of MOSFETs for plastic electronics Chapter 12: Field Effect Transistors pp Construction of MOS 2.NMOS and PMOS 3.Types of MOS 4.MOSFET Basic Operation 5.Characteristics 6.Small-Signal Equivalent Circuits 7.Examples Figure nm footprint T-gate with self-aligned source and drain contacts.Figure 4 showing the lateral etching control offered by digital recess etching. In both micrographs, the depth of the recess is 30 nm. The micrograph on the left shows a wide gate recess with large lateral extent whilst the micrograph on the right shows a recess tightly defined around the gate footprint. Building A MOSFET Transistor Using Silicon It is done. Now, how does it work? JFET and MOSFET Transistorsor JFET Junction Field Effect Transistor MOSFET - Metal Oxide Semiconductor Field Effect Transistor n-channel MOSFET & p-channel MOSFET L= m W= m SiO 2 Thickness= m Device characteristics depend on L,W, Thickness, doping levels Symbol n-channel MOSFET Basic Operation Operation in the Cutoff region Schematic pn junction: forward bias, reverse bias i D =0 for v GS < V t0 When v GS =0 then i D =0 until v GS > V t0 (V t0 threshold voltage) n-channel MOSFET Basic Operation Operation in the Triode Region For vi DS V t0 the NMOS is operating in the triode region Resistor like characteristic (R between S & D, Used as voltage controlled R) For small v DS, i D is proportional to the excess voltage v GS -V t0 n-channel MOSFET Basic Operation Operation in the Saturation Region (v DS is increased) Tapering of the channel i D is smaller when v DS is larger Device parameter KP for NMOSFET is 50 A/V 2 When v GD =V t0 then the channel thickness is 0 and n-channel MOSFET Basic Operation Characteristic Example 12.1 Channel length modulation i d depends on v DS in saturation region (approx: i D =const in saturation region) p-channel MOSFET Basic Operation It is constructed by interchanging the n and p regions of n-channel MOSFET. Symbol Characteristic How does operate p-channel MOSFET? -voltage polarities -i D current -schematic Load-Line Analysis of NMOS Amplifier It is a graphical analysis similar to load-line analysis of pn diode. Schematic Analysis Input loop Output loop Load line v GS v DS We look for operating point Load-Line Analysis of NMOS Amplifier Load line Taking i D =0 or v DS =0 we find out the quiescent operating point Q The quiescent values v in (t)=0 then i DQ =9 mA and v DSQ =11V Points A & B intersection of curve and the load-line Input signal Load-Line Analysis of NMOS Amplifier (peak-to-peak amplitude is 2V) 12V Inverse operation The positive peak of the input occurs at the same time as the min. value of v DS. These are not symmetrical sinusoids! (nonlinear distortion) Bias Circuits Analysis of amplifier circuits is often undertaken in two steps: (1) The dc circuit analysis to determine the Q point. It involves the nonlinear equation or the load-line method. This is called bias analysis (2) Use a linear small-signal equivalent circuit to determine circuit parameters The fixed-plus self-bias circuit InputOutput Equivalent circuit Analysis Assume the V RG =0 v GS For saturation region v DS Bias Circuits Plot ofand Disregarded root for v GS < V t0 Use only larger root for v GS and smaller for i D Example 12.2