10/2/2018 1 Analog Electronics (Course Code: EE314) Lecture 15‐17: MOSFETs Indian Institute of Technology Jodhpur, Year 2018 Course Instructor: Shree Prakash Tiwari Email: [email protected]b h //h / / Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/EE314/ 1 Note: The information provided in the slides are taken form text books for microelectronics (including Sedra & Smith, B. Razavi), and various other resources from internet, for teaching/academic use only The MOSFET Gate M etal‐O xide‐S emiconductor F ield‐ E ffect T ransistor: GATE LENGTH, L g OXIDE THICKNESS, T ox • Current flowing through the channel between the source and drain is controlled by the gate voltage Substrate Gate Source Drain JUNCTION DEPTH, X j M. Bohr, Intel Developer Forum, September 2004 source and drain is controlled by the gate voltage. “N‐channel” & “P‐channel” MOSFETs operate in a complementary manner “CMOS” = C omplementary MOS |GATE VOLTAGE| CURRENT V TH
b h //h / /Webpage: http://home.iitj.ac.in/~sptiwari/
Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/EE314/
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Note: The information provided in the slides are taken form text books for microelectronics (including Sedra & Smith, B. Razavi), and various other resources from internet, for teaching/academic use only
• Current flowing through the channel between the source and drain is controlled by the gate voltage
Substrate
Gate
Source Drain
JUNCTION DEPTH, Xj
M. Bohr, Intel DeveloperForum, September 2004
source and drain is controlled by the gate voltage.
“N‐channel” & “P‐channel” MOSFETs operate in a complementary manner“CMOS” = Complementary MOS
|GATE VOLTAGE|
CU
RR
ENT
VTH
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N‐Channel MOSFET StructureCircuit symbol
• The conventional gate material is heavily doped polycrystalline silicon (referred to as “polysilicon” or “poly‐Si” or “poly”)silicon (referred to as polysilicon or poly Si or poly )– Note that the gate is usually doped the same type as the source/drain,
i.e. the gate and the substrate are of opposite types.
• The conventional gate insulator material is SiO2.
• To minimize current flow between the substrate (or “body”) and the source/drain regions, the p‐type substrate is grounded.
• The net charge density [C/cm3] in a semiconductor is
AD NNnpq • Note that p, n, ND, and NA each can vary with position.
• The mobile carrier concentrations (n and p) in the channel of a MOSFET can be modulated by an electric field via VG.
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• As the gate voltage (VG) is increased, holes are repelled away from the substrate surface. – The surface is depleted of mobile carriers The
Channel Formation (Qualitative)
VG < VTH
– The surface is depleted of mobile carriers. The charge density within the depletion region is determined by the dopant ion density.
• As VG increases above the threshold voltage VTH, a layer of conduction electrons forms at the substrate surface.
For V > V n > N at the s rface
VG ≥ VTH
– For VG > VTH, n > NA at the surface.
The surface region is “inverted” to be n‐type.
The electron inversion layer serves as a resistive path (channel) for current to flow between the heavily doped (i.e. highly conductive) source and drain regions.
Voltage‐Dependent Resistor• In the ON state, the MOSFET channel can be viewed as a resistor.
• Since the mobile charge density within the channel depends on the gate voltage, the channel resistance is voltage‐dependent.
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• Shorter channel length and wider channel width each yield lower channel resistance, hence larger drain current.– Increasing W also increases the gate capacitance, however, which
Channel Length & Width Dependence
limits circuit operating speed (frequency).
Comparison: BJT vs.MOSFET• In a BJT, current (IC) is limited by diffusion of carriers from the
emitter to the collector.
– IC increases exponentially with input voltage (VBE), because the /C p y p g ( BE),carrier concentration gradient in the base is proportional to
• In a MOSFET, current (ID) is limited by drift of carriers from the source to the drain.
TBE VVe /
– ID increases ~linearly with input voltage (VG), because the carrier concentration in the channel is proportional to (VG‐VTH)
In order to understand how MOSFET design parameters affect MOSFET performance, we first need to understand how a MOS capacitor works...
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MOS Capacitor• A metal‐oxide‐semiconductor structure can be considered as a
parallel‐plate capacitor, with the top plate being the positive plate, the gate insulator being the dielectric, and the p‐type semiconductor substrate being the negative plate.
• The negative charges in the semiconductor (for VG > 0) are comprised of conduction electrons and/or acceptor ions.
In order to understand how the potential and charge distributions within the Si depend on VG, we need to be familiar with electrostatics...
Gauss’ Law
If th it d f l t i fi ld h th t b h !
E is the net charge density
is the dielectric permittivity
If the magnitude of electric field changes, there must be charge!
• In a charge‐free region, the electric field must be constant.
• Gauss’ Law equivalently says that if there is a net electric field leaving a region, there must be positive charge in that region:
dVdVE
Q
dSE
VV
V
QdV
SV
dSEdVE
The integral of the electric field over a closed surface is proportional to the charge within the enclosed volume
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Gauss’ Law in 1‐D
dx
dEE
• Consider a pulse charge distribution:
dxdE
')'(
)()(0
0 dxx
xExEx
x
)(xE
x0
)(xxdX
AqN
0
dX
Electrostatic Potential
• The electric field (force) is related to the potential (energy):
)()(
2
2 x
d
xVd
d
dVE
– Note that an electron (–q charge) drifts in the direction of increasing potential:
2dxdx
dx
dVqqEFe
)(xxdX
AqN
)(xV
x0
0
)(xE
x0 dX
dX
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Boundary Conditions• Electrostatic potential must be a continuous function.
Otherwise, the electric field (force) would be infinite.
• Electric field does not have to be continuous, however. ,Consider an interface between two materials:
)( 11 E
)( 22 E
insideQSESEdSE 2211 x
then,0 If0
xinsideQ
0 SESES
Discontinuity in electric displacement E charge density at interface!
02211 SESE
1
2
2
1
E
E
MOS Capacitor Electrostatics
• Gate electrode:– Since E(x) = 0 in a metallic material, V(x) is constant.
• Gate‐electrode/gate‐insulator interface:Gate‐electrode/gate‐insulator interface:– The gate charge is located at this interface.E(x) changes to a non‐zero value inside the gate insulator.
• Gate insulator:– Ideally, there are no charges within the gate insulator.E(x) is constant, and V(x) is linear.
• Gate insulator/semiconductor interface:• Gate‐insulator/semiconductor interface:– Since the dielectric permittivity of SiO2 is lower than that of Si, E(x) is larger in the gate insulator than in the Si.
• Semiconductor:– If (x) is constant (non‐zero), then V(x) is quadratic.
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• If the gate and substrate materials are not the same (typically the case), there is a built‐in potential (~1V across the gate insulator).– Positive charge is located at the gate interface, and negative charge in the Si.
MOS Capacitor: VGB = 0
Positive charge is located at the gate interface, and negative charge in the Si.
– The substrate surface region is depleted of holes, down to a depth Xdo
)(V
)(x
xXdo
0
)(xV
x‐tox Xdo0
Qdep
VS,o
Flatband Voltage, VFB
• The built‐in potential can be “cancelled out” by applying a gate voltage that is equal in magnitude (but of the opposite polarity) as the built‐in potential. This gate voltage is called the flatband voltage because the resulting potential profile is flat.
)(V
)(x
x‐tox
0
)(xV
x
‐tox0
There is no net charge (i.e. (x)=0) in the semiconductor under for VGB = VFB.
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Voltage Drops across a MOS Capacitor
SoxFBGB VVVV )(xV
• If we know the total charge within the semiconductor (Q̕S) , we can find the electric field within the gate insulator (Eox) and hence the voltage drop across the gate insulator (Vox):
x‐tox Xd0
where QS is the areal charge density in the semiconductor [C/cm2]
and is the areal gate capacitance [F/cm2]
ox
Sox
QAEdSE
ox
Sox
ox
Soxoxox C
Qt
A
QtEV
oxoxox tC
VGB < VFB (Accumulation)
• If a gate voltage more negative than VFB is applied, then holes will accumulate at the gate‐insulator/semiconductor interface.
)(x
)(xV
)(x
x‐tox
0
x‐tox
0 FBGBoxG VVCQ
Areal gate charge density [C/cm2]:
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VFB < VGB < VTH (Depletion)
• If the applied gate voltage is greater than VFB, then the semiconductor surface will be depleted of holes.– If the applied gate voltage is less than VTH, the concentration ofIf the applied gate voltage is less than VTH, the concentration of
conduction electrons at the surface is smaller than NA (x) ‐qNA(x)
)(V
)(x
x‐tox
Xd
0Areal depletion charge density [C/cm2]:)(xV
x‐tox Xd0
12
1
2
2
2
ASi
FBGBox
ox
Sid
Si
dA
ox
dASoxFBGB
Nq
VVC
CX
XqN
C
XqNVVVV
dAdep XqNQ charge density [C/cm ]:
VGB > VTH (Inversion)• If the applied gate voltage is greater than VTH, then n > NA at
the semiconductor surface.
– At VGB = VTH, the total potential dropped in the Si is 2B where
A
TB
NV lnGB TH, p pp B
)(x
x‐tox
Xd,max
i
TB n
)(xV
x‐tox Xd,max
0
)2(2
2 ox
BASiBFBTH C
NqVV
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Maximum Depletion Depth, Xd,max
• As VGB is increased above VTH, VS and hence the depth of the depletion region (Xd) increases very slowly.
– This is because n increases exponentially with VS whereas XdThis is because n increases exponentially with VS, whereas Xdincreases with the square root of VS. Thus, most of the incremental negative charge in the semiconductor comes from additional conduction electrons rather than additional ionized acceptor atoms, when n exceeds NA.
Xd can be reasonably approximated to reach a maximum value (Xd max) for VGB ≥ VTH. ( d,max) GB TH
– Qdep thus reaches a maximum of Qdep,max at VGB = VTH.
• If we assume that only the inversion‐layer charge increases with increasing VGB above VTH, then
max,)( so and depTHGBoxGBGTHGBoxinv QVVCVQVVCQ
Q‐V Curve for MOS Capacitor
GQA
BSid qN
X)2(2
max,
THGBoxinv VVCQ
max,depQ
VV
VVGB
THVFBV
)2(2max,max, BSiAdAdep qNXqNQ
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VGB = VTH (Threshold)• VTH is defined to be the gate voltage at which the inversion‐layer
carrier concentration is equal to the channel dopant concentration.– For an NMOS device, n = NA at the surface (x=0) when VGB = VTH:
• The semiconductor potential is
• The potential in the body (“bulk”) is
• At VGB = VTH, the potential at the surface is
, A ( ) GB TH
)(x
x‐tox
Xd
Bi
AT n
NV
ln
BA
TT
NV
nV
lnln
iT
iT n
pV
n
nV lnln
The total potential dropped in the semiconductor is 2B
The depletion width is
)(xV
x‐tox Xd0
)2(22
ox
BASiBFBTH C
NqVV
Bi
Ti
T nn
A
BSid qN
X 22
Effect of Channel‐to‐Body Bias• When a MOS device is biased in the inversion region of operation,
a PN junction exists between the channel and the body. Since the inversion layer of a MOSFET is electrically connected to the source, a voltage can be applied to the channel.
VG ≥ VTH
• If the source/channel of an NMOS device is biased at a higher potential (VC) than the body potential (VB), the channel‐to‐body PN junction is reverse biased. The potential drop across the depletion region is increased.
A
CBBSid qN
VX
)2(2
p p p g
The depletion width is increased:
The depletion charge density (Qdep= qNAXd) is increased.
The inversion‐layer charge density is decreased, i.e. VTH is increased.
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Small‐Signal Capacitance
• The MOS capacitor is a non‐linear capacitor:
• If an incremental (small‐signal) voltage dVG is applied in addition b l h l h h
CVVfQ )(
to a bias voltage VG, the total charge on the gate is
• Thus, the incremental gate charge (dQG) resulting from the incremental gate voltage (dVG) is
GGoGVV
GGGG dQQdVdV
VdfVfdVVfQ
G
)()()(
constant charge
incremental gate voltage (dVG) is
• CG is the small‐signal gate capacitance:
GGGVV
G dVCdVdV
VdfdQ
G
)(
GVVG
GG dV
Vdf
dV
dQC
)(
(N)MOS C‐V Curve
• The MOS C‐V curve is obtained by taking the slope of the Q‐V curve.
CG = Cox in the accumulation and inversion regions of operation.
C i ll d i li CG is smaller, and is a non‐linear function of VGB in the depletion region of operation.
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MOS Small‐Signal Capacitance Model
C
Accumulation Depletion Inversion
ox
oxox t
C
oxC oxCoxC
depC
d
Sidep X
C
The incremental charge is located at the semiconductor surface
The incremental charge is located at the bottom edge of the depletion region
The incremental charge is located at the semiconductor surfacesurface the depletion region surface
max,min,
min,
min,min
where
d
Sidep
depox
depox
XC
CC
CCC
MOS Capacitive Voltage Divider
• In the depletion (sub‐threshold) region of operation, an incremental change in the gate voltage (VGB) results in an incremental change in the channel potential (VCB) that is c e e ta c a ge t e c a e pote t a ( CB) t at ssmaller than VGB:
oxC
depC GBd
oxCB V
CC
CV
CV
GV
CBdepGBdepox
depoxG VCV
CC
CCQ
• How can we maximize VCB/VGB ?
dep depox CC
BV
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PMOS Capacitor• The PMOS structure can also be considered as a parallel‐plate
capacitor, but with the top plate being the negative plate, the gate insulator being the dielectric, and the n‐type semiconductor b b i h i i l
Depletion
VTH <VGB < VFB
substrate being the positive plate.– The positive charges in the semiconductor (for VGB < VFB) are comprised of
