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11/14/2018 1 Analog Electronics (Course Code: EE314) Lecture 35: Frequency Response contd.. Feedback Indian Institute of Technology Jodhpur, Year 2018 Feedback Course Instructor: Shree Prakash Tiwari Email: [email protected] b h //h / / Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/EE314/ 1 Note: The information provided in the slides are taken form text books for microelectronics (including Sedra & Smith, B. Razavi), and various other resources from internet, for teaching/academic use only Impedance of Parallel RC Circuit
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Page 1: Impedance of Parallel RC Circuit - Indian Institute of ...home.iitj.ac.in/~sptiwari/EE314/Lecture35_FrequencyResponseContd… · Impedance of Parallel RC Circuit. 11/14/2018 2 Small‐Signal

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1

Analog Electronics(Course Code: EE314)

Lecture 35: Frequency Response contd..Feedback

Indian Institute of Technology Jodhpur, Year 2018

Feedback

Course Instructor: Shree PrakashTiwari

Email: [email protected]

b h //h / /Webpage: http://home.iitj.ac.in/~sptiwari/

Course related documents will be uploaded on  http://home.iitj.ac.in/~sptiwari/EE314/

1

Note: The information provided in the slides are taken form text books for microelectronics (including Sedra & Smith,  B. Razavi), and various other resources from internet, for teaching/academic use only

Impedance of Parallel RC Circuit

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2

Small‐Signal Model for CE Stage

… Applying Miller’s Theorem 

CRgCR CminThevinp

1

1,

1

C

RgCR

CmoutC

outp1

1

1,

Note that p,out > p,in

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CE Stage Pole Frequencies, for VA<∞

CrRgCR oCminThevinp

1

1,

1

Note that p,out > p,in

CrRg

CrRoCm

outoC

outp1

1

1,

I/O Impedances of CE Stage

1 1

r

CrRgCjZ

oCmin ||

1

1

oC

CSout rR

CCjZ ||||

1

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Small‐Signal Model for CS Stage

0

… Applying Miller’s Theorem 

GDDminThevinp CRgCR

1

1,

1

GDDm

outD

outp

CRg

CR1

1

1,

Note that p,out > p,in

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I/O Impedances of CS Stage

0

GDDmGSin CRgCj

Z

1

1

DDBGD

out RCCj

Z ||1

• Note that there is no capacitance between input & output nodes

No Miller multiplication effect!

CB Stage: Pole Frequencies

1

YCYp CR

1,

CSY CCC

or

CB stage with BJT capacitances shown

T

Xm

S

Xp

Cg

R

1||

1,

CCX

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CG Stage: Pole Frequencies

X

1

CG stage with MOSFET capacitances shown

Xm

S

Xp

Cg

R

1||

,

SBGSX CCC

1

0

YDYp CR

1,

DBGDY CCC

Emitter Follower

• Recall that the emitter follower provides high input impedance and low output impedance, and is used as a voltage buffer.

Follower stage with BJT capacitances shown• CL is the load capacitance

Circuit for small-signal analysis (Av)

or

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AC Analysis of Emitter Follower 

• KCL at node X:

vvv outX

• KCL at output node:

011

Cj

v

r

v

Cj

vv

R

vvv out

S

inout

L

outm

Cj

vvg

Cj

v

r

v

11

1)()(

)(1

2

jbja

jg

C

v

v m

in

out

m

LS

mS

LLm

S

g

C

r

R

g

CCRb

CCCCCCg

Ra

1

Ljj

Follower: Zero and Pole Frequencies 

1)()(

)(1

2

jbj

jg

C

v mout

LS

LLm

S

CRC

CCCCCCg

Ra

• The follower has one zero:

• The follower has two poles at lower frequencies:

1)()( 2 jbjavinm

LS

mS g

C

r

R

g

CCRb

1

Tm

z fC

g

2

The follower has two poles at lower frequencies:

21

2 1 11)()(pp

jjjbja

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Emitter Follower: Input Capacitance

• Recall that the voltage gain of an emitter follower is

Follower stage with BJT capacitances shown mL

Lv

gR

RA

1

or

Lm

vX Rg

CCAC

11

• CXY can be decomposed into CX and CY at the input and output nodes, respectively:

Lmin Rg

CCC

1

LmvY Rg

CC

AC

11

Lin RrR 1

Emitter Follower: Output Impedance

Circuit for small-signal analysis (Rout)or

Cjrvgiv mX

1

Crj

CrRRrj

Rr

jCr

RrjCrR

i

vZ SSSSS

X

Xout

/11

/1

11

Smxx Rvgivv

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Emitter Follower as Active Inductor

Cj

CrRRrj

Rr

jCr

RrjCrR

i

vZ SSSSS

X

Xout

/11

/1

11

CASE 1: RS < 1/gm CASE 2: RS > 1/gm

Cr/1

capacitive behavior inductive behavior

• A follower is typically used to lower the driving impedance

RS > 1/gm so that the “active inductor” characteristic on the right is usually observed.   

Cascode Stage

• Review:– A CE stage has large Rin but suffers from the Miller effect.

– A CB stage is free from the Miller effect, but has small Rin.

• A cascode stage provides high Rin with minimal Miller effect.

11

21,

mm

Y

XXYv g

gv

vAor

XYX CC 2

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Cascode Stage: Pole Frequencies

, 2||

1CCrRXp

Cascode stage with BJT capacitances shown

(Miller approximation applied)

111 2|| CCrRS

1212

,

21

1

CCC

g CSm

Yp

22 2 T

mY f

g Note that

or

22,

1

CCR CSL

outp

22

, 2 TYp fC

Note that

Cascode Stage: I/O Impedances

or

111 2

1||

CCjrZin

22

1||

CSLout CCj

RZ

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Summary of Cascode Stage Benefits

• A cascode stage has high output impedance, which is advantageous for

hi i hi h l i– achieving high voltage gain

– use as a current source

• In a cascode stage, the Miller effect is reduced, for improved performance at high frequencies.

MOS Cascode Stage

• For a cascode stage, Miller multiplication is smaller than in the CS stage.

11

21,

mm

Y

XXYv g

gv

vA

XYX CC 2 XYX CC 2

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Cascode Stage: Pole Frequencies

1

Cascode stage with MOSFET capacitances shown

(Miller approximation applied)0

1

22,

GDDBDoutp CCR

12

11

,

1

1

GDm

mGSG

Xp

Cgg

CR

211

221

2

,

11

1

SBGDm

mGSDB

m

Yp

CCgg

CCg

Cascode Stage: I/O Impedances

0

12

11 1

1

GDm

mGS

in

Cgg

Cj

Z

22

1||

DBGDDout CCj

RZ

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Next

• Feedback

Negative Feedback System

26

• A negative feedback system consists of four components:  1) feedforward system, 2) sense mechanism, 3) feedback network, and 4) comparison mechanism.

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Close‐loop Transfer Function

27

1

1

1 KA

A

X

Y

Feedback Example

121

2

1

1 ARR

RA

X

Y

28

• A1 is the feedforward network, R1 and R2 provide the sensing and feedback capabilities, and comparison is provided by differential input of A1.

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Comparison Error

E

KA

XE

11

29

• As A1K increases, the error between the input and fed back signal decreases.  Or the fed back signal approaches a good replica of the input.

Comparison Error 

11R

R

X

Y

30

2RX

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Loop Gain

test

N

V

VKA 1

0X

31

• When the input is grounded, and the loop is broken at an arbitrary location, the loop gain is measured to be KA1.

Example:  Alternative Loop Gain Measurement 

32

testN VKAV 1

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Incorrect Calculation of Loop Gain

33

• Signal naturally flows from the input to the output of a feedforward/feedback system.  If we apply the input the other way around, the “output” signal we get is not a result of the loop gain, but due to poor isolation. 

Gain Desensitization

1KAY 1

34

• A large loop gain is needed to create a precise gain, one that does not depend on A1, which can vary by ±20%.

11 KAKX

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Ratio of Resistors

35

• When two resistors are composed of the same unit resistor, their ratio is very accurate.  Since when they vary, they will vary together and maintain a constant ratio.

Merits of Negative Feedback

1) B d id h• 1)  Bandwidth enhancement

• 2)  Modification of I/O Impedances

36

• 3)  Linearization

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Next

• Feedback contd…


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