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Objective 1: VHDL Code for 2 input XOR Gate using BehavioralModeling Scheme.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity XOR_2 isPort ( a : in std_logic;

b : in std_logic;c : out std_logic);

end XOR_2;

architecture Behavioral of XOR_2 is

beginprocess(a,b)beginif a=b thenc

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Objective 2: Code for 2 input OR Gate using Data Flow ModelingScheme.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity OR_2 isPort ( a : in std_logic;

b : in std_logic;c : out std_logic);

end OR_2;

architecture Dataflow of OR_2 is

beginc

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Objective 3: Code for Half Adder using Structural Modeling Scheme.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity halfadder isPort ( a : in std_logic;

b : in std_logic;sum : out std_logic;carry : out std_logic);

end halfadder;

architecture Structural of halfadder iscomponent AND_2

port(a,b:in std_logic; c:out std_logic);end component;component XOR_2port(a,b:in std_logic; c:out std_logic);end component;beginx1: XOR_2 port map(a,b,sum);x2: AND_2 port map(a,b,carry);

end Structural;

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Objective 4: Code for Full Adder using Mixed Modeling Scheme.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity full_adder isPort ( a : in STD_LOGIC;

b : in STD_LOGIC;cin : in STD_LOGIC;sum : out STD_LOGIC;carry : out STD_LOGIC);

end full_adder;

architecture Mixed_Modeling of full_adder is

signal s1: std_logiccomponent XOR_2port(a,b: in std_logic; c: out std_logic);end component;beginX1: XOR_2 port map(a,b,s1);

sum

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Objective 5: Code for 4 bit Parallel Adder using Structural ModelingScheme

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity adder_4bit_parallel isPort ( a : in STD_LOGIC_VECTOR(3 downto 0);

b : in STD_LOGIC_VECTOR(3 downto 0);s : out STD_LOGIC_VECTOR(3 downto 0);cout : out STD_LOGIC);

end adder_4bit_parallel;

architecture Structural of adder_4bit_parallel is

signal temp: std_logic:='0';signal c: std_logic_vector(2 downto 0);

component fulladder_using_halfadderport(a,b,cin: in std_logic; sum,carry: out std_logic);end component;

begin

FA1: fulladder_using_halfadder port map(a(0),b(0),temp,s(0),c(0));

FA2: fulladder_using_halfadder port map(a(1),b(1),c(0),s(1),c(1));FA3: fulladder_using_halfadder port map(a(2),b(2),c(1),s(2),c(2));FA4: fulladder_using_halfadder port map(a(3),b(3),c(2),s(3),cout);end Structural;

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Objective 6: Code for D-Flip Flop

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity D_flipflop isPort ( D : in STD_LOGIC;

clk : in STD_LOGIC;rst : in STD_LOGIC;

Q : out STD_LOGIC;Qbar : out STD_LOGIC);

end D_flipflop;

architecture D_flip of D_flipflop is

beginprocess(D,clk,rst)beginif rst='1' thenQ

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Objective 7: VHDL Code for 4:1 Multiplexer.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity MUX_4to1 isPort ( a : in STD_LOGIC_VECTOR (7 downto 0);

b : in STD_LOGIC_VECTOR (7 downto 0);c : in STD_LOGIC_VECTOR (7 downto 0);d : in STD_LOGIC_VECTOR (7 downto 0);sel: in STD_LOGIC_VECTOR (1 downto 0);e : out STD_LOGIC_VECTOR (7 downto 0));

end MUX_4to1;

architecture Mux of MUX_4to1 is

beginprocess(a,b,c,d,sel)beginif sel="00" thene

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Objective 8: VHDL code for 3:8 line Decoder using When/Elsestatement.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity DECODER_3to8 isPort ( sel : in STD_LOGIC_VECTOR(2 downto 0);

X: out STD_LOGIC_VECTOR(7 downto 0));end DECODER_3to8;

architecture Decode of DECODER_3to8 is

begin

X

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Objective 9: VHDL code for JK- Flip Flop.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity jkflipflop isPort ( j : in STD_LOGIC;

k : in STD_LOGIC;rst : in STD_LOGIC;clk_en : in STD_LOGIC;clk : in STD_LOGIC;Y : out STD_LOGIC);

end jkflipflop;

architecture jk_flip of jkflipflop is

signal temp: std_logic;beginprocess (clk)

beginif (clk'event and clk='1') then

if rst='1' thentemp

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Objective 10: VHDL code for Parity Detector using Generic Scheme.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity parity_detr_genric isgeneric(n:integer:=7);

Port ( input : in STD_LOGIC_vector(n downto 0);output : out STD_LOGIC);

end parity_detr_genric;

architecture parity of parity_detr_genric is

beginprocess(input)variable temp:std_logic;begintemp:='0';for i in input'range looptemp:= temp xor input(i);end loop;output

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Objective 11: VHDL code for 8-bit Arithmetic and Logical Unit (ALU)Design.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_signed.all;

entity ALU isPort ( a : in STD_LOGIC_vector(7 downto 0);

b : in STD_LOGIC_vector(7 downto 0);cin : in STD_LOGIC;sel : in STD_LOGIC_vector(3 downto 0);y : out STD_LOGIC_vector(7 downto 0));

end ALU;

architecture Behavioral of ALU issignal arith,logic: std_logic_vector(7 downto 0);beginwith sel(2 downto 0) selectarith

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Objective 12: VHDL code for Operator overloading

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

entity operator1 is

port ( a: in STD_LOGIC ;

b:in STD_LOGIC;c:out STD_LOGIC);

function "+"(a:integer,b:bit)return integer isbeginif b='1' return a+1;

else return a;

end if;

end "+";end operator1;

architecture OL of operator1 is

beginprocess(a,b,c)

begin

c

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