Fixed Outline Floorplan

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858 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 5, MAY 2008

Fixed-Outline Floorplanning: Block-PositionEnumeration and a New Method

for Calculating Area CostsSong Chen and Takeshi Yoshimura, Member, IEEE

AbstractIn this paper, we propose a fixed-outline floorplan-ning (FOFP) method [insertion-after-remove (IAR) FP]. An elab-orated method for perturbing solutions, the IAR, is devised. Thisperturbation uses a technique of enumerating block positions,which is implemented based on the floorplan-representation se-quence pair. The proposed perturbation method can greatly ac-celerate searching-based algorithms, such as simulated annealing,by skipping many solutions that fail to meet the fixed-outlineconstraint. Moreover, based on the analysis of the diverse objective

functions used in the existing research works, we suggest forthe FOFP a new objective function which is still effective whencombined with other objectives. Experimental results show that, ifarea and wirelength are optimized simultaneously, using less time,the proposed method obtains much higher average success rate forthe FOFP with various aspect ratios, while the wirelength with thefixed-outline constraint is reduced by 20% on average, comparedwith the latest fixed-outline floorplanners. On the other hand, wevalidated once more by experiments that an aspect ratio close toone is beneficial to wirelength, and hence, a larger area weight isnecessary for the FOFP with a larger aspectratio to ensure feasiblesolutions.

Index TermsFixed outline, floorplanning, sequence pair (SP).

I. INTRODUCTION

AS THE IC technology advances, integrated density keeps

increasing. A single chip can integrate more and more

functions and often includes millions of transistors. Multi-

level hierarchical design is an essential method to cope with

the increasing design complexity. Fixed-outline floorplanning

(FOFP) enables multilevel hierarchical design [1], where aspect

ratios and area of floorplans are usually imposed by higher level

floorplanning and must be satisfied. Hence, a floorplan violating

fixed-outline constraint is useless. Kahng [2] also pointed out

that modern very large scale integration design is based on a

fixed-die (fixed-outline) floorplan rather than a variable-die one.The FOFP has been shown to be much more difficult than

outline-free floorplanning [1]. In Parquet [1], [3], based on

sequence pair (SP) [4], the author presented new objective

functions to drive simulated annealing and better local search

Manuscript received April 30, 2007; revised August 31, 2007 andNovember 16, 2007. This work was supported in part by the Knowledge ClusterInitiative implemented by the Ministry of Education, Culture, Sports, Scienceand Technology (MEXT). This paper was recommended by Associate EditorD. Z. Pan.

The authors are with the Graduate School of Information, Production andSystems, Waseda University, Kitakyushu 808-0135, Japan (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCAD.2008.917968

with new types of moves for the FOFP. References [5] and [6]

incorporated min-cut partitioning into floorplanning to improve

the performance and runtime of Parquet. Liu et al. [7] pro-

posed an FOFP method based on instance augmentation, which

started with a subset of blocks and progressively worked on

larger subsets until all of the blocks were involved. However,

there was no consideration of interconnect. Lin et al. [8]

proposed an evolutionary-search-based robust FOFP method,which only took area into account. Chen and Chang [9], [10]

presented an adaptive fast simulated annealing (SA) scheme

that dynamically changed the weights in the cost function to

optimize the wirelength under the outline constraint.

It is easy for the existing flat fixed-outline floorplanners to

get feasible solutions if area is the only objective. If wirelength

is also considered, however, finding feasible solutions becomes

difficult for them. Partially, it is due to inappropriate objective

functions. We analyzed the objective functions used in the ex-

isting FOFP methods and found that all of them have limitations

(Section III-B) when combined with other objectives.

In this paper, we suggest for the FOFP a new function to

calculate area costs, which is still effective when combinedwith other objectives. The objective function is used in the pro-

posed fixed-outline floorplanner insertion-after-remove (IAR)

FP (IARFP). An elaborate method for perturbing solutions, the

IAR, is also devised for annealing-based search algorithms.

This perturbation uses a technique of enumerating block posi-

tions, which is implemented based on a floorplan-representation

SP, and takes O(n2) time without considering wirelength. Theproposed perturbation method can greatly accelerate searching-

based algorithms since many solutions that failed to meet

the fixed-outline constraint are skipped. Compared with some

previous fixed-outline floorplanners, IARFP is very effective

and has a good scalability. Experiments show that, if area andwirelength are optimized simultaneously, using less running

time, IARFP obtains 94.24% average success rate compared

with the average success rates of 67.2% and 31% obtained by

Parquet 4.5 [11] and the B-tree-based fixed-outline floor-planner [10] National Taiwan University (NTU-FOFP), respec-

tively. At the same time, the IARFP reduces the wirelength

with fixed-outline constraint by 21% and 19%, respectively,

compared with Parquet 4.5 [11] and NTU-FOFP [10].

Additionally, it has been shown, in existing research works,

that the aspect ratio of the chip (the ratio of the chip width to

the chip height) has an effect on wirelength [1]. However, there

are no proper interpretations for this. In this paper, by dividing

0278-0070/$25.00 2008 IEEE


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CHEN AND YOSHIMURA: FOFP: BLOCK-POSITION ENUMERATION AND A METHOD FOR CALCULATING AREA COSTS 859

the half-perimeter wirelength (HPWL) into the wirelength

along two directions (x- and y-axes), we interpret it intuitivelyand show by experiments that an aspect ratio close to one is

beneficial to wirelength.

The organization of this paper is as follows. Section II

gives the problem definition and briefly reviews the floorplan-

representation SP. Section III shows the analysis of the objec-tive functions and the flow of the FOFP. Section IV elaborates

the technique of enumerating block positions in SP. Section V

discusses the wirelength evaluation during enumerating inser-

tion points. Section VI analyzes the complexity. Section VII

compares the proposed FOFP method with some latest fixed-

outline floorplanners and analyzes the relation between aspect

ratio and wirelength by experiments. Section VIII draws some

conclusions.

II. PROBLEM FORMULATION

Let S = {bi|1 i n} be a set of rectangular blocks,among which connections (nets) exist, and each block bi hasspecified width wi and height hi. The FOFP is an assignment oftwo tuples (xi, yi) to blocks such that the following conditionsare achieved.

1) There is no overlapping between any two blocks.

2) All the blocks are packed into the specified region (fixed

outline).

3) Some objectives, for example, area, wirelength, etc., are

optimal (minimized).

Given the total area A of the blocks and a maximum whitespacefraction , we construct a fixed outline with an aspect ratio 1 [1] as follows:

W0 =

(1 + )A, H 0 =

(1 + )A/.

Without special declaration, the aspect ratio is defined asW0/H0(> 1) in this paper.

The well-studied SP [4] is used as the floorplan representa-

tion. An SP is a pair of sequences of n elements representing alist of n blocks. It imposes the relationship between each pairof blocks as follows:

( bi bj , bi bj )bi is left to bj

( bj bi , bi bj )bibelow

bj .

The original paper that proposed the SP presented an O(n2)algorithm to transform an SP into a floorplan. Tang et al. [12]

sped up the evaluation algorithm to O(nloglogn).A block position, in an SP (P, M), means an insertion point

represented by a tuple (p, m), where p is one position betweentwo adjacent blocks in P, and m is one position between twoadjacent blocks in M. p(m) may also be the position beforethe first block or after the last block in P(M). Hence, thereare (n + 1) candidate positions for insertion in each sequence,and there are totally (n + 1)2 block positions to insert a blockin a given SP. As shown in Section IV, some of them will be

equivalent because of having the same distances to the chipboundaries.

Fig. 1. Optimization flow.

III. FOFP

A. Overview

Fig. 1 shows the flow of the proposed fixed-outline floor-

planner (IARFP). The initial solution is generated randomly,

and then, the simulated annealing engine is invoked. Instead

of the traditional methods of perturbing solutions, for example,

swapping blocks, moving blocks, etc., we elaborate a pertur-

bation method, the IAR, which is based on the strategy of

IAR. (O-tree-based floorplanning method [13] used a simple

remove-and-insertion perturbation strategy.) In this paper, we

propose an elaborate insertion procedure which can accelerate

the searching greatly by skipping many solutions that fail tomeet the fixed-outline constraint.

In Fig. 1, the step Select an insertion point for the removed

block does not just select a random position for the removed

block. Instead, candidate block positions are restricted within

a small range by enumerating insertion points, which is imple-

mented based on SP (Section IV). The flow of the selection is

as follows.

1) Compute the floorplan of the blocks except the re-

moved one.

2) Enumerate all the insertion points based on the floorplan

information obtained in step 1), and select a fixed number

of candidate insertion points (CIPs) for the removed block

by rough evaluations.

3) Choose for the removed block one of the candidate inser-

tion points selected in step 2).

In step 2), the insertion points are evaluated by the linear

combination of the area costs and the wirelength of the nets

related to the removed block. Area costs are calculated in (5)

defined in the next section. In this step, since the candidate

insertion points are restricted into a small range, many solutions

that are faraway from meeting the fixed-outline constraint are

skipped. The enumeration of insertion points will be discussed

in Section IV.

In step 3), we can randomly choose one insertion point in

the CIPs selected in step 2) and calculate its costs accurately.If there is an improvement, the corresponding insertion point


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Fig. 2. Potential tradeoff between area and aspect ratio.

will be the new position of the removed block. Otherwise, an

acceptable probability will be calculated.

On the other hand, we can evaluate all the CIPs selected in

step 2) accurately. We insert the block into the SP at each CIP

and compute the costs by a linear combination of area costs (5)

and total wirelength. If the best one of them shows an improve-

ment, the corresponding insertion point will be the new position

of the removed block. Otherwise, an acceptable probability will

be calculated. In such a case, the greedy strategy is used, but it

is much faster. In the experiments, we use such a method for

wirelength-driven FOFP.

B. Objective Functions

In this section, we analyze the limitations of the objective

functions used in the existing FOFP methods. Additionally,

we propose a new objective function for the FOFP problem.

The proposed function works well when optimizing multiple

objectives.

In [1], the following objective functions were suggested:

max(W W0, 0) + max(H H0, 0) (1)max(W

W0, H

H0). (2)

The authors showed by experiments that a classic annealer-

based floorplanner was practically unable to satisfy fixed-

outline constraints under these objective functions, thus devised

slack-based moves for FOFP. However, when combined with

other objectives, for example, wirelength, such functions are

likely to be ineffective because the function values hardly reach

zero if competitions from other objectives exist.

The following functions were also used [7], [9]:

max(H H0, 0)/H0 + max(W W0, 0)/W0 (3)W H + (W/H W0/H0)2. (4)

The functions have the same problem as the functions defined

in (1) and (2). Equation (4) combines the area and the aspect

ratio. Both objectives may conflict with each other. Therefore,

this function potentially makes a tradeoff between the area and

the aspect ratio. Fig. 2 shows an illustration. Assume that Wdecreases by x and H increases by y. The new area will be

(Wx) (H+y) = W H(H xW y+xy).

In such a case, the aspect ratio (W/H) is reduced. However,the area may decrease, keep unchanged, or increase, depending

on x and y which are difficult to predict based on solution

perturbations. The area decreases if (W/x H/y) < 1, isunchanged if(W/x H/y) = 1, and increases otherwise.

In this paper, we suggest the following objective function for

calculating the area costs in FOFP:

EW+EH +C1 max(EW, EH )+ C2 max(W, H )(5)

where EW = max(W

W0, 0) and EH = max(H

H0, 0)

are the excessive width and height of the floorplan, respectively,and C1 and C2 are some user-defined constants. Generally, C1is greater than C2. In our experiments, C1 = 1, and C2 = 1/16for all test cases. The differences between the proposed function

and the functions aforementioned are as follows.

1) The values related to the height of the chip are scaled by

the aspect ratio . Without scaling H, experiments showthat the shorter of width and height of the fixed-outline

will be violated with a very high probability if aspect

ratios are far from one.

2) An additional penalty item is added for the larger of

EH and EW. The bigger of the excessive width andexcessive height should be penalized more.

3) An additional penalty item is added for the larger ofH and W. This item keeps the function effective when com-bined with other objectives since width and height can be

reduced even though excessive width and height are close

to zero. On the other hand, as the aspect ratio grows, this

item also increases, which ensures the competitiveness

of the fixed-outline constraint if some other objectives,

for example, wirelength, etc., exist. Because, according

to our experiences, the larger the aspect ratio ( 1), thelonger the wirelength. An explanation will be given in the

next section.

C. Aspect Ratio and Wirelength

In the HPWL model, the wirelength is estimated by

nets

(xmax xmin) + (ymax ymin)

where xmax denotes the maximum x coordinates of all thepins involved in a net (xmin, ymin, and ymax have simi-lar meaning). We denote the wirelength in x-direction bywirex(=

nets(xmax xmin)) and wirelength in y-direction

by wirey(=

nets(ymax ymin)).There is a well-known simple geometric observation that the

square has the smallest perimeter among all the rectangles withthe same area, and the larger the aspect ratio ( 1), the longerthe perimeter.

In the FOFP, the area of the outline envelop is fixed. There-

fore, the bigger the aspect ratio, the larger W0 + H0. Thiscould cause different distributions of HPWL in the x-direction(corresponding to W) and in the y-direction (correspondingto H) from different aspect ratios. Intuitively, larger aspectratio means more wirex and less wirey since many nets might

have larger bounding-box aspect ratios under larger chip aspect

ratios. wirex + wirey will be larger if the bounding boxes havesimilar area.

According to [14], the statistical expectation of the dif-

ference between maximum and minimum for k independentrandom points uniformly distributed on the segment [0, L] is


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[1 2/(k + 1)] L. Therefore, the expected wirex, wirey, andwirex + wirey are linear with W, H, and W + H, respectively.Although, in real cases, the blocks could not overlap with

each other and any wirelength-driven fixed-outline floorplanner

tends to place blocks with more interconnections together, this

overestimate shows the trend wirelength changes with chip

dimensions.In Section VII-C, the experiments are devised to demonstrate

this trend. Area costs are calculated using (5), and the following

formula is modified from (5), in which width and height are

scaled by 1/

and

, respectively, to keep similar area costsfor all aspect ratios:

EW/

+ EH

+ C1 max(EW/

, EH

)

+ C2 max(W/

, H

). (6)

In the experiments, besides computing the HPWL, we also

calculate wirex and wirey , respectively. We find that the wire-

length increases as the chip aspect ratio increases. The ratio

of wirex to wirey becomes larger and larger as the aspect

ratio increases, whereas the geometric mean (

x y) of themvaries in a much smaller range compared with the change

of wirelength. These are consistent with the aforementioned

simple geometric observation.

IV. ENUMERATING INSERTION POINTS

As discussed in Section II, given an SP of n blocks, there are(n + 1)2 insertion points for inserting a block. To restrict thecandidate block positions within a small range, it is important

to evaluate these insertion points efficiently. In order to evaluate

an insertion point for a block, we have to estimate the chipdimensions and wirelength after inserting the block into the

insertion point. In this section, we discuss how to evaluate the

chip dimensions for each insertion point. The estimation of

wirelength will be discussed in the next section.

A. Distances of Insertion Points to a Chip Boundary

To compute the chip dimension after inserting a block into an

insertion point, we first compute the corresponding x/xr/y/yr

distances (later defined in this section) of the insertion point.

Then, the sum of x distance, xr distance, and the width of the

block is calculated. The new chip width will be the maximumof the sum and the current chip width. In the remainder of this

section, we discuss the computation of these distances in detail.

Given n blocks, bi, i = 1, . . . , n, and their sequence P, thefollowing notations are used in the rest of this section:

P[I] ith block in P, 1 i n.Pi prefix of P with length i, 0 i n; P0 means an

empty prefix, and Pi = P[1]P[2] P[i], 1 i n.LP[b] position of blockb in P, e.g., LP[P[i]] = i.Given an SP (P, M), we use (p, m) to represent an insertion

point for a block in (P, M) that consists of the insertion po-sition in sequence P just after block p and the insertion po-sition in M just after block m, where p, m

{0

}

{bi

|i =

1, . . . , n}, and zero means the insertion position at the be-ginning of a sequence (before the first block). Inserting

a block b into an insertion point (P[i], M[j]) means anew SP (P, M) = (P[1] P[i]b P[i + 1] P[n], M[1] M[j]b M[j + 1] M[n]).

Definition 1: The x distance of an insertion point (p, m). Ifa block is inserted into (p, m), in the corresponding floorplan,the minimum distance from the left boundary of the block to

that of the chip is defined as the x distance of (p, m), denotedas x(p,m).

We can similarly define the y distance of (p, m), denotedas y(p,m), which is the minimum distance to the chip bottomboundary, the xr distance of (p, m), denoted as xr(p,m), whichis the minimum distance to the chip right boundary, and the yr

distance of (p, m), denoted as yr(p,m), which is the minimumdistance to the chip top boundary.

Let LCS(Pi, Mj) be the block-width-weighted longest com-mon subsequence of Pi and Mj , and let lcs(Pi, Mj) be theweight sum of the elements in LCS(Pi, Mj)

1 [12]. As presented

in [12], x(P[i],M[j]) = lcs(Pi, Mj). Let PR denote the reverse

of a sequence P, and let (PR)i be the prefix ofPR. Similarly,we have

y(P[i],M[j]) = lcs

(PR)ni, Mj

xr(P[i],M[j]) = lcs

(PR)ni, (MR)nj

yr(P[i],M[j]) = lcs

Pi, (MR)nj

.

When computing y(P[i],M[j]) and yr(P[i],M[j]), we use block-

height-weighted longest common subsequences.

In this section, we discuss a method to compute the xdistance of total (n + 1)2 insertion points in O(n2) time, whichis linear with the number of insertion points.

1) Computing the xDistance for All Insertion Points: Given

an SP (P, M) of n blocks, it is obvious that x(p,0) = 0 andx(0,m) = 0, where p, m {0}

{bi|i = 1, . . . , n}. We needto compute the x distance of n2 insertion points (P[i], M[j]),where 1 i n and 1 j n. Because x(P[i],M[j]) =lcs(Pi, Mj), x(P[i],M[j]) has nothing to do with block M[l],j < l n, which is right to M[j] in M. Accordingly, thex distances can be computed by visiting the blocks on the orderof sequence M.2

The following algorithm is modified from an algorithm in

[12]. It computes the x distances of all the insertion points.

Algorithm 1: COMPUTE_ALL_0(P, M)

1. Initialize distance vector X with 0;2. For i = 1 to n3. ip = L

P[M[i]]; //get the position ofM[i] in P4. t = X[ip] + w(M[i]);

//w(M[i]) means the width and x(P[ip],M[i]) = t.5. For j = ip to n do //update X6. if (t > X[j])7. X[j] = t;8. else break;

1For example, 1345 is one of the longest common subsequences of twosequences 13245 and 12345. If the elements of the sequences are weighted,the LCS(S1, S2) is defined as the common subsequence with the maximumweight lcs(S1, S2).

2x(P[i],M[j]) also has nothing to do with block P[l], i < l n, which is

right to P[i] in P. In our discussion, we choose M as the order.


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In the following discussions, we use Xi to represent thestatus of vector X at the end ofith i-for loop.

Theorem 1: Given an SP (P, M) of n blocks, Algorithm 1correctly computes the x distances of n2 insertion points(P[l], M[i]), where 1 l n, and 1 i n, and

x(P[l],M[i]) = X

i

[l].

Proof: We use an induction on i to prove that the x dis-tances of the insertion points in (P, M) are correctly computed.

Initially, in Algorithm 1, X[l], l = 1, . . . , n, is zero.When i = 1, let ip = Lp[M[1]], i.e., P[ip] = M[1]. After the

first i-for loop finishes, we can easily know that X1[l] = 0 ifl < ip and X1[l] = M[1] ifip l n.

1) If l = ip, since M1 includes only M[1], we havex(P[ip],M[1]) = lcs(Pip , M1) = w(M[1]).

2) Ifl < ip, x(P[l],M[1]) = lcs(Pl, M1) = 0.3) Ifl > ip, x(P[l],M[1]) = lcs(Pl, M1) = w(M[1]).

Based on 1), 2), and 3)

x(P[l],M[1]) = X1[l], l = 1, . . . , n .

Assume that, when i = k

x(P[l],M[k]) = Xk[l], l = 1, . . . , n .

We prove that

x(P[l],M[k+1]) = X(k+1)[l], l = 1, . . . , n .

When i = k + 1, let ip = LP[M[k + 1]] and b = P[ip] =

M[k + 1]. Let j0 be the break point of j-for loop in step 5.

It is obvious that j0 > ip.After finishing the (k + 1)th i-for loop, we know

that X(k+1)[l] = Xk[l] if 1 l < ip or j0 l n andX(k+1)[l] = Xk[l] + w(M[ip]) = t ifip l < j0.

1) If1 l < ipx(P[l],M[k+1]) = lcs(Pl, Mk+1) = lcs(Pl, Mk)

= x(P[l],M[k]) = Xk[l] = X(k+1)[l].

2) Ifl = ip

x(P[ip],M[k+1]) = lcs(Pip , Mk+1)

= lcs(Pip1b, Mkb)= lcs(Pip1, Mk) + w(b)= lcs(Pip , Mk) + w(b)

= x(P[ip],M[k]) + w(b)

= Xk[ip] + w(b)

= X(k+1)[ip].

3) Ifip < l < j0, based on the condition in step 6, we knowthat x(P[ip],M[k+1]) = t > x(P[l],M[k]), i.e.,

lcs(Pip , Mk+1) > lcs(Pl, Mk), ip < l < j0. (7)

Let us check the relation between b(= M[k + 1] =P[ip]) and LCS(Pl, Mk+1). If b is not an element

of LCS(Pl, Mk+1), we can get lcs(Pl, Mk+1) =lcs(Pl, Mkb) = lcs(Pl, Mk). Considering (7), we have

lcs(Pip , Mk+1) > lcs(Pl, Mk+1). (8)

We should have lcs(Pip , Mk+1) lcs(Pl, Mk+1)since ip < l. It is a contradiction. Hence, b must bean element of LCS(Pl, Mk+1). Then, lcs(Pl, Mk+1) =lcs(Pip , Mk+1), i.e., x(P[l],M[k+1]) = x(P[ip],M[k+1]) =

X(k+1)[ip]. Since X(k+1)[l] = X(k+1)[ip], ip < l < j0,

we get

x(P[l],M[k+1]) = X(k+1)[l], ip < l < j0.

4) Ifj0 l n, we prove that x(P[l],M[k+1]) = x(P[l],M[k])using a proof by contradictory.

Assume that x(P[l],M[k+1]) = x(P[l],M[k]), j0 l n.Because x(P[l],M[k+1]) = lcs(Pl, Mk+1) lcs(Pl,

Mk) = x(P[l],M[k]), we get

x(P[l],M[k+1]) > x(P[l],M[k]), j0 l n. (9)

Since j-for loop breaks at j = j0, we have

x(P[ip],M[k+1]) x(P[l],M[k]), j0 l n

i.e.,

lcs(Pip , M(k+1)) lcs(Pl, Mk), j0 l n. (10)

On the other hand, let us check the relation be-

tween b and LCS(Pl, Mk+1). If b does not belong toLCS(Pl, Mk+1), we have

lcs(Pl, Mk+1) = lcs(Pl, Mkb) = lcs(Pl, Mk)

i.e., x(P[l],M[k+1]) = x(P[l],M[k]), which contradicts with(9). Hence, b must be an element of LCS(Pl, Mk+1). Weget lcs(Pl, Mk+1) = lcs(Pip , Mk+1) accordingly. Con-sidering (10), we have lcs(Pl, Mk+1) lcs(Pl, Mk), i.e.,

x(P[l],M[k+1]) x(P[l],M[k]), j0 l n

which contradicts with (9). Consequently, if j0

l

n

x(P[l],M[k+1]) = x(P[l],M[k]) = Xk[l] = X(k+1)[l].

In short, based on 1), 2), 3), and 4), we get

x(P[l],M[k+1]) = X(k+1)[l], l = 1, . . . , n .

Q.E.D.

Algorithm 1 can accept an SP (PR, MR) to compute thexr distance of all the insertion points in (P, M). Similarly,if elements are weighted by block height (i.e., in step 4 of

Algorithm 1, w(M[i]) is the height of M[i]), Algorithm 1 can

accept the SPs (PR, M) and (P, MR) to compute the y and yrdistances, respectively.


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2) Implementation of Algorithm 1: As discussed in the pre-

vious section, the x and y distances of insertion points can becomputed by visiting the blocks on the order of sequence M.However, the xr and yr distances have to be computed on theorder of sequence MR. Accordingly, in order to compute thefour distances of insertion points by visiting blocks on the order

ofM, we have to get the statuses ofX, corresponding to the xr

and yr distances, on the order ofXn, Xn1, . . . , X 1. Trivially,we can back up the status of X at the end of each i-for loop,but O(n2) space is needed, and we have to visit the insertionpoints one by one even though they have the same distances

to chip boundaries. In this section, we give a modification of

Algorithm 1 with X managed by a doubly linked list, in whichthe statuses of X can be easily backed up in O(n) space andrestored in O(n) time (Section IV-B will discuss the backingup and the restoring of doubly linked lists in detail).

Algorithm 2: COMPUTE_ALL(P,M,w,X,dl,bk_dl)1. dl[H].suc = T; dl[T].pre = H;2. X[H] = 0;3. For i = 1 to n4. ip = L

P[M[i]];//get the position ofM[i] in P5. it = H; lp = dl[it].suc;6. while (lp = T) and (lp < ip)

//Find the insertion position in dl for ip.7. it = lp;8. lp = dl[lp].suc;9. t = X[it] + w(M[i]);//x(P[ip],M[i]) = t.10. X[ip] = t;11. while (lp = T) and (t > X[lp])12. lp = dl[lp].suc;

13. bk_dl[ip].suc = dl[it].suc; bk_dl[ip].pre = dl[lp].pre;14. dl[it].suc = ip; dl[ip].suc = lp; //update dl15. dl[lp].pre = ip; dl[ip].pre = it; //update dl

In Algorithm 2, step 1 initializes the doubly linked list. HandT could be zero and n + 1, respectively. Steps 4 to 9 achievethe same function as that of step 4 in Algorithm 1. Compared

with Algorithm 1, Algorithm 2 only records the change points

of values in X by a doubly linked list dl. In step 10, a newvalue is recorded in X at point ip. The steps from 11 to 15update the doubly linked list to a new status by inserting a new

node corresponding to ip (note that ip is the position of M[i]

in sequence P, which determines the position in the dl of thenode) and removing any node after ip whose value is less thanthat at ip(t). The new status of the dl records the change pointsof value in the new X status.

In step 13, we add a statement for backing up the doubly

linked lists (note that bk_dl is not a doubly linked list). Letdli be the status of dl at the end of ith for-loop. Based on thisbackup, we can easily restore the status of dl from dli+1 to dli.Accordingly, we can easily know the Xi from Xi+1, 1 i n 1 (Section IV-B).

Fig. 3 shows an example of dl. The given SP is (P, M) =(f cedba, cbfade), and the block dimensions are shown in thefigure. The x distance of the insertion points is shown in

the captions of the subfigures. In each subfigure, the relatedpart of the floorplan is also shown. The dashed vertical line

segments in the floorplans correspond to the change points of xdistance. The rj labels show the regions to which the insertionpoints correspond. For example, in Fig. 3(a), the insertion point

(f, c) corresponds to region r1, and (p, c), p = c,e,d,b, and a,corresponds to region r2.

In Algorithm 2, the total iteration number of while-loop in

step 11 is less than n because the total number of elementsdeleted from the dl in the whole for-loop is less than n. Thewhile-loop in steps 6 to 8 totally consumes O(n2) time duringthe whole for-loop. Therefore, the complexity of Algorithm 2 is

also O(n2). In the experiments, we combine a complete binarytree with the doubly linked list. The insertion and deletion

operation on dl can be done in log(n) time [12], and thecomplexity of Algorithm 2 can be reduced to O(n(log(n)))accordingly.3 Since the implementation is the same as that in

[12], we skip the discussion.

B. Backing Up and Restoring the Doubly Linked List

As discussed in Section IV-A1, the x and y distances ofinsertion points can be computed by visiting the blocks on the

order of sequence M, whereas the xr and yr distances haveto be computed on the order of sequence MR. Accordingly, ifwe want to compute the four distances of insertion points by

visiting blocks on the order of M, we have to get the statusesof the doubly linked lists dl, corresponding to the xr and yr

distances, on the order of dln, dln1, . . . , dl1. In this section,we discuss how to back up and restore the doubly linked list so

that we can visit the statuses of doubly linked lists on the order

ofdln, dln1, . . . , dl1.In order to insert an element into a doubly linked list, we have

to change two pointers (one in the forward list and the other inthe backward list) and add two new pointers that point out from

the inserted element.

The statements in steps 14 and 15 of Algorithm 2 show the

operation of inserting a node into the dl. Let dli1 and dli

denote the statuses ofdl at the end of(i 1)th and ith for-loop,respectively. In the forward linked list, although a new pointer

that points out from ip is added, in dli1, only the pointer that

points out from it is changed. Correspondingly, a pointer in thebackward linked list is changed. Therefore, we can get dli1

from dli by restoring these two changed pointers. In step 13of Algorithm 2, bk_dl[ip].suc and bk_dl[ip].pre recorded thechanged pointers. Given dli, we can get dli1 from dli byassigning bk_dl[ip].suc to dl

i[it].suc and bk_dl[ip].pre todli[lp].pre. The operations of restoring the doubly linked listare as follows.

Func. 1 restore_list (ip,dl,bk_dl)t1 = dl[ip].suc;t2 = dl[ip].pre;dl[t2].suc = bk_dl[ip].suc;dl[t1].pre = bk_dl[ip].pre;

3

In theory, this complexity can be O(n(log log(n))) by using a moreadvanced priority [12]. However, the results in [12] showed that such an algo-rithm has advantages only when the block number is more than around 4000.


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Fig. 3. Computation ofx distance. (a) M[1] = c, w(c) = 2: x(p,c) = 0 ifp = f(r1); x(p,c) = 2 ifp = c,e,d,b,a(r2). (b) M[2] = b, w(b) = 2 : x(p,c) = 0

ifp = f(r1); x(p,c) = 2 ifp = c,e,d(r2); x(p,c) = 4 ifp = b, a(r3). (c) M[3] = f, w(f) = 3: x(p,c) = 3 ifp = f , c , e , d(r2); x(p,c) = 4 ifp = b, a(r3).

(d) M[4] = a, w(a) = 2: x(p,c) = 3 if p = f , c , e , d(r2); x(p,c) = 4 if p = b(r3); x(p,c) = 4 if p = a(r4). (e) M[5] = d, w(d) = 3: x(p,c) = 3 if p =

f , c , e(r2); x(p,c) = 4 ifp = d,b,a(r3). (f) M[6] = e, w(e) = 3 : x(p,c) = 3 ifp = f, c(r2); x(p,c) = 4 ifp = e,d,b,a(r3).

It is obvious that Func.1 can be done in constant time.

Therefore, we can sequentially restore the n statuses of dl inO(n) time. In Algorithm 2, we can easily know that the spacecomplexity of backing up dl is O(n).

An example is used to show the backing up and restoring of

doubly linked lists. Given the SP (P, M) = (f cedba, cbfade)used in Section IV-A2, Fig. 4 shows an example on the yr

distance, which is computed based on the pair of sequences

(P, MR) = (f cedba, edafbc). As we move from e to c, theillustration of the changing dl is shown in Fig. 4(a)(f). Thestatuses of dl, X, and bk_dl at the end of each loop arealso shown in the corresponding subfigure. In the figure,

dl[H].suc is shown in the captions of the subfigures forconvenience.

For instance, in Fig. 4(d), f(LP[f] = 1) (ip = 1) is insertedinto dl with a value of three stored in X, and e and d are deletedfrom dl since their values are not more than three. Because thetwo pointers changed to f previously point to e and d, respec-tively, we need to record (e, d) for restoring dl to the statusbefore f is inserted. Since LP[f] = 1, LP[e] = 3, and LP[d] =4, we set bk_dl[1].suc = 3 and bk_dl[1].pre = 4 (in the figure,the corresponding values are displayed using italic fonts). The

dl status shown in Fig. 4(c) easily comes back by redirectingthe forward pointer that ends at f to e and the backward pointerthat ends at f to d. Based on function 1, since dl[1].pre = Hand dl[1].suc = 6(LP[a] = 6), the status of the doubly linked

list is restored to that in Fig. 4(c) by setting dl[H].suc =bk_dl[1].suc(= 3) and dl[6].pre = bk_dl[1].pre(= 4).

C. Enumerating Insertion Points

Based on the technique of backing up and restoring doubly

linked list discussed in the previous section and the Algorithm 2

discussed in Section IV-A2, we give an algorithm to enumerate

the insertion points for a block.

Algorithm 3: ENUMERATE_SP(P , M , b)1. COMPUTE_ALL(PR, MR, w, Xxr , dlxr , bk_dlxr );//compute xr distance and back up the doubly linked liststatuses

2. COMPUTE_ALL(P, MR, h, Xyr , dlyr , bk_dlyr );//compute yr distance and back up the doubly linked liststatuses

3. dlx[H] = T; Xx[0] = 0;4. dly[H] = T; Xy[0] = 0;5. For i = 1 to n6. update_dl(LP, M[i], dlx, Xx, w);

7. update_dl(LPR

, M[i], dly , Xy , h);

8. restore_dl(LPR

[M[i]], dlxr , bk_dlxr );9. restore_dl(LP[M[i]], dlyr , bk_dlyr );10. scan_dls(dlx, Xx, dly, Xy, dlxr , Xxr , dlyr , Xyr , b);

Steps 1 and 2 call Algorithm 2. The function Update_dl()includes steps 4 to 15 in Algorithm 2 except step 13. The

names with the subscript x correspond to the computation of

x distance. The other names have similar implications. Thefour linked lists are simultaneously scanned in the function


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Fig. 4. Backing up and restoring of a doubly linked list. (a) dl[H].suc = 3: M[1] = e, w(e) = 1 ; the pointers to (T, H) are redirected to insert e.

(b) dl[H].suc = 3 : M[2] = d, w(d) = 2; the pointers to (T, e) are redirected to insert d. (c) dl[H].suc = 3: M[3] = a, w(a) = 1 ; the pointers to (T, d)are redirected to insert a. (d) dl[H].suc = 1: M[4] = f, w(f) = 3; the pointers to (e, d) are redirected to insert f. (e) dl[H].suc = 1: M[5] = b, w(b) = 2; thepointers to (a, a) are redirected to insert b. (f) dl[H].suc = 1: M[6] = c, w(c) = 3; the pointers to (b, b) are redirected to insert c.

scan_dls(), which is not difficult to implement. We will explainthe operations by an example in Section IV-E.

D. Evaluation and Selection of Insertion Points

During scanning the doubly linked lists, it is easy to compute

the chip width and the chip height according to four distances

of insertion points to chip boundaries. Let W and H be thewidth and the height of the floorplan transferred from (P, M).If a blockb is inserted into an insertion point (P[i], M[j]), thechip width should be max(x(P[i],M[j]) + x

r(P[i],M[j]) +

b.width, W), and the chip height should be max(y(P[i],M[j]) +yr(P[i],M[j]) + b.height, H). Then, (5) can be used to calculate

the area cost of inserting b into (P[i], M[j]).It is obvious that (x(P[i],M[j]), y(P[i],M[j])) are the coordi-

nates of the bottom-left corner of b. These coordinates will beused to estimate the wirelength of nets related to block b (thewirelength calculation model will be discussed in Section V).

Accordingly, the costs of inserting b into (P[i], M[j]) canbe evaluated by the linear combination of the area costs and

the wirelength. We will select top kcip insertion points with thelowest costs as the candidate insertion points of b.

E. Example of Enumerating Insertion Points

Given an SP (P, M) = (f cedba, cbfade), Fig. 5 shows theillustrations of the changing doubly linked lists (for simplicity,

only forward lists are shown) for enumerating insertion points.

In each subfigure, the corresponding distances are also shown.

When visiting a block M[i] in sequence M, we have fourdoubly linked lists. They are scanned simultaneously to enu-

merate the insertion points with positionM[i]

in sequenceM

.

For example, when we visit block c, four lists are shown inFig. 5(e). Assuming that the size of block z to be inserted is(2, 2), we can calculate the chip dimensions after inserting zinto each of the seven insertion points (p, c), where p is anyposition in P. Fig. 5(f) shows the corresponding floorplan illus-tration. Without inserting the block, the chip width is six, and

the chip height is six. If we insert z into (0, c), corresponding toregion r1 in Fig. 5(f), the chip width will be increased to eight,and the chip height will be kept unchanged (6). The other six

insertion points are evaluated as follows.

(f, c) r2, width: six, height: eight;(c, c), (e, c), and (d, c) r3, width: eight, height: six;

(b, c) r4, width: six, height seven;(a, c) r5, width: six, height seven.


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Fig. 5. Enumeration of insertion points. (a) x distance. (b) xr distance. (c) y distance. (d) yr distance. (e) Four doubly linked lists used when visiting c.(f) Floorplan illustration when visiting c.

The insertion points (c, c), (e, c), and (d, c) have the samedistances to all the boundaries: six to the top (yr), zero tothe bottom (y), two to the left (x), and four to the right (xr).They are regarded as equivalent to each other in our evaluation

algorithm, and only one of them is randomly chosen as a

candidate insertion point.

V. WIRELENGTH EVALUATION

During enumerating the insertion points, to avoid a time-

consuming accurate evaluation of wirelength [15], we use a

rough estimation method. Intuitively, given a floorplan and a

block bi to be inserted, to which some blocks in the floorplanhave connections, bi will be forced to a position so that theseconnections are minimized. Consequently, the wirelength eval-

uation is based on the following two simplifications.

1) Consider only the nets that are connected to bi.

2) Use the block positions without actually inserting bi forwirelength evaluation.

With the simplifications, the wirelength can be evaluated for

each insertion point by a piecewise linear function in log(k)time, where k is the number of the nets that have pins on bi.

In Algorithm 3, when scanning the doubly linked lists to

enumerate the insertion points, we can get the coordinates

of bi at any insertion point. Since we just roughly evaluatethe insertion points without really inserting the block, the

coordinates of blocks in the floorplan will be kept unchanged.

Therefore, the only changing coordinates are the coordinates of

bi, which varies at different insertion points. In such a case, the

wirelength of nets related to bi is a piecewise linear function ofthe coordinates ofbi.

Fig. 6. Locations of inflexions.

In the HPWL model, the wirelength in x- and y-directionscan be calculated separately. Here, we take the x-direction asan example to explain the wirelength evaluation method.

For a certain net ntj connected to bi, let BBj be the minimumrectangle (bounding box) enveloping the pins of ntj except

for the pin on bi, and let xjmin and x

jmax be the coordinates

of the left and right boundaries of BBj , respectively. If an

insertion point is inside BBj , i.e., xjmin xbi xjmax, xbi has

no influence on the wirelength of ntj in the x direction since

wirejx = xjmax xjmin. When xbi < xjmin or xbi > xjmax, wirejx

is a linear function of xbi . Hence, wirejx is a piecewise linear

function of xbi , and it is continuous. The two inflexion points

(break points), where the slopes change, are located at x

j

minand xjmax. We know that the sum of piecewise linear functionsis a piecewise linear function. Consequently, we can use a

piecewise linear function to estimate the wirelength of nets

connected bi.Hereafter, we show an example of such a piecewise linear

function. Let lbi be the total wirelength of nets that are con-nected to bi.

Assume that the minimum and maximum (excluding pins on

the removed block) x coordinates of the nets connected to bi arethe following: x1min = 3, x

1max = 13, x

2min = 2, x

2max = 6, and

x3min = 4, x3max = 7, respectively (Fig. 6). The value of lbi is a

piecewise linear function of the x coordinates of bi, as shown

in Fig. 7. For example, if xbi is located in the interval betweenfour and six, lbi = 17.


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Fig. 7. Wirelength estimation.

Such a piecewise linear function can be constructed before

enumerating the insertion points and easily stored in a table

by recording the inflexion points in the ascending order of

coordinates and the corresponding slopes. It will not be changed

during the evaluation of (n + 1)2 insertion points. Given thecoordinates xbi , we can determine the interval in which xbilocates by a binary search in the table and, then, calculate the

wirelength by the corresponding slope and the function value at

the corresponding inflexion.

Let nnt be the total number of nets. Assume that the nets con-nected to bi are ntj , j = 1, . . . , k. In worst case, there are 2 kbreak points in the piecewise linear function, which correspond

to the boundaries ofBBj ,j = 1, . . . , k. The construction of thetable takes O(k(log k)) time, which is the complexity of sortingthe break points. The time complexity of a binary search in the

table is O(log(k)). Consequently, the complexity of estimatingwirelength for all the O(n2) insertion points is O(n2(log k)),assuming that the magnitude of k is at most that of n2. In allthe circuits we used, k is around 20 on average.

VI. COMPLEXITY ANALYSIS

To evaluate an insertion point, a direct method is to insert

the block into the point to generate a new SP. Then, we can

compute the chip area in O(n(log log(n))) time [12] and thewirelength in O(nnt) time, where nnt is the number of nets.The complexity of evaluating total (n + 1)2 insertion points

will be O(n

2

nnt) (assume nnt n) and O(n3

(log log(n)),respectively, with and without considering the wirelength. Inthis paper, given an SP of n blocks and an additional block tobe inserted, we devised an efficient method to enumerate and

evaluate the (n + 1)2 insertion points.If wirelength is not considered, in Algorithm 3, steps 8 and 9

are done in constant time, and step 10 consumes O(n) time inworst case. As a consequence, the complexity of Algorithm 3

is O(n2). Hence, the complexity of the IAR perturbation isO(n2).

Considering wirelength evaluation, step 10 consumes

O(n(log(k))) time, where k is the number of nets connected theblock to be inserted (Section V). Consequently, the complexity

of Algorithm 3 is O(n2 log(k)), assuming that k is not morethan n2.

Accurate evaluation of an insertion point takes O(nnt) time,assuming that nnt n. Let kcip be the candidate insertionpoints that we select during the enumeration. As discussed in

Section III-A, we can randomly choose one or choose the best

one of the kcip insertion points for the block to be inserted. Inthe former case, the evaluation complexity is O(nnt), whereas

in the latter case, the evaluation complexity is O(kcip nnt). Inour experiments, kcip has some value between 2 and 25.

VII. EXPERIMENTAL RESULTS

The proposed method has been implemented in C-language

and run on an IBM workstation (3.2 GHz and 3-GB RAM)

with Linux OS. The MCNC benchmarks (ami33 and ami49)

and GSRC benchmarks (n100, n200, and n300) are used in

the experiments. The wirelength is estimated using the HPWL

model.

A. FOFP

We compared the proposed fixed-outline floorplanner with

the Parquet [15], [11] and the B-tree-based fixed-outline floor-planner [9], [10], [16] (NTU-FOFP) on the same platform. If the

outline of a floorplan is smaller than H0 and W0, its aspect ratiocan be different from that of the fixed outline. Otherwise, the

floorplan fails to meet the outline constraint. The success rate

is defined as the ratio of the number of runs that failed to meet

the fixed-outline constraint to the total run number. We have

tested Parquet 4.5 using SP and B-tree, NTU-FOFP [10], andthe proposed fixed-outline floorplanner (IARFP) under two sit-

uations: with and without HPWL optimization. The maximum

percentage of white space is assumed to be 10%.Without considering the wirelength, we first compared the

success rate and the runtime of IARFP, Parquet 4.5 [11], and

NTU-FOFP. The expected aspect ratios of the floorplans are

chosen from the range [1, 3] with an interval of 0.5. The

results were averaged over 250 runs (50 runs for each aspect

ratio). Table I lists the average success rate of Parquet with

SP, Parquet with B-tree, NTU-FOFP, and IARFP. The averagesuccess rates of Parquet using B-tree and SP are 94.48% and53.6%, respectively.4 NTU-FOFP obtains the highest success

rate 99.92% on average. The average success rate of the pro-

posed method (IARFP) is 98.24%, which is 1.78% lower than

that of NTU-FOFP. The average runtime of IARFP is much lessthan those of Parquet and NTU-FOFP.

For ami33 and ami49, compared with NTU-FOFP (using

B-tree), IARFP gets a lower success rate. There are twopotential reasons for this. One is that the B-tree representationdefines a much smaller solution space for the area optimization,

and its evaluation time complexity is lower compared with SP.

Therefore, B-tree might be more efficient and effective whenwirelength is not taken into consideration. The experimental

results of Parquet also showed this point. The other is that, in

the proposed method, we restrict the candidate insertion points

4

The Parquet with B

-tree outperformed the Parquet with SP, whereas thesituation is reverse if wirelength is also taken into account (see the analysis inTable II).


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TABLE IRESULTS OF FOFP. = 10%, AN D ALL BLOCKS ARE HAR D. THE ASPECT RATIOS ARE CHOSEN FROM THE RANGE [1, 3]

WIT H INTERVAL 0.5. EACH DATUM IS AN AVERAGE OF 250 RUN S (50 RUNS FOR EACH ASPECT RATIO)

TABLE IIRESULTS OF FOFP. = 10%, AN D ALL BLOCKS ARE HAR D. ALL DATA OF AMI33, AM I49, AND N100 ARE AVERAGED

OVER 50 INDEPENDENT RUN S, AND THE DATA OF N200 AND N300 ARE AVERAGED OVE R TEN INDEPENDENT RUN S

within a small range, which might reduce the success rate.

However, in both SP-based floorplanners, the results of IARFP

(using SP) are still better than those of Parquet with SP, which

is even better than those of Parquet with B-tree.IARFP(Greedy) shows the results of IARFP when we select

the best insertion point for the removed block during theenumeration. It is much faster than all the other methods, but the

success rate is a little lower compared with IARFP. In IARFP,

the average iteration (Fig. 1) numbers of test cases are around

19 000 (ami33), 21 500(ami49), 4300 (n100, n200), and 5200

(n300), respectively, whereas in IARFP(Greedy), the iteration

number of all the test cases is 2200.

Second, taking the linear combination of (5) and wirelengthas the objective function, we compared the success rate, the


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HPWL, and the runtime. Table II lists the experimental results

of ami33 (with 123 nets and 42 I/O pins), ami49 (with 408 nets

and 22 I/O pins), n100 (with 885 nets and 334 I/O pins), n200

(with 1585 nets and 564 I/O pins), and n300 (with 1893 nets

and 569 I/O pins). In Parquet and NTU-FOFP, the I/O pads for

all circuits are fixed at the given coordinates in the benchmark.

For fair comparison, we deal with I/O pins in the same way.The floorplan expected ratios are chosen from the range [1, 3]

with an interval of 0.5. The results of ami33, ami49, and n100

are averaged on 50 runs for each aspect ratio. The results of

n200 and n300 are the average of ten runs. In Parquet and

NTU-FOFP, we set new area or wire weights to ensure a little

higher success rate. When running NTU-FOFP, the area weight

is chosen between 0.99 and 0.99999 (default 0.9), and other

parameters are default. In Parquet using SP, we set the wire

weights by the values between 0.05 and 0.4 (default 0.4). It

has been shown in [15] that Parquet using SP did better than

Parquet using B-tree when considering the wire optimization.We also made experiments and found that Parquet using B-treetook less time but much lower success rate and larger HPWL.

Consequently, we compare with Parquet using SP.

From the experiments on GSRC benchmarks, we observed

that IARFP reached 100% success rate for all aspect ra-

tios, whereas NTU-FOFP and Parquet with SP got 57.3%,

and 28.67%, respectively, on average. IARFP, respectively,

achieved 25.12% and 17.16% improvement in wirelength com-

pared with Parquet with SP and NTU-FOFP. IARFP is also

much faster than other two floorplanners.5 The total iteration

numbers in each run are n100: 4700, n200: 7000, and n300:

9400, respectively. In Parquet and NTU-FOFP, we have to set

large area weights or small wire weight to ensure a success rate.

It is, hence, difficult to get a good wirelength. As for MCNCbenchmarks, NTU-FOFP outperformed IARFP in ami33. On

average, the IARFP got the highest average success rate 85.5%,

whereas those of NTU-FOFP and Parquet are 82% and 34%,

respectively. The total comparison data are shown in Table II.

The aforementioned results demonstrated the effectiveness

and efficiency of the proposed FOFP method.

B. Adaptability of the Proposed Function

To show the adaptability of the proposed method for calcu-

lating the area costs, the objective function defined in (5) for

FOFP is embedded into NTU-FOFP.We ran the NTU-FOFP using (5) to calculate the area costs

instead of the original one. The test cases n100, n200, and n300

are used for experiments.

Table III listed the experimental results when the fixed-

outline constraint is the only consideration. We can see that both

methods got almost 100% success rate.

In Fig. 8, we show the results of experiments on test case

n100, taking into account the wirelength. Each data point is an

average of 50 independent experiments. In similar runtime, the

5In [6](Capo), theperformanceand theruntime of Parquet were improved byincorporating min-cut partitioning into floorplanning, and in [17], the multilevel

strategy was incorporated into the B

-tree-based floorplanning. In this paper,since we focus on flat-style fixed-outline floorplanning, no comparison is madewith these two methods.

TABLE IIIRESULTS OF FOFP. = 10%, AN D ALL BLOCKS ARE HAR D. THE ASPECT

RATIOS ARE CHOSEN FROM THE RANGE [1, 3] WITH INTERVAL 0.5

Fig. 8. Using the proposed objective function in NTU-FOFP. : IARFP;: NTU-FOFP; : NTU-FOFP using (5). (a) Success rate. (b) Wirelength.(c) Time.

proposed function got 58% improvement on the success rate

while wirelength is comparable. The subfigures of Fig. 8 show

the comparison of success rate, wire, and runtime, respectively.

In the figure, we also show the results of IARFP.

The experimental results showed that the proposed functionis effective when embedded into the NTU-FOFP.


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Fig. 9. Aspect ratio versus the ratio of wirex to wirey .

C. Aspect Ratio and Wirelength

We devised three groups of experiments on test cases n100a

using the following three objective functions.

1) The linear combination of (5) and wirelength. In (5),

the weight of area costs will increase as the aspect ratioincreases.

2) Linear combination of (6) and wirelength. In (6), the

weight of area costs will remain similar for all the aspect

ratios.

3) Equation (5) only.

In the following figures and analysis, we use series-1

(area+wire), series-2 (area+wire), and series-3 (area), respec-

tively, to refer to the experimental results using the afore-

mentioned three objective functions. In series-1 and series-2,

= 10%, and the objective functions are a linear combinationof area costs and wire. Series-3 will be discussed in the next

section. All the data points are based on 50 independent runs.The runtime is not shown since we use the same simulated

annealing parameters for all experiments and the runtime of

each experiment is close to that shown in Table II. In order to

track the changes of wirelength, the I/O pins are scaled on the

chip boundaries.

Fig. 9 shows the ratio of wirex to wirey. As the aspect ratio

grows, the ratio also increases. Fig. 10 shows the geometric

means of wirex and wirey (Section III-C), which show the

change of the product of wirex and wirey . In series-1 and

series-2, the products vary slightly (Fig. 11 shows these values

with a smaller scale) under various aspect ratios compared with

the change of wirex, wirey , and the total wirelength (HPWL, thesum of wirex and wirey). The sum of wirex and wirey increases

with the increment of the aspect ratio. These are consistent

with the simple geometric observation in Section III-C. Larger

aspect ratio causes larger wirelength.

In Fig. 9, we can see that series-2 has a little smaller slope.

The ratios in series-2 are smaller and so is the wirelength

(Fig. 10). The success rates in series-2, however, lowered

greatly with the increase of the aspect ratio (Fig. 12). This is

because in series-2, width and height are scaled (6) according

to the aspect ratios, and hence, for all the aspect ratios, the

area costs will remain similar, whereas the wirelength will

increase as the aspect ratio increases. The wirelength gets more

competitive as the aspect ratio increases in series-2. Hence, wehave to enlarge the weight of area costs for larger aspect ratios

Fig. 10. Aspect ratio () and wirelength (: series-1; : series-2). Along thedirection of wire HPWL increasing, the four pairs of lines are wirey , geometric

mean of wirex and wirey , wirex, total wirelength, respectively.

Fig. 11. Aspect ratio () versus the geometric mean of wirex and wirey .

Fig. 12. Success rate versus aspect ratio (with HPWL optimization).

to conquer the outline constraint as (5) does. Equation (5) is

much more effective than (6) under fixed-outline constraints

when the aspect ratios are far from one.

According to our statistics, 99.4% of the experiments that

failed to meet the fixed-outline constraint (in series-2, totally

450 runs, 150 runs fail to meet the fixed-outline) violated

the height constraint H0 (note that, in our case, since > 1,

height is shorter). In some sense, it also demonstrates that thewirelength keeps increasing as the aspect ratio increases. In


14/14


Fig. 13. Success rate versus aspect ratio.

other words, the wirelength optimization causes smaller aspect

ratios. Therefore, the smaller of outline height and outline width

is violated more frequently. Consequently, we have to raise the

area weight to ensure a feasible solution under a fixed-outline

constraint as the aspect ratio increases.

D. Aspect Ratio and Success Rate

In series-3, the objective is only area. Fig. 13 shows the

change of the success rate on the aspect ratio. The success

rate seems not to lower with increased aspect ratio. However,

based on our statistics, 95% of the runs that failed to meet the

fixed-outline violated the outline height constraint (of totally

450 runs, 21 failed to meet the outline constraint, and 5%

violated the outline width constraint) if = 8%. This percentis 84% if = 6% (of totally 450 runs, 339 failed to meetthe outline constraint, and 42% violated the outline width

constraint).

VIII. CONCLUSION

In this paper, we proposed an FOFP method (IARFP). An

elaborated method for perturbing solutions, the IAR, was de-

vised for the simulated annealing. The IAR operation was

devised based on the technique of enumerating block positions

in SP and accelerated the searching greatly. Moreover, based on

the analysis of diverse objective functions used in the existing

methods, we suggested a new objective function for floor-

planning with a fixed-outline constraint. Experimental results

showed the efficiency and effectiveness of the proposed methodfor FOFP with various aspect ratios. Additionally, the proposed

method can be combined with multilevel hierarchical strategy

to further improve scalability. Related research is ongoing.

REFERENCES

[1] S. N. Adya and I. L. Markov, Fixed-outline floorplanning: Enablinghierarchical design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. ,vol. 11, no. 6, pp. 11201135, Dec. 2003.

[2] A. B. Kahng, Classical floorplanning harmful, in Proc. ACM ISPD,2000, pp. 207213.

[3] S. N. Adya and I. L. Markov, Fixed-outline floorplanning through betterlocal search, in Proc. ICCD, 2001, pp. 328334.

[4] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, VLSI module

placement based on rectangle-packing by sequence-pair, IEEE Trans.Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 12, pp. 15181524, Dec. 1996.

[5] S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov, Uni-fication of partitioning, floorplanning and placement, in Proc. ICCAD,2004, pp. 550557.

[6] S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov, Min-cut floorplacement, IEEE Trans. Comput.-Aided Design Integr. CircuitsSyst., vol. 25, no. 7, pp. 13131326, Jul. 2006.

[7] R. Liu, S. Dong, X. Hong, and Y. Kajitani, Fixed-outline floorplanningwith constraints through instance augmentation, in Proc. IEEE ISCAS,

2005, pp. 18831886.[8] C. T. Lin, D. S. Chen, and Y. W. Wang, Robust fixed-outline floorplan-ning through evolutionary search, in Proc. IEEE/ACM ASP-DAC, 2004,pp. 4244.

[9] T. C. Chen and Y. W. Chang, Modern floorplanning based on fast simu-lated annealing, in Proc. ACM ISPD, 2005, pp. 104112.

[10] T. C. Chen and Y. W. Chang, Modern floorplanning based on b-treeand fast simulated annealing, IEEE Trans. Comput.-Aided Design Integr.Circuits Syst., vol. 25, no. 4, pp. 637650, Apr. 2006.

[11] S. N. Adya, H. H. Chan, and I. L. Markov, Parquet 4.5: Fixed-Outlinefloorplanner. [Online]. Available: http://vlsicad.eecs.umich.edu/BK/parquet/

[12] X. Tang, R. Tian, and D. F. Wong, Fast evaluation of sequence pair inblock placement by longest common subsequence computation, IEEETrans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 12,pp. 14061413, Dec. 2001.

[13] P. N. Guo, T. Takahashi, C. K. Cheng, and T. Yoshimura, Floorplanning

using a tree representation, IEEE Trans. Comput.-Aided Design Integr.Circuits Syst., vol. 20, no. 2, pp. 281289, Feb. 2001.

[14] A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky,On wirelength estimations for row-based placement, IEEE Trans.Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 9, pp. 12651278, Sep. 1999.

[15] H. H. Chan, S. N. Adya, and I. L. Markov, Are floorplan representationsimportant in digital design, in Proc. ACM ISPD, 2005, pp. 129136.

[16] T. C. Chen and Y. W. Chang, B-tree based floorplanner. [Online].Available: http://eda.ee.ntu.edu.tw/research.htm

[17] T. C. Chen and Y. W. Chang, IMF: Interconnect-driven multilevel floor-planning for large-scale building-module designs, in Proc. ICCAD, 2005,pp. 159164.

Song Chen received the B.S. degree in computer sci-

ence from Xian Jiaotong University, Xian, China,in 2000, and the M.S. and Ph.D. degrees in computerscience from Tsinghua University, Beijing, China, in2003 and 2005, respectively.

He is currently a Visiting Research Associate withthe Graduate School of Information, Production andSystems, Waseda University, Kitakyushu, Japan. Hisresearch interests include several aspects of elec-tronic design automation, e.g., floorplanning, place-ment, and high-level synthesis.

Takeshi Yoshimura (M86) received the B.E., M.E.,and Dr.Eng. degrees from Osaka University, Osaka,Japan, in 1972, 1974, and 1997, respectively.

He was with the NEC Corporation, Tokyo, Japan,in 1974, where he was engaged in the research anddevelopment of computer application systems forcommunication network design, hydraulic networkdesign, and Very Large Scale Integration (VLSI)computer-aided design (CAD). From 1979 to 1980,he was on leave at the Electronics Research Lab-oratory, University of California, Berkeley, where

he worked on the VLSI CAD. Since April 2003, he has been with theGraduate School of Information, Production and Systems, Waseda University,Kitakyushu, Japan.

Dr. Yoshimura is a Fellow of the Institute of Electronics, Information, and

Communication Engineers of Japan (IEICE) and a member of the InformationProcessing Society of Japan. He received Best Paper Awards from the IEICEand the IEEE Circuits and Systems Society.

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Fixed Outline Floorplan

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