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Page 1: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz
Page 2: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

FPGA Co-Processing for DSPFPGA Co-Processing for DSP

Page 3: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

AgendaAgendaApplications of FPGA-Based Co-Processors for DSPDevelopment Tools & Methodologies Available from Altera to Build Co-Processors− SOPC Builder− DSP Builder

FPGA Co-Processor Development Examples− QAM Modulator− FIR Filter

Page 4: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Growing Demand for MIPS &Memory BandwidthGrowing Demand for MIPS &Memory Bandwidth

Growth Drivers− Algorithm Complexity− Security− Multiple Users

Dig

ital S

igna

l Pr

oces

sing

(DSP

) MIP

S &

Mem

ory

Ban

dwid

th

Time

Digital SignalProcessors

ApplicationRequirements

Page 5: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Dedicated Hardware Architecture

DSP System Architecture OptionsDSP System Architecture OptionsPe

rfor

man

ce (M

AC

s/Se

c)

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

Processor ArrayStand-Alone Processor

DSP

Processor + Co-Processor

DSP

Page 6: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Exploring the DSP Design SpaceExploring the DSP Design Space

Digital SignalProcessor

Farm

Digital SignalProcessor

with Co-Processor

ConventionalProcessor

AlteraFPGA

Co-Processor

AlteraFPGA with

Nios & Co-Processor

Digital SignalProcessor

AlteraFPGA

Co-Processor

AlteraFPGA

Algorithmin Hardware

The Flexibility Zone

CustomASIC

Perf

orm

ance

Digital SignalProcessor Conventional

Processor

Flexibility

Page 7: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Co-Processing on FPGAsCo-Processing on FPGAs

FIRFIR

NCO

IQMap

Processor External to FPGAProcessor External to FPGAProcessor on FPGAProcessor on FPGA

MemoryMemory

FPGAFPGA

MemoryMemoryNCO

FPGA

IQMap

MemoryMemory

ProcessorProcessor

Page 8: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Off-Loading Algorithms to Co-Processor Reduces Number or Cost of Digital Signal Processors

Applications− Algorithms with Large Amount of Digital Signal Processing &

Small Amount of Control Processing

When Do FPGA Co-Processors Reduce System Cost?When Do FPGA Co-Processors Reduce System Cost?

Expensive Array to DSP + FPGA

Expensive DSP to Inexpensive DSP + FPGA

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

FIR

NCO

IQMap

MemoryMemory

DSP

MemoryMemory

DSP$$$

Page 9: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

FPGA Co-Processor ApplicationsFPGA Co-Processor ApplicationsWireless − 2.5-G EDGE Equalization− 3-G Baseband Processing

HSDPA1xEVDV

− 3-G RF Linearization

Consumer − Broadcast - Studio & Cable

Plant − Digital Entertainment –

MPEG2 & MPEG4

Medical − Imaging

Wireline Communications − Encryption− Framer− Traffic Management− TCP/IP

Computer & Storage − Data Analysis & Routing

Engine − Digital Imaging

Military & AerospaceSecurity

Page 10: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

DSP Development Tools & Design Methodology

DSP Development Tools & Design Methodology

Page 11: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

FPGA Co-Processor Design ToolsFPGA Co-Processor Design Tools

Dedicated Hardware Architecture

Stand-Alone Processor

Processor + Co-Processor

DSP BuilderDSP BuilderSOPC BuilderSOPC Builder

Page 12: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

CreatesHDL Code

DSP BuilderDownloadDesign to

DevelopmentBoard

CreatesSimulation Test Bench

Verifyin

Hardware

CreatesProcessor

Plug-In

HDLSynthesis

DSP Builder OverviewDSP Builder Overview

Page 13: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

DSP Builder Library ComponentsDSP Builder Library ComponentsArithmeticBus ManipulationComplex Signals Logical ComponentsSOPC PortsStorageMegaCore® IPRate ChangeState MachineAltera LibraryDSP Board

Page 14: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

MegaCore IP in DSP BuilderMegaCore IP in DSP Builder

DSP Builder MegaCore® Functions

• FIR• FFT• Viterbi• Turbo• Reed Solomon• NCO

DSP Builder MegaCore® Functions

• FIR• FFT• Viterbi• Turbo• Reed Solomon• NCO

Page 15: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

DSP Builder Support for Multiple Clock DomainsDSP Builder Support for Multiple Clock Domains

Inherit Sampling Frequency (FS)Adhere to Clock Design RulesAll Sample Times Match One of Phase-Locked Loops (PLLs) Output Clock PeriodsSimplify Analysis & Implementation ofMulti-Rate System− Up Sampling− Down Sampling

Page 16: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

State Machine BuilderState Machine Builder

Page 17: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Sub-System BuilderSub-System BuilderImport Existing VHDL Design into SimulinkSimulink Simulation Options− Convert into DSP Builder Blocks or MATLAB Functions− Treat VHDL Design as Black Box

Page 18: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Signal CompilerSignal CompilerGenerates VHDL Design FilesGenerates Tool Command Language(Tcl) Scripts

Generates TestbenchEnables Parameterizationof IP BlocksLaunch HardwareCompilation fromSimulink Cockpit

Page 19: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Stratix DSP Development BoardStratix DSP Development Board

Altera® Nios®

ExpansionPrototypeConnector

80-Pin I/O Connector

14-Bit, 165-MHz D/A

PrototypingArea

12-Bit, 125-MHz A/D Push-Button

SwitchesSMAConnector

9-Pin RS232Connector5-V Power

Supply

Texas Instruments Connectors CanBe Found on Underside of Board

40-Pin Connector for AnalogDevices Evaluation Boards

LEDs

Page 20: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Altera DSP Development Kits Altera DSP Development Kits Contains Everything You Need

to Develop High-Performance DSP Designs on FPGAs

30-Day EvaluationVersion

System ReferenceDesigns

Page 21: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

QAM Modulator Co-Processor Design Example

QAM Modulator Co-Processor Design Example

Page 22: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Modem Reference DesignModem Reference DesignInstalled with Code Composer Studio As a Tutorial− C:\ti\tutorial\dsk6711\modem

Used to DemonstrateCCS Functionality16 QAM TX Modem

Page 23: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Modem Design Code ProfileModem Design Code Profile

Page 24: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Modem Design Hardware/ Software Petition

Main100%

Initialize3%

Add Noise Signal0.5%

Shaping Filter 82%

Modulation 8%

Sine Lookup 2.5%

Cosine Lookup 2.5%

HardwareAccelerator

Modem Design Hardware/ Software Petition

Modem Transmitter

96.5%

Page 25: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Modulator Co-ProcessorModulator Co-ProcessorDSP Builder Used to Build Hardware DSP Data Path

Page 26: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Avalon™ Interface in SOPC BuilderAvalon™ Interface in SOPC Builder

Page 27: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Import DSP Builder Generated Co-Processorinto SOPC Builder

DSP Builder— SOPC Builder ImportDSP Builder— SOPC Builder Import

Page 28: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

SOPC Builder IntegrationSOPC Builder IntegrationModem Co-Processor (fir_comp)

Integrated with TI EMIF I/F (TIMaster)

Page 29: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

FIR Filter Co-Processor Design ExampleFIR Filter Co-Processor Design Example

Page 30: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Driving Down System CostsDriving Down System Costs

Digital Signal Processor + FPGA Co-Processor

Digital Signal Processor + FPGA Co-Processor

Multi-ProcessingDSP

DSP DSPDSP DSPDSP DSPDSP DSP

FPGA

DSPMemoryMemory

FPGA

FIRFIR

Page 31: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

FIR Co-Processor Design ExampleFIR Co-Processor Design Example

FIR Parameters− 128-Tap− 16-Bit Data, 14-Bit Coefficients

Four FIR Implementations for Comparison− TI C6711-Optimized TI DSPLib Function− TI C6416-Optimized TI DSPLib Function− Altera Eight-Cycle FIR Co-Processor− Altera One-Cycle FIR Co-Processor

Page 32: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

TI Filtering Library (DSP Lib)TI Filtering Library (DSP Lib)C-Callable Optimized Assembly RoutinesTI C67x DSPLib: Fir Filter (Radix 8)− Formula: Nh * Nr /2 + 13

Nh = Number of CoefficientsNr = Number of Samples

− ~1 Sample/ 64 Cycles (128 Tap Filter)TI C64x DSPLib: FIR Filter (Radix 8)− Formula: Nh * Nr/4 + 17− ~ 1 Sample/ 32 Cycles (128 Tap Filter)

Page 33: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Filter Co-Processor Design ExampleFilter Co-Processor Design Example

Current Implementation− 100 MHz, 32-Bit, Asynchronous EMIF on DSK− TI Writes 300 Samples to Co-Processor (Input Data)− Filter & Send Output to TI

C6000 Digital Signal Processor

External M

emory I/F

FPGA Co-Processor

TI I/F Core

QD

MA

Input FIFO

FIR

Com

piler

Page 34: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

FIR Filter Example* – 16X Cost/Performance ImprovementFIR Filter Example* – 16X Cost/Performance Improvement

1-Cycle***at 170 MHz

7-Cycles***at 200 MHz

32-Cycles**at 600 MHz

64-Cycles**at 200 MHz

Solution

$84

$14

$160

$24.59

DeviceCost****

170

28

18.75

3.125

FIR Performance(MHz)

Altera EP1C12-8

Altera EP1C3-8

TI C6416-600

TI C6713-200

Device

$0.50

$0.49

$8.53

$7.87

Cost perFIR MHz

* FIR 128 Tap, 16-Bit Data, 14-Bit Coefficients** DSPLib Optimized Assembly Libraries from Texas Instruments*** Optimized MegaCore FIR Compiler from Altera**** Pricing in Quantity of 100 at Arrow 6/25/03

* FIR 128 Tap, 16-Bit Data, 14-Bit Coefficients** DSPLib Optimized Assembly Libraries from Texas Instruments*** Optimized MegaCore FIR Compiler from Altera**** Pricing in Quantity of 100 at Arrow 6/25/03

Page 35: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

14X Reduction in System Costs14X Reduction in System Costs

DSP DSPDSP DSPDSP DSPDSP DSP

FPGA

DSPMemoryMemory

FPGA

FIRFIR

173

167

Total FIR Performance

(MHz)

$84 + $25

9 * $160

Device Costs

$110

$1,440

Total Cost

170 + 3

9 * 18.75

FIR Performance

(MHz)

Altera EP1C12-8 + 1 TI c6713-200

9 * TI C6416-600

Architecture

Page 36: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

SummarySummaryFPGA Co-Processors for DSP Offer Many Advantages− 10X Performance Boost

More ChannelsMore Complex AlgorithmsIncreased System Throughput

− 10X Cost Reduction Fewer Components

− Complementary to DSP-Based SystemsOffloads Existing DSPIntegrates Into Existing DSP IDEEvolution Not Revolution

Page 37: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

Altera Code: DSP SolutionsAltera Code: DSP SolutionsFPGAs− Stratix, Stratix GX, Cyclone

Development Tools− DSP Builder, SOPC Builder

Intellectual Property− FIR, FFT, Viterbi, Turbo, Reed Solomon, NCO− AMPP Third-Party Partners

Development Kits− Altera− Third-Parties

Design Services− ACAP Third-Party Partners

Training

Page 38: FPGA Co-Processing for DSP · 2003-12-13 · Generates VHDL Design Files ... FIR Filter Example* – 16X Cost/Performance Improvement 1-Cycle*** at 170 MHz 7-Cycles*** at 200 MHz

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