2 TM
1990 2020 2010 2000
1T
100B
10B
1B
10M
Computers People Everything
$100
Past Today Future
$1
1¢
50B Connected Nodes by 2020*
Cloud Wireless Enterprise
Factory
Automation
Smart
Energy Transportation
1.0 2.0 3.0
2
1 2 3
1 3
*Source Ericsson
3 TM
Hardware
Development Tools
Software
Development Tools
Application Stacks
Middleware
Scalable SOC
Customer Differentiation
Operating
Systems
SDOS
Application Software
Reference Solutions
Middleware
Commercial OS
Embedded
Board
Solutions
Silicon
Processor
Expert
Clo
se
r to
Cu
sto
me
r S
olu
tio
n
4 TM
Accelerate Integrate Innovate
• Scalable Roadmap
• Datapath Acceleration
• 64-bit Processing
• Core Agnostic
• Software Enabled
• Best Price/Performance/
per Watt
• I/O Flexibility
• Integrated Switch
• Altivec Processing
• Time-to-Market Advantage
• Software Development Kits
• Turn-Key Reference
Solutions
• Embedded Board Solutions
• Third Party Ecosystem
• Full Development
Environment
5 TM
Target Applications Portfolio Product Overview
1-6 heterogeneous
cores
5 family members in 2013
1-8 cores, data path acceleration , security and
pattern matching, hardware-assisted hypervisor
25 family members
in production
General purpose MPU
75 family members
in production
1-24 cores, 64-bit,
AltiVec technology
6 family members in 2013
Core-agnostic approach
to hardware
Freescale’s unrivaled networking
expertise with Arm’s expansive
ecosystem
QorIQ
T Series
QorIQ
Qonverge
Platform
QorIQ
P Series
QorIQ
LS Series
PowerQUICC
•Networking
•Aerospace and
Defense
•Factory Automation
•Aerospace and Defense
• Industrial
•Wireless Access
•Networking
• Industrial Automation
•Smart Grid
•Data Center
•Aerospace and
Defense
•High-End Networking
• Industrial
•Smart Grid
•Networking
6 TM
2012 2013 2Q 3Q 4Q Existing 1Q 4Q
P3041
P2041/40
P1023/17
P1010/14
T4160
T4240
P1021/12
P1022/13
P2020/10
MPC8569
P4080/40
P5040
P5020/10
P5021
P1020//11
2014 2Q 3Q 4Q 1Q 2Q 1Q
LS1xxx
T1040/42
T2080
T2081
T1020/22
SDK 1.6 SDK 1.7 SDK 1.5 SDK 1.4 SDKs
SDK 1.3 Biannual
releases
LS1 Family
Next generation
Production Proposal Planning Execution
High Performance
Mid Performance
Value Performance
LS3xxx
LS2xxx
Sample
Production
8 TM
P1010 P1014
P1024, P1015
P1025, P1016
P1020, P1011
P1021, P1012
P2020
P2010
P1022
P1013
P1023
P1017
CPU
e500v2 e500v2 1 to 2 e500v2 1 to 2 e500v2 1 to 2 e500v2 1 to 2 e500v2 1 to 2 e500v2
Up to 800 MHz Up to 800 MHz Up to 667 MHz Up to 800 MHz Up to 1200 MHz Up to 1200 MHz Up to 800 MHz
32K I/D 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D
L2 Cache 256 KB 256 KB 256 KB 256 KB 512 KB 256 KB 256 KB
DDR I/F
Type/Width
DDR3/3L DDR3/3L DDR3 DDR2/3 DDR2/3 DDR2/3 DDR3/3L
32/16-bit 16-bit 32-bit 32-bit 32/64-bit 32/64-bit 32-bit
10/100/1000
Ethernet (with
IEEE 1588v2) 3 w/(2) SGMII 2 w/(2) SGMII 3 w/(2) SGMII 3 w/(2) SGMII 3 w/(2) SGMII 2 w/(2) SGMII 2 w/(2) SGMII
TDM Yes Yes Yes Yes - Yes -
ATM UTOPIA - - In P1025/16 In P1021/12 - - -
SERDES 6 lanes 4 lanes 4 lanes 4 lanes 4 lanes 6 lanes 4 lanes
PCI-Exp 1.0a 2 controllers 2 controllers 2 controllers 2 controllers 3 controllers 3 controllers 3 controllers
sRIO 1.2 - - - - 2 controllers - -
SATA
2 controllers 2 controllers
- - -
2 controllers
- 1.5 or 3 Gbaud
1.5 or
3 Gbaud 1.5 or 3 Gbaud
USB2.0 1 w/ PHY 1 w/ PHY 2 2 1 2 1
Memory Card SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC -
Other Interfaces SPI, 2xI2C,
DUART, 2xeCAN
SPI, 2xI2C,
DUART
SPI,
2xI2C, DUART
SPI,
2xI2C, DUART
SPI, 2xI2C,
DUART
SPI,
2xI2C, DUART
SPI,
2xI2C, DUART
Accelerators SEC4.0 w/
trusted boot SEC4.0 SEC3.3 SEC3.3 SEC3.1 SEC3.2
DPAA,
SEC 4.2
Package
425 TePBGA
19x19mm 0.8mm
561 TePBGA
23x23mm, 0.8mm
689 TePBGAII
31x31mm
689 TePBGAII
31x31mm
457 TePBGA
19x19mm, 0.8mm
Pin-compatible Pin-compatible Pin-compatible Pin-compatible Pin-compatible Audio I2S Audio
Video LCD (DIU)
RAID XOR
9 TM
P5040/P5021 P5020/P5010 P4080 P4040 P2040 P3041
CPU
Quad and Dual e5500
to 2200 MHz
Dual and Single
e5500 to 2000 MHz
Octal core e500MC to
1500 MHz
Quad core e500MC
to 1500 MHz
Quad e500MC to
1200 MHz
Quad e500MC to
1500 MHz
Cache
L1: 32K I/D
L2: 512 KB BS
L3: 2MB FS
L1: 32K I/D
L2: 512 KB BS
L3: 1MB
L1: 32K I/D
L2: 128 KB BS
L3: 2 MB -FS
L1: 32K I/D
L2: 128 KB BS L3: 2
MB -FS
L1: 32K I/D
CoreNet Cache: 1
MB -FS
L1: 32K I/D
L2: 128 KB BS
L3: 1 MB -FS
10/100/1000
Ethernet (with
IEEE®1588v2) 10x GbE, 2 10 GbE 5x GbE, 1 10 GbE
(2) Frame managers w/
4 x1 GbE (SGMII) & 1
10 GbE (XAUI)
(2) Frame managers
w/ 4 x 1 GbE (SGMII)
& 1 10 GbE (XAUI) 5x GbE
4x GbE, 1
10 GbE
PCI-Exp X3 gen 2.0 x4 gen 2.0 X3 gen 2.0 X3 gen 2.0 X3 gen 2.0 X3 gen 2.0
sRIO 2 2 2 2 2
USB 2.0 2 2 2 2 2 with PHY -
SerDes
20 lanes
@ 5 GHz
18 lanes
@ 5 GHz
18 lanes
@ 5 GHz
18 lanes
@ 5 GHz
10 lanes
@ 5 GHz
12 lanes
@ 5 GHz
Memory
DUAL
DDR3/3L to 1.6 GHz DDR2/3 to 1.3 GHz
DUAL
DDR2/3 to 1.3 GHz
DUAL
DDR2/3 to 1.3 GHz
DDR2/3 to 1.067
GHz
DDR2/3 to 1.3
GHz
Other interfaces
SPI, 4x I2C, 2x
DUART, CoreNet
SATA
SPI, 2xI2C, 2x
DUART, CoreNet
SATA
SPI, 4x I2C, 4x UART,
CoreNet
SPI, 4x I2C, 4x
UART, CoreNet
SPI, 2xI2C, 4x
UART, CoreNet,
SATA
SPI, 2xI2C, 4x
UART, CoreNet,
SATA
Accelerators
Data path: SEC 5.2,
RAID 5/6
Data path: SEC 4.0,
RAID 5/6, PME
Data path: SEC 4.0, 10
Gbps IP forwarding,
PME
Data path: SEC 4.0,
10 Gbps IP
forwarding, PME
Data path: SEC 4.0,
5 Gbps IP
forwarding, PME
Data path: SEC
4.0, 5 Gbps IP
forwarding, PME
Package 1295-pin package 1295-pin package 1295 FCPBGA 1295 FCPBGA 783-pin package
1295 FCPBGA
(pin compatible
P4040)
10 TM
P1020, P1011 P1021, P1012
P2020 P2010 T1020 T1022 T1040 T1042
CPU
1 to 2 e500 1 to 2 e500 2 e5500 2 e5500 4 e5500 4 e5500
Up to 800MHz Up to
1200MHz 800-1400MHz 800-1400MHz 800-1400MHz 800-1400MHz
32K I/D 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D
L2 Cache 256KB 512KB 256KB/Core 256KB/Core 256KB/Core 256KB/Core
Platform Cache 256KB 256KB 256KB 256KB
DDR I/F Type/Width
DDR2/3 DDR2/3 DDR3L/4 DDR3L/4 DDR3L/4 DDR3L/4
16/32-bit , 800MHz
32/64-bit, 800MHz 32/64-bit, 1333MHz 32/64-bit, 1333MHz 32/64-bit, 1333MHz 32/64-bit, 1333MHz
10/100/1000 Ethernet (with IEEE1588v2) 3 x 10/100/1000
3 x 10/100/1000
8-Port GE Switch & 3 x 10/100/1000 4 x 10/100/1000
8-Port GE Switch & 3 x 10/100/1000 5 x 10/100/1000
TDM Yes - Yes Yes Yes Yes
QUICC Engine In P1021/12 - TDM and HDLC TDM and HDLC TDM and HDLC TDM and HDLC
SERDES 4 lanes 4 lanes 8 lanes 8 lanes 8 lanes 8 lanes
PCI-Exp 2 (Gen-1) 3 (Gen-1) 4 (Gen-2) 4 (Gen-2) 4 (Gen-2) 4 (Gen-2)
DIU - - Yes Yes Yes Yes
SATA - -
2 controller 2 controller 2 controller 2 controller
1.5 or 3Gbaud 1.5 or 3Gbaud 1.5 or 3Gbaud 1.5 or 3Gbaud
USB2.0 2 1 2 with PHY 2 with PHY 2 with PHY 2 with PHY
Memory Card SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC
Accelerators
SEC3.3 SEC3.1
DPAA, PME SEC5.x with Trust
Architecture
DPAA, PME SEC5.x with Trust
Architecture
DPAA, PME SEC5.x with Trust
Architecture
DPAA, PME SEC5.x with Trust
Architecture
Power Management <5.0W <8.0W
Packet Lossles Deepsleep
Packet Lossles Deepsleep
Packet Lossles Deepsleep
Packet Lossles Deepsleep
Package Pin Compatible
11 TM
P4080 T4160 T4240
Physical Cores 8 8 12
Threads/virtual core 8 16 24
Max Core Freq (MHz) 1500 1800 1800
SoC DMIPS 30K 73K 117K
Vector Engine AltiVec Engine AltiVec Engine
L2 Cache 128 KB/core 2M/cluster
2x cluster
2M/cluster
3x cluster
Corenet Platform Cache 2 MB 2x 512 KB 3x 512 KB
Main Memory
Type/Speed
DDR2 / DDR3 to
1333 MT/s
DDR3 and DDR3L to
1867 MT/s
DDR3 and DDR3L to
1867 MT/s
Main Memory Dual x72-bit Dual x72-bit Triple x72-bit
Ethernet 2x XAUI + 8x SGMII 2 x XFI/XAUI + 12x GE 4 x XFI + 16x GE
HiGig Yes Yes
SerDes lanes/max
frequency 18 Lanes; 5 GHz 24 Lanes; to 10 GHz 32 Lanes; to 10 GHz
Serial RapidIO® Dual Dual (+RMAN) Dual (+RMAN)
PCI Express® 3x Gen 2 3x Gen 2/3 + SRIOV 4x Gen 2/3 + SRIOV
SATA Dual Dual
Acceleration Engines SEC, PME SEC, PME, DCE, Prefetch SEC, PME, DCE, Prefetch
13 TM
• First 64-bit embedded processor with an integrated GbE switch
− Reduces system cost, design complexity and power
• One of the industry’s most scalable, pin-compatible family of devices
− Performance scalability with a common architecture
• Energy efficiency and low power
− Designed to be compliant to European Code of Conduct, and EnergyStar energy consumption standards
• Ideal for low- to mid-range networking and industrial connectivity applications
QorIQ Processors:
Accelerating the
Network’s IQ
14 TM
Perf
orm
ance
Power
T2081
NEW
- Dual-Core up to 1.4GHz T1020
NEW
T1022
NEW
T1042
T1040
NEW
- Dual-Core up to 1.4GHz
- Integrated GbE Switch
- Quad-Core up to 1.4GHz
- Quad-Core up to 1.4GHz
- Integrated GbE Switch
- Eight Virtual Cores up to 1.8GHz
Scale from dual, quad to
eight virtual cores with
QorIQ T1/T2 devices
15 TM
New
• 64-bit architecture
• AltiVec Technology: 240 GFLOPS
• 1TB physical address
• Accelerate Hypervisor performance with LRAT
• New process and e6500 core allowing increased frequency
• Dual Thread
• Each with separate front end, branch unit and LSU
• Larger amount of onboard cache per core
• Up to 24 virtual cores
• Large 2 MB shared L2 cache within a cluster of 1 to 4 cores
• CoreNet Cache-coherent fabric with multiple clusters to scale from 1 to 8 clusters
• Virtualization
Up to 4x Performance Improvement
over Previous Generation
IPC
Improvements Multithreading
Frequency
Improvements Multicore
2.4x 1.3x 1.5x
Frequency Dual thread Efficiency
Number of Cores
Improvement of DMIPs per Thread X X X
16 TM
• Highest performance CPU cores within a power envelope
• Advanced integration with multilayer Gigabit Ethernet switch to reduce system cost and design complexity
• Offload engines – encryption/decryption for high performance security
• Deep packet inspection offload engine enabling UTM services
• Data path acceleration architecture (DPAA) – for QoS and balanced networking performance
• Virtualization to support customers and 3rd party software
• Small form factor, fanless and convection-cooled designs
Enterprise
Routers/Switches
Industrial Computing
and Networking
UTM Security
Appliances
The T1/T2 communications processors
are architected to provide maximum
performance per watt
17 TM
Freescale Multicore Platform
Power Architecture® Cores
On-Demand Acceleration CoreNet™ Fabric
Pattern Matching
Crypto Security
Table Lookups
Data Path Acceleration Architecture
e500mc
Core
L2 Cache
e500mc
Core
L2 Cache
e500mc
Core
L2 Cache
e500mc
Core
L2 Cache
CoreNet Fabric
Decompression / Compression
Data Path Resource Management
System Functions
Real-Time Debug
Trace Advanced Trace
512 KB 512 KB 512 KB
64-bit DDR3/3L/4
QUICC Engine
Ethernet eTSEC
PCI Express®
Connectivity
RapidIO® SATA USB
Platform Cache
Up to 1024 KB L3
32/64-bit DDR2/3/3L
• SCALE for Performance and Power
− The Right Cores
Processing / watt
Vector acceleration
Advanced threading
− The Right SoC Infrastructure
− The Right Balance Memories
• Enhanced Virtualization Support
− Hypervisor with three tier privilege modes
SoC memory
Interrupts
I/O virtualization
• Advanced Process Technology
• Multicore Debug
• Advanced Trace
• Trust Architecture
• Customer Driven Features
18 TM
Necessary feature if a system is to operate as multiple independent subsystems
• Application consolidation
• Customer consolidation
• Secure applications (e.g. policy modules, rights management)
• Untrusted software (third party; Sandbox application)
System is divided into “logical” partitions (a virtually independent sub-system)
• A sub-system each with its own operating system
Resources of the system are apportioned among logical partitions
• Processors, storage, devices, I/O, event mechanisms, etc.
Typically, individual operating systems want to “own” their resources
• Expect to map the resources into own address space (OWN = ACCESS) − Expect to initialize them
− Expect to have “unrestricted” access
Interpartition protection
• Subsystems must be protected from each other
• Computational state − Error: Required
− Performance: Best effort
23 TM
•kvm
• Freescale hypervisor
• Linux containers (lxc)
• Linux GRO/GSO
sofware offloads
• SEC XOR DMA
Fastpath modules:
• NAPT/firewall,
Ipfwd, IPsec (P3041,
P204x, P102x)
Power management:
• system sleep
• CPU idle
• CPU clock freq.
• thermal monitor
• Huge pages
• Egress TM
• Multi-threading
•Kernel 3.0
•U-Boot 2012-10
•Gcc 4.6.2
•Yocto 1.2
kvm
• vfio device assignment
• vhost net
• kernel MPIC
• libvirt management
• USB 2.0
• IP reassembly offload
Fastpath modules:
• IPv6
Power management:
• 64 bit hibernation
• CPU nap modes
• DPAA cascading power
management reference
• DPAA storage profiles
• Linux realtime – B4,
P1025
• T4 / B4 support
•Kernel 3.8
•U-Boot 2012-10+
•Gcc 4.7
•Yocto 1.4
kvm
• virtual time
• hotplug
• direct interrupts
• vcpu enhancements
• Unified Control Path
integration API (FP-API)
• Kernel FP-API
• Linux CP
integration
Fastpath modules:
• QoS
Power management:
• system deep sleep
• deep sleep proxy
•Hardware Table-walk
kvm
Fastpath modules:
• new features
Power management:
• new features
•Yocto 1.5
Fastpath modules
•
Available Now Target Date: May 2013
Virtualization Partitioning
Virtual Machines
Performance
Applications
Offloads
Fastpath
Power Efficiency
Power Mgt
Platform Power Architecture
ARM
SDK 1.3.2 SDK 1.7
Target Date: Nov 2013
SDK 1.5 SDK 1.6 SDK 1.4
2013 2014 4Q 2Q 3Q 4Q 1Q 1Q Available Now Future
25 TM
Enterprise AP-WLAN
Multiservice Gateway
(Media & Voice Gateway)
Security Appliance
Wireless
Media Gateway
NAS
Network
Attached Storage Networked Smart Gateway
Smart Energy Gateway
DLNA VOD Video-on-Demand
NVR – Network Video Recorder
(Video Surveillance)
Industrial Gateway
26 TM
Runtime Software HW and SW Engineering Services Training SW Dev Tools
HW Dev Tools
Application Specific
Middleware
Operating Systems
Training
Partners
Embedded Board Solutions
IDH/ODM
Com
mo
n
Occa
sio
na
l
Software and
Solution
Integrators (SSI)
Communities
Semiconductors/Companion Modules
For more partner options, visit freescale.com/partners
© 2012 Freescale Semiconductor, Inc.
Qonverge
Layerscape
P series
T series
Processor Expert
28 TM
e6500 / 1.8GHz
512KB L2
e5501/ 1.4GHz
256KB L2
2 – 4 cores
2 – 8 cores
A53 / 1.4GHz
256K L2
A57 / 1.8GHz
1MB L2
4 – 12 cores
6 – 32 cores
Leverage increase
in number of threads
for 2x performance
Leverage optimizations
In memory subsystem
& number of cores
Today 1st Wave Layerscape
SoC Solutions
Value
Tier
High
Tier
Mid
Tier
e500/ 800MHz
256KB L2 shared
1 – 2 cores
e500/ 1.5GHz
128KB L2
4 – 8 cores
29 TM
1- Core Agnostic (ARM, Power Arch)
• ARM V8 Product Roadmap
• Small / Large footprints
2- Scalable Acceleration Elements
• Sized to Application Needs
• Turn key or C-programmable
• Wire rate I/O switching & TM
3- Ease of Use
• Real Time Monitoring / Debug
• SW Management utility
• I/O virtualization
4- Turn-key Software
• Fast path modules
• Linux / BSP
• Hypervisor: KVM
• Eclipse-based Tools
Ethernet 100/40/10/1G
SERDES
Switching
& TM
PCI-
Express
C-prog Accelerated Packet Processor
Security
Engine
Pattern
Match
Engine
Load
Balance
Engine
Task
Scheduler
Re-
assembly
Table
Look Up
CPU 64b
CPU 64b
CPU 64b
CPU 64b
CPU 64b
CPU 64b
CPU 64b
DSP
DSP
DSP
Ease of Use (EoU) Facilities
Turn Key Software Linux SMP, KVM, Fast Path Module, Eclipse Tools
Layerscape: Networking 64b Multicore SoC Platform a) Industry standard Tools & C-programmability b) Abstracts I/O and Acceleration c) Turn-key / Production-quality SW
30 TM
1 2 Processing Elements Overview Scalable Acceleration Elements
3 4 Ease of Use Turn Key / Production-Quality SW
• Advanced 64b Power ISA: e6500 & e5500
• Fastest time to market with ARM A53 and A57
• Continue to leverage 64b Power and Starcore
• Scalable packet processing up to 100Gbps
• Ethernet L2 Switching for system optimization
• High speed interfaces & SERDES innovation
• Production quality SW - key differentiation enabler
• Modules and complete stacks for time to market
• Support for Software Services model
• Remote debug and real time trace innovation
• 3rd generation of H/W and S/W virtualization
• Fabric / interconnect innovation
TM 31
• Freescale continues performance innovation and leadership
− T4240 offers leadership compute density multicore processor
− T-Series offers widest range pin compatible portfolio
• Qonverge is the leading basestation SoC architecture
− B4860 is the highest performance basestation-on-a-chip available
− From femto to macro BTS
• The Layerscape architecture enables performance roadmap for the future
− Leadership in multicore for the next 10 years