1/31
Front End Processes2005 ITRS
Larry Larson, Assoc. Director, FEP DivisionSEMATECH
With Thanks to the 2005 FEP Sub-TWG Chairs:Carl Osburn, NCSUJeff Butterbaugh, FSI International
AVEM Seminar22 February 2006
2/31
New for 2005 FEP ChapterStarting Materials:• Starting Materials Position Paper on 450mm Substrates• Edge Exclusion Reduced to 1.5mm in 2007Thermal/Thin Films • Thermal/Thin Films/Doping Parallel Paths for Planar CMOS,
FDSOI, Multi-Gate• Need for High k Gate Stacks Moved to 2008• Metal Gate Electrode Work Functions Defined for FDSOI and
Multi-Gate Devices and for Low Power ApplicationsEtch• Increase and Reallocation of Gate CD toleranceMemory• Added Section on Phase Change Memory• Series Resistance Becomes More Limiting Factor
3/31
Near Term FEP Challenges2005-2012
• Starting silicon material alternatives greater than 300mm diameter require identification and assessment even as the 450mm diameter (standard evolutionary wafer enlargement) requires the start of wafer manufacturing development in year 2005.
• New gate stack processes and materials • Critical dimension and effective channel length (Leff)
control • Introduction and CMOS integration of new memory
materials and processes • Surfaces and interfaces—structure, composition, and
contamination control • Scaled MOSFET dopant introduction and control
4/31
Long Term FEP Challenges2013-2020
• Assessment of starting silicon material alternatives greater than 300mm diameter, including the 450mm diameter wafer.
• Continued scaling of planar CMOS devices • Introduction and CMOS integration of non-standard,
double gate MOSFET devices • New memory storage cells, storage devices, and
memory architectures • Surface and interface structural, contamination, and
compositional control
5/31
New for 2005 FEP ChapterStarting Materials:• Starting Materials Position Paper on 450mm Substrates• Edge Exclusion Reduced to 1.5mm in 2007Thermal/Thin Films • Thermal/Thin Films/Doping Parallel Paths for Planar CMOS, FDSOI,
Multi-Gate• Need for High k Gate Stacks Moved to 2008• Metal Gate Electrode Work Functions Defined for FDSOI and Multi-
Gate Devices and for Low Power ApplicationsEtch• Increase and Reallocation of Gate CD toleranceMemory• Added Section on Phase Change Memory• Series Resistance Becomes More Limiting Factor
6/31
Starting Materials450 mm Wafers
• 450 mm Wafers Required in 2012 (per ORTC direction)• Introduction of 450 mm presents unprecedented challenges
– Technical (meeting specs over larger areas)– Economic (especially for wafer, equipment, and metrology suppliers)– Critical path definition - We are already late to meet this development
cycle (3-4 years behind)– Standardization
• Wafer specification (type, thickness, diameter tolerance, etc.)• Factory automation (load lock, transportation method, etc.)• Wafer package (FOSB, FOUP, door configuration, etc.)
• 450 mm Wafer Issues Are Highlighted in 2005 ITRS – Discussion within FEP chapter– Supplemental position paper– Highlighted material in executive summary
7/31
Starting MaterialsDefect Density and Edge Exclusion
• High Performance(HP) MPU chip size– Previous ITRS defect densities were based on 310mm2 chip size
– Allowable defect densities for HP MPU consider new chip size scenario in 2005
• Edge Exclusion– Set at 1.5 mm in 2007 (from 2 mm in 2003) by Factory Integration
TWG, Where it will be Yellow for Bulk Si and Red for SOI– Implementation Poses a Significant, Immediate Challenge in FEP
• Edge Rolloff– Definition currently being addressed by SEMI / JEITA– Assessment of table entry for future ITRS publications (post 2005) to
be implemented once agreed upon metric is obtained• Defects
– Leading, Current SOI Manufacturing Processes Produce a Spatial Region at edge that is not Usable Real Estate for IC Production
8/31
Why is Edge Exclusion a big dealUsable Area2mm Exc.687cm2
Usable Area1.5mm Exc.692cm2
A 1% yieldincrease
9/31
New for 2005 FEP ChapterStarting Materials:• Starting Materials Position Paper on 450mm Substrates• Edge Exclusion Reduced to 1.5mm in 2007Thermal/Thin Films • Thermal/Thin Films/Doping Parallel Paths for Planar CMOS,
FDSOI, Multi-Gate• Need for High k Gate Stacks Moved to 2008• Metal Gate Electrode Work Functions Defined for FDSOI and Multi-
Gate Devices and for Low Power ApplicationsEtch• Increase and Reallocation of Gate CD toleranceMemory• Added Section on Phase Change Memory• Series Resistance Becomes More Limiting Factor
10/31
2003 ITRS: Multiple Enabling Technologies
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016
Strained Si--HP
High-k (Low Power)
Elevated S/D
High-k (HP)
Metal Gate (HP, dual gate)
Metal Gate (Low Power, dual gate)
Ultra-thin Body (UTB) SOI, single gate (HP)
Metal gate (near midgap for UTBSOI)
Strained Si (Low Power)
Multiple Gate (HP)
Ultra-thin Body (UTB) SOI, single gate (Low power)
Multiple Gate (Low Power)
Quasi-ballistic transport (HP)
Quasi-ballistic transport (LOP)
Quasi-ballistic transport (LSTP)
Production
Production
ProductionUncertain
ProductionUncertain
Production
Production
Production
Production
Production
Production
ProductionUncertain
Uncertain
Production
Production
11/31
Thermal / Thin Films / DopingParallel Lines to Capture Alternative Device Scenarios
• Extended Bulk and PD-SOI Devices to Overlap 4 Years with FD-SOI / Multi-Gate– Recognizes Different Approaches in Different Companies– Roadmap Illustrates Requirements for Different Scenarios– Increases the Number of Lines in the Table– FD-SOI and multi-gate will be placed on separate, over-lapping lines.
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016
Bulk/PD-SOIFD-SOI
Multi-Gate
The Baseline Scenario Envisions a Nominal Switch from Bulk to FD-SOI Around 2008, and a Switch to Multi-Gate Around 2012
12/31
New for 2005 FEP ChapterStarting Materials:• Starting Materials Position Paper on 450mm Substrates• Edge Exclusion Reduced to 1.5mm in 2007Thermal/Thin Films • Thermal/Thin Films/Doping Parallel Paths for Planar CMOS, FDSOI,
Multi-Gate• Need for High k Gate Stacks Moved to 2008• Metal Gate Electrode Work Functions Defined for FDSOI and
Multi-Gate Devices and for Low Power ApplicationsEtch• Increase and Reallocation of Gate CD toleranceMemory• Added Section on Phase Change Memory• Series Resistance Becomes More Limiting Factor
13/31
Difficult Transistor Scaling Issues• ITRS modeled scaling results involve high-level, idealized MOSFET
physics– Assumption: highly scaled MOSFETs with required characteristics can be
successfully fabricated• All lateral and vertical MOSFET dimensions (Tox, xj’s, spacer width,
etc.) are scaling down rapidly along with Lg
• With scaling, increasing difficulty in meeting transistor requirements – High gate leakage
• Direct tunneling increases rapidly as Tox is reduced– Poly depletion in gate electrode increased effective Tox, reduced Ion– Scaling S/D extension and deep S/D
• High Rseries,s/d reduced Ion– Etc.
14/31
High K Gate Dielectric to Reduce Direct Tunneling
• Equivalent Oxide Thickness = EOT = TK * (3.9/K) = Tox, where 3.9 is relative dielectric constant of SiO2 and K is relative dielectric constant of high K material
– C = Cox = εεεεox/Tox– To first order, MOSFET characteristics with high-k are same as for SiO2
• Because TK > Tox, direct tunneling leakage much reduced with high K– If energy barrier is high enough
• Candidate materials: LaO2/HfO2/ (K~15 - 30); Hf, Zr-SiO4 (K~12 - 16); others– Major materials, process, integration issues to solve
Electrode
Si substrate
Tox SiO2TK
High-k Material
Electrode
Si substrate
15/31
Gate Leakage Current Density Due to Direct Tunneling for Low Standby Power Logic: 2001 ITRS Projections Versus Simulations
1.E+02
Implementation of high-k will be driven by Low Power Logic in 2005
(Simulations courtesy of C. Osburn, NCSU and ITRS)
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
2001 2003 2005 2007 2009 2011 2013 2015
Year
J gat
e (A/c
m2 )
0
0.5
1
1.5
2
2.5
Tox (nm
)
2005 or beyond, high-k needed to reduce gate leakage
Jgate: simulated assuming oxynitride
Maximum Jgate Projections per 2001 ITRS
Tox
16/31
Thermal / Thin Films / DopingDeferred Implementation of High k
2004
2005
2006
2007
2008
Enhanced Mobility
High k for Low Power
High K for MPUMetal Gate
FD-SOI
Enhanced Mobility
“
“
High k for Low PowerHigh K for MPUMetal GateFD-SOI
Year 2003 ITRS 2005 ITRS
• Puts Multiple, Major Changes into One Year (2008)• Causes Other Parameters, e.g., Xj, to Scale More Aggressively
17/31
Thermal / Thin Films / DopingMetal Gate Electrode Work Functions
• Constraint was Added to PIDS Device Design Scenario for Bulk, FDSOI, and Multi-Gate, Namely to Minimize the Number of Different Work Function Metals Needed Over Time
•••• Three-Four Systems Seen to Meet All Needs Through 2020- Band Edge (~100 meV inside band) for Bulk- ~150 meV Above*/Below* Midgap for HP FDSOI- Midgap for HP Multi-Gate, LOP FDSOI and Multi-Gate- ~100 meV Below*/Above* Midgap for LSTP FDSOI and Multi-
Gate
• Band Edge Metal Gates Viewed as Limiting Factor in High k Deployment
NMOS*/PMOS*
18/31
Thermal / Thin Films / DopingDoping and Junctions
• EOT Values are Given for Different Poly-Si Doping Levels-1e20/cm3 (lightly-doped) tdepletion ~ 0.5 nm-1.5e20/cm3 (baseline doping) tdepletion ~ 0.4 nm-3e20/cm3 (advanced, e.g., laser annealed) tdepletion ~ 0.2nm
• Junction Depths are Scaled More Aggressively in 2005 to Accommodate Slower EOT Scaling
• Junction Implant Parameters to meet Xj-Rs Requirements are Given in Supplemental Tables
-Maximum Implant Energy-Dose
• Series Resistance Becomes a Increasingly Important Limitation (Ominous)
• Scenario, Rather than Requirements, Given for Elevated Junctions in FDSOI and Multi-Gate
19/31
New for 2005 FEP ChapterStarting Materials:• Starting Materials Position Paper on 450mm Substrates• Edge Exclusion Reduced to 1.5mm in 2007Thermal/Thin Films • Thermal/Thin Films/Doping Parallel Paths for Planar CMOS, FDSOI,
Multi-Gate• Need for High k Gate Stacks Moved to 2008• Metal Gate Electrode Work Functions Defined for FDSOI and Multi-
Gate Devices and for Low Power ApplicationsEtch• Increase and Reallocation of Gate CD toleranceMemory• Added Section on Phase Change Memory• Series Resistance Becomes More Limiting Factor
20/31
EtchRepartitioning of Lithography and Etch Contributions to Physical Gate Length
Issue: Neither Etch nor Lithography Could Meet Tolerance Budgets to Achieve +/- 10% Control of Physical Gate Length
2005 “Partial Solution”: • Maintain Final (Etched) Physical Gate Length at 2003 Values• Relax (increase) Printed Gate Length Dimension in Resist• Increase the Amount of Resist Trim• Increase the Total Tolerance on Physical Gate Length to 12%• Repartition Tolerance Budgets from 80% Litho/20% Etch to 75% Litho/25% Etch
Observation: At the “90 nm Node”, Most Manufacturers are using Gate Lengths Longer than ITRS Values.
- If Trend Persists, ITRS Values May Need to be Adjusted Upwards in 2006-7
21/31
EtchGate Etching
25%12%2005
20%10%2004
Fraction of variance allocated to etch
Total allowed 3
sigma
• Gate sizing variation allowance• Surveys in 2003 and 2004 indicated that the industry
was not processing etched gates at <10% 3 sigma• Feedback from device modeling indicated that relaxing
to 12% 3 sigma would not degrade performance• Requirements for gate etch were relaxed as follows:
(Litho is given75% of the allowablegate length variance)
22/31
EtchGate Etching
3 sigma gate length tolerance
0
2
4
6
8
2001 2002 2003 2004 2005 2006 2007
nm
0
10
20
30
40
50
60
70
nm
Total LithoEtchEtch (03)Phys Lgate
2001 ITRS 2003 ITRS 2005 ITRS
Increase of overall gate sizing tolerance from 10-12% and allocation of variance to etch from 20-25%
- Increases Litho allowance by 18%- Increases Etch Absolute allowance by 35% - Allows improved coloration of the table entries
23/31
New for 2005 FEP ChapterStarting Materials:• Starting Materials Position Paper on 450mm Substrates• Edge Exclusion Reduced to 1.5mm in 2007Thermal/Thin Films • Thermal/Thin Films/Doping Parallel Paths for Planar CMOS, FDSOI,
Multi-Gate• Need for High k Gate Stacks Moved to 2008• Metal Gate Electrode Work Functions Defined for FDSOI and Multi-
Gate Devices and for Low Power ApplicationsEtch• Increase and Reallocation of Gate CD toleranceMemory• Added Section on Phase Change Memory• Series Resistance Becomes More Limiting Factor
24/31
Stacked-Capacitor DRAM Changes for ITRS 2005
Cell size factor, a, is projected to remain at 8 through 2007—not scaling as rapidly as projected in 2003-4
Capacitor dielectric material and Dielectric constant are modified based on survey of DRAM manufacturers
25/31
Stacked-Capacitor DRAM Changes in 2005
Year of Production 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
- Choice of capacitor dielectric material is an ongoing question
Cell size factor a
8.0 7.5 7 7 6 6 6 6 6 6 6 6 6 5 52005 ITRS2005 ITRS 88 88 88 66 66 66 66 66 66 66 66 66 66 66 66 66
2003/2004 ITRS2003/2004 ITRS
Capacitor dielectric material – potential solutions
ALO/TAO ALO/TAO ALO /TAO /others
AlAl22OO33, HfO, HfO22,,TaTa22OO55
ultraultra--highhigh--k, new materials, strontiumk, new materials, strontium--based,based,perovskitesperovskites
TaTa22OO55, TiO, TiO222005 ITRS2005 ITRS
2003/2004 ITRS2003/2004 ITRS new material
2005 ITRS2005 ITRS 22 40 50 50 50 50 50 60 60 60 80 80 80 100 100 100100 100100Dielectric constant
26/31
Trench-Capacitor DRAM Changes in 2005 versus 2004 Update
Solutions exist down to 57nm generation (WAS: 70nm)
“Red brick wall” moved out to 28nm
Higher trench aspect ratios anticipated for ≤ 45nm
MIM option for ≤ 50nm (WAS: ≤ 45nm)
MIM only option for ≤ 35nm (WAS: epi-high-k as 2nd option)
27/31
ITRS 2005 Trench DRAM RoadmapYear of 1st Product Shipment
Technology Node2004
90 nm2005
80 nm2006
70 nm2007
65 nm2008
57 nm2009
50 nm2010
45 nm2011
40 nm2012
35 nm2013
32 nm2014
28 nmDRAM 1/2 pitch [nm] 90 80 70 65 57 50 45 40 36 32 28Cell size factor 8 8 8 8 8 8 8 8 8 8 8Cell size [µm2] 0.065 0.051 0.039 0.034 0.026 0.020 0.016 0.013 0.010 0.008 0.006Trench structure bottled bottled bottled bottled bottled bottled bottled bottled bottled bottled bottledTrench circumference [nm] 748 665 582 540 474 416 374 333 291 266 233Trench area enhancement factor (bottle) [A] 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6Trench surface roughening factor 1.3 1.25 1.25 1.2 1 1 1 1 1 1 1Effective oxide thickness (CET) [nm] 5.2 4.4 4.3 3.9 2.8 2.3 2.0 1.8 1.6 1.4 1.2Trench depth [mm] (at 35fF) 6.4 6.2 6.8 6.8 6.7 6.2 6.1 6.2 6.1 6.0 5.8Aspect ratio [trench depth / trench width] 55 60 75 80 90 95 105 120 135 145 160
Upper electrode Poly-Silicon Poly-Silicon Poly-Silicon Metal Metal Metal Metal Metal Metal Metal Metal
Dielectric material NO High-k High-k High-k High-k High-k High-k High-k High-k High-k High-k
Bottom electrode Silicon Silicon Silicon Silicon Silicon 1: Silicon 1: Silicon 1: Silicon Metal Metal Metal2: Metal 2: Metal 2: Metal
Capacitor structure / dielectric SIS / NO
Solutions Exist Solutions Being Pursued No known Solutions
2: MIM / High-kSIS / High-k MIS / High-k 1: MIS / High-k
Known Solutions exist through 57nm generation “Red brick wall” moved to 28nmMIM option for ≤ 50nm; only option for ≤ 35nm
28/31
Flash Memory • A sharp decrease in the interpoly dielectric (IPD) EOT is needed at 45-50
nm, for NOR, and maybe for NAND, to enable further scaling of the Bit Line pitch and the Floating Gate spacing and to maintain an acceptable Coupling Ratio (CR)
Poly 1
Poly 1
Poly 2IPD
Poly 2
Poly 2
IPD
IPD
65 nm
60-80 nm
Poly 1
Poly 1
Poly 2IPD
Poly 2IPD
Decoupling
50-60 nm
45 nm10-12 nm EOT
4-6 nm EOT
• ONO (Oxide-Nitride-Oxide) technology is no longer feasible and new materials/architecture are necessary (e.g., high-k,…)
• Alternatively new floating gate design (e.g., SiN charge storage)• Since STI may be formed post floating gate and because it is deeper,
its aspect ratio is higher than in logic ⇒⇒⇒⇒ trench fill technology is more critical (MLD or SOD)
29/31
FeRAM• Japan PIDS Surveyed the Commercial Production Status of FeRAM
• 2005 Technology Generation Feature Sizes will be for Stand-alone memory at 10k/mo volume by 2 companies (as with DRAM)– 2003-4 ITRS Used Both Stand-alone and Embedded Memory
• Scaling Rate of FeRAM is Subject of Ongoing FEP/PIDS Discussion
0.01
0.1
1
2000 2005 2010 2015 2020 2025Year
Feat
ure
Size
(um
)
ITRS2003 (Standard Memory)ITRS2003 (Embedded Memory)ITRS2001Proposal for ITRS2005
30/31
FeRAM• Access and Cycle Time are now Expected to Scale More
Slowly than Projected in 2003 ITRS• Assuming a Minimum Switching Charge Density of
30µµµµC/cm2 and a Bit Line Voltage Swing of 140mV, 3 Dimensional (3D) Capacitors will be Needed in 2010
• Definition of Minimum Switching Charge Density after 3D Introduction will be Determined with PIDS
0
20
40
60
80
100
2000 2005 2010 2015 2020 2025Year
Acc
ess
Tim
e (n
s) ITRS2003
ITRS2001
Proposal for ITRS2005
020406080
100120140
2000 2005 2010 2015 2020 2025Year
Cyc
le T
ime
(ns)
ITRS2003
ITRS2001
Proposal for ITRS2005
31/31
Conclusions – Or more correctly: Ongoing FEP Issues and Challenges
• 450 mm Wafers – Time to start moving!• Edge Exclusion – move for more yield!• Introduction of High k Gate Stacks – When??• Gate CD Control – Are we pushing the limits?• Increasing importance of individual device
requirements: Memory– Higher K Dielectrics and Cell Size Reduction for
DRAM– Scaling Flash Memory
