FUNDAMENTALS OF FUNDAMENTALS OF SINGLE CHIP PACKAGINGSINGLE CHIP PACKAGING

Marko BUNDALOMarko BUNDALO

Derek LINDBERG Derek LINDBERG

Chapter ObjectivesChapter Objectives

Single chip package (SCP)Single chip package (SCP)

Functions of a SCPsFunctions of a SCPs

Types of SCPsTypes of SCPs

Fundamentals of SCPFundamentals of SCP

Materials, Processes, PropertiesMaterials, Processes, Properties

Characteristics of SCPsCharacteristics of SCPs

IntroductionIntroduction

SCP – components (IC) onto system-level boardsSCP – components (IC) onto system-level boards

Plastic – low cost Plastic – low cost

Ceramics – high thermal performance & reliabilityCeramics – high thermal performance & reliability

Recent trend – area array packages:Recent trend – area array packages:

ball grid array (BGA) ball grid array (BGA)

chip scale package (CSP)chip scale package (CSP)

7.1 Single chip package (SCP)7.1 Single chip package (SCP)

7.2 Functions of a SCPs7.2 Functions of a SCPs

7.3 Types of SCPs7.3 Types of SCPs

7.4 Fundamentals of SCP7.4 Fundamentals of SCP

7.5 Materials, Processes, Properties7.5 Materials, Processes, Properties

7.6 Characteristics of SCPs7.6 Characteristics of SCPs

7.7 Summary and Future Trends7.7 Summary and Future Trends

7.1 Single Chip Package7.1 Single Chip Package

SCP supports a single microelectronic device SCP supports a single microelectronic device Electrical, thermal, chemical performance adequately servedElectrical, thermal, chemical performance adequately served Wafer Diced Packaged Burnt-in TestedWafer Diced Packaged Burnt-in Tested Packaged IC = (few to million) of transistorsPackaged IC = (few to million) of transistors

Example of SCP – Example of SCP –

Intel’s ceramic pin grid array –Intel’s ceramic pin grid array –

generations of X86 family generations of X86 family

microprocessorsmicroprocessors

ACTIVE devicesACTIVE devices Memory or microprocessorMemory or microprocessor Active – device capable of modifying and enabling the information in Active – device capable of modifying and enabling the information in

accordance with the logical instruction set.accordance with the logical instruction set.

PASSIVE devicesPASSIVE devices Resistors, capacitors, inductorsResistors, capacitors, inductors Do not alter the transmitted signalDo not alter the transmitted signal Serve to optimize the performance and function Serve to optimize the performance and function Chapter 11Chapter 11

Active vs. Passive devicesActive vs. Passive devices

More than one ACTIVE device multichip package (MCP) or More than one ACTIVE device multichip package (MCP) or

multichip module (MCM) multichip module (MCM)

System designers - Combination of PASSIVE components, SCPs, System designers - Combination of PASSIVE components, SCPs, MCM to meet application needs of the system.MCM to meet application needs of the system.

Examples of SCP for common applications:Examples of SCP for common applications:

Examples of SCP Examples of SCP

7.1 Single chip package (SCP)7.1 Single chip package (SCP)

7.2 Functions of a SCPs7.2 Functions of a SCPs

7.3 Types of SCPs7.3 Types of SCPs

7.4 Fundamentals of SCP7.4 Fundamentals of SCP

7.5 Materials, Processes, Properties7.5 Materials, Processes, Properties

7.6 Characteristics of SCPs7.6 Characteristics of SCPs

7.7 Summary and Future Trends7.7 Summary and Future Trends

7.2 Functions of a SCPs7.2 Functions of a SCPs Primary function – enable the device/chipPrimary function – enable the device/chip Perform its designed functions in a reliable mannerPerform its designed functions in a reliable manner

Product life varies Product life varies 1-2 years or less – cell phones and microprocessors for PCs1-2 years or less – cell phones and microprocessors for PCs 15-20 years – public exchange telecommunication switches15-20 years – public exchange telecommunication switches Up to 40 years – military and aerospace applicationsUp to 40 years – military and aerospace applications

EVERY single chip package EVERY single chip package MUSTMUST perform 6 functions: perform 6 functions: Signal transmission and power distribution TO and FROM the ICSignal transmission and power distribution TO and FROM the IC Signal transmission and power distribution BETWEEN the package device and Signal transmission and power distribution BETWEEN the package device and

other components.other components. Enable device to be ATTACHED to the next level of packagingEnable device to be ATTACHED to the next level of packaging Allow for effective DISSIPATION OF HEAT generated by the packageAllow for effective DISSIPATION OF HEAT generated by the package Provide adequate PROTECTION of the deviceProvide adequate PROTECTION of the device Act as SPACE TRANSFORMER between the fine pitch grid and the PWB pitch gridAct as SPACE TRANSFORMER between the fine pitch grid and the PWB pitch grid

Single chip package needs to deliver the best possible performance at the Single chip package needs to deliver the best possible performance at the lowest possible cost.lowest possible cost.

7.1 Single chip package (SCP)7.1 Single chip package (SCP)

7.2 Functions of a SCPs7.2 Functions of a SCPs

7.3 Types of SCPs7.3 Types of SCPs

7.4 Fundamentals of SCP7.4 Fundamentals of SCP

7.5 Materials, Processes, Properties7.5 Materials, Processes, Properties

7.6 Characteristics of SCPs7.6 Characteristics of SCPs

7.7 Summary and Future trends7.7 Summary and Future trends

7.3 Types of SCPs7.3 Types of SCPs

Single chip packages classified into three types:Single chip packages classified into three types:

PTH (pin-through-hole)PTH (pin-through-hole)

SMT (surface mount technology)SMT (surface mount technology)

SMT-Area ArraySMT-Area Array

Microprocessor evolution during last three decadesMicroprocessor evolution during last three decades IBM (CISC – complex instruction set computing)IBM (CISC – complex instruction set computing) Apple (RISC – reduced instruction set computing)Apple (RISC – reduced instruction set computing)

Ceramic Pin-Grid-Arrays (PGAs) used SCP since 1982Ceramic Pin-Grid-Arrays (PGAs) used SCP since 1982 Ease of pluggability and removal for IC repairEase of pluggability and removal for IC repair Proven reliabilityProven reliability Area array connectionsArea array connections Compatible PWB availabilityCompatible PWB availability

Plastic (PGAs) replaced ceramicPlastic (PGAs) replaced ceramic Recently, build-up or high-density Ball-Grid-Array (BGA)Recently, build-up or high-density Ball-Grid-Array (BGA)

Lower cost Lower cost Higher electrical performanceHigher electrical performance

Table - Types of single chip packages, I/O, pitches and volumesTable - Types of single chip packages, I/O, pitches and volumes

In memory – plastic packages and lower pin count higher volumesIn memory – plastic packages and lower pin count higher volumes Higher priced ceramics packages, high pin count lower volumesHigher priced ceramics packages, high pin count lower volumes BGA emerges as dominant in futureBGA emerges as dominant in future Joint Electronic Device Engineering CouncilJoint Electronic Device Engineering Council – establishes the package – establishes the package

geometrygeometry This body mandates standard dimensions for types of packagesThis body mandates standard dimensions for types of packages

Companies provide set of technical specifications Companies provide set of technical specifications Material of construction, dimensional features, electrical, thermal and Material of construction, dimensional features, electrical, thermal and

reliability performancereliability performance

Logic and Memory PackagesLogic and Memory Packages

Total number of package pin outs to the PWB depends upon data being Total number of package pin outs to the PWB depends upon data being processedprocessed

Total pin counts vary from few dozen to over a thousandTotal pin counts vary from few dozen to over a thousand Memory chips – few I/O pinsMemory chips – few I/O pins Logic chips – higher number of gates/circuits – more pinsLogic chips – higher number of gates/circuits – more pins Wide bandwidth networking switches for transmission over the internet – over Wide bandwidth networking switches for transmission over the internet – over

1000 I/O pins1000 I/O pins

Package pins distributed between:Package pins distributed between: SignalSignal PowerPower Common reference voltage or groundCommon reference voltage or ground

System performance ↑ - total pin count ↑System performance ↑ - total pin count ↑ High performance - ↑ power and ground pins in order to reduce electrical High performance - ↑ power and ground pins in order to reduce electrical

noise during fast circuit switching.noise during fast circuit switching.

7.1 Single chip package (SCP)7.1 Single chip package (SCP)

7.2 Functions of a SCPs7.2 Functions of a SCPs

7.3 Types of SCPs7.3 Types of SCPs

7.4 Fundamentals of SCP7.4 Fundamentals of SCP

7.5 Materials, Processes, Properties7.5 Materials, Processes, Properties

7.6 Characteristics of SCPs7.6 Characteristics of SCPs

7.7 Summary and Future trends7.7 Summary and Future trends

7.4 Fundamentals of SCP7.4 Fundamentals of SCP The need for I/O determined be Rent’s RuleThe need for I/O determined be Rent’s Rule Designers use it in estimating the number of required package Designers use it in estimating the number of required package

pins or I/O terminals (N), given the total number of gates (M)pins or I/O terminals (N), given the total number of gates (M)

K is constant – the average number of terminals required by one logic K is constant – the average number of terminals required by one logic circuitcircuit

p is constant – depends on system typep is constant – depends on system type Four main classes of application:Four main classes of application:

1. memory (static and dynamic RAMs)1. memory (static and dynamic RAMs)2. microprocessors2. microprocessors3. gate arrays (FPGAs)3. gate arrays (FPGAs)4. high-performance custom logic chips (“supercomputers”)4. high-performance custom logic chips (“supercomputers”)

Relationship between chip I/Os and the number of Relationship between chip I/Os and the number of chip circuits for various applicationschip circuits for various applications

I/O Pitch and DistributionI/O Pitch and Distribution I/O pitch definedI/O pitch defined Peripheral vs. Area (BGA)Peripheral vs. Area (BGA) 20mm package at 0.2mm pitch – 10,000 I/Os20mm package at 0.2mm pitch – 10,000 I/Os

What package to use – board assembly yieldWhat package to use – board assembly yield The first pass manufacturing yield at IC assembly for The first pass manufacturing yield at IC assembly for

various packages are:various packages are:

The most important reasons for these yields:The most important reasons for these yields: Contribution of the pitch Contribution of the pitch Self-alignment of solders to minimize shorts between two Self-alignment of solders to minimize shorts between two

neighboring connectionsneighboring connections Coplanarity of leads parallel to the boardCoplanarity of leads parallel to the board Solder wettingSolder wetting Solder ball collapseSolder ball collapse

Materials Influence Materials Influence PerformancePerformance

Electrical PerformanceElectrical Performance RC delay – influence the speed of signal RC delay – influence the speed of signal

propagation through the packagepropagation through the package

V = C / square root of dielectric constantV = C / square root of dielectric constant V is signal propagationV is signal propagation C is speed of lightC is speed of light

Thermal PerformanceThermal Performance Thermal dissipation capabilities dependent on the Thermal dissipation capabilities dependent on the

materials with which SCP are made.materials with which SCP are made. Intel’s microprocessor ICs – 4W in 1989Intel’s microprocessor ICs – 4W in 1989 30W currently30W currently 100W in near future100W in near future

Single Chip PackagesSingle Chip Packages

Peripheral:Peripheral: DIP to PLCC to QFP to fine pitch QFPDIP to PLCC to QFP to fine pitch QFP

DIP, SOP, and QFPDIP, SOP, and QFP

Area Array:Area Array: Ceramic and plastic PGA to BGA to fine Ceramic and plastic PGA to BGA to fine pitch BGApitch BGA

Flip Chip:Flip Chip: Ceramic flip chip to organic flip chipCeramic flip chip to organic flip chip

DIP: Dual In line PackageDIP: Dual In line Package

Invented by Bryan Rogers in the early 1960s with 14 Invented by Bryan Rogers in the early 1960s with 14 leadsleads

Adopted by Texas Instruments in 1962Adopted by Texas Instruments in 1962 Plastic or Ceramic versionPlastic or Ceramic version Earliest industry standardEarliest industry standard Low pin counts – 8 to 48 pin rangeLow pin counts – 8 to 48 pin range Memory and logic microcontrollersMemory and logic microcontrollers Interconnect to the next level provided by copperInterconnect to the next level provided by copper Lead pitches of 1.75mm and 2.5mmLead pitches of 1.75mm and 2.5mm Not preferred when space is a critical design constraintNot preferred when space is a critical design constraint

SOP: Small Outline PackageSOP: Small Outline Package

Well-suited for 24 to 48 pin memory packagingWell-suited for 24 to 48 pin memory packaging Cell phones, pagers, PCMCIA cardsCell phones, pagers, PCMCIA cards Similar to DIP by using copper leadframe for Similar to DIP by using copper leadframe for

pinspins Leads have minimum standoff – making it Leads have minimum standoff – making it

easier to use in a surface mount assembly easier to use in a surface mount assembly process to attach to the circuit board.process to attach to the circuit board.

QFP: Quad Flat PackQFP: Quad Flat Pack

Plastic QFP – established member of the family of Plastic QFP – established member of the family of peripherally-leaded packagesperipherally-leaded packages

Main difference – runs around all four sidesMain difference – runs around all four sides Enables higher pin count – up to 304 pinsEnables higher pin count – up to 304 pins The most common usage – 48 to 128 rangeThe most common usage – 48 to 128 range Very popular choice for lower cost microprocessors Very popular choice for lower cost microprocessors

and other ICs for portable systemsand other ICs for portable systems Ceramic QFP preferred when resistance to high Ceramic QFP preferred when resistance to high

temperatures and humidity becomes an important temperatures and humidity becomes an important design parameter.design parameter.

Area Array PackagesArea Array Packages The first high volume PGA package in 1982The first high volume PGA package in 1982 1993, Motorola started shipping BGA1993, Motorola started shipping BGA Since, packages have been “hot spot”Since, packages have been “hot spot” SOP and QFP more expensiveSOP and QFP more expensive Last few years – With finer pitch and lower cost, Chip Last few years – With finer pitch and lower cost, Chip

Scale Package (CSP) count as low as 36 or less.Scale Package (CSP) count as low as 36 or less. CSP twice as expensive as small outline packages.CSP twice as expensive as small outline packages. High I/O for BGA, small size for CSPHigh I/O for BGA, small size for CSP Distinguish between CSP and BGA:Distinguish between CSP and BGA:

A Ball-Grid-Array is an array package with a ball pitch of 0.8mm A Ball-Grid-Array is an array package with a ball pitch of 0.8mm or greater. Includes very high leadcount packages (>500 I/O)or greater. Includes very high leadcount packages (>500 I/O)

A Chip-Scale-Package is an array package with a ball pitch of A Chip-Scale-Package is an array package with a ball pitch of 0.8mm or less (0.5, 0.75, or 0.8) and area no more than 50% 0.8mm or less (0.5, 0.75, or 0.8) and area no more than 50% more than the IC.more than the IC.

BGA: Ball Grid ArrayBGA: Ball Grid Array Overcomes many size and performance limitations of Overcomes many size and performance limitations of

peripherally-leaded packagesperipherally-leaded packages Greater number of I/Os at larger pitch preventing solder Greater number of I/Os at larger pitch preventing solder

shorts.shorts. Basic types:Basic types:

Plastic (PBGA)Plastic (PBGA) Ceramic (CBGA)Ceramic (CBGA) Tape (TBGA)Tape (TBGA)

Advantages:Advantages: SizeSize PerformancePerformance Ease of assemblyEase of assembly

CSP: Chip Scale PackageCSP: Chip Scale Package Size advantage. Only 50% larger area than the silicon Size advantage. Only 50% larger area than the silicon

wafer and only 20% larger circumference.wafer and only 20% larger circumference. This makes it one of the most important package types.This makes it one of the most important package types.

Materials, Processes, and Materials, Processes, and PropertiesProperties

Typical elements of an SCP:Typical elements of an SCP: Base substrate for wiringBase substrate for wiring Interconnects between chip and packageInterconnects between chip and package Interconnect scheme between package and PCBInterconnect scheme between package and PCB Encapsulation to mechanically and chemically protect Encapsulation to mechanically and chemically protect

the chip and for thermal managementthe chip and for thermal management Adhesive materials to attach chip to substrate Adhesive materials to attach chip to substrate

(underfill)(underfill)

Materials chosen must be:Materials chosen must be: Physically strongPhysically strong Corrosion resistantCorrosion resistant Withstand temperature and environmental conditionsWithstand temperature and environmental conditions

MaterialsMaterialsCommon Package Materials:Common Package Materials:

Plastic molding compounds (QFPs)Plastic molding compounds (QFPs) Organic laminates such as FR-4, BT-epoxy (BGAs)Organic laminates such as FR-4, BT-epoxy (BGAs) Ceramics, both high (HTCC) and low temperature (LTCC) used Ceramics, both high (HTCC) and low temperature (LTCC) used

in PGAs and BGAsin PGAs and BGAs Thin film flex and tape matreialsThin film flex and tape matreials

By volume the majority of SCPs are laminatesBy volume the majority of SCPs are laminates Manufacturability in large arrays makes them cheapManufacturability in large arrays makes them cheap Ability to use copper conductors can give better electrical Ability to use copper conductors can give better electrical

performanceperformance High-frequency and high pin count use ceramicsHigh-frequency and high pin count use ceramics

Most common is alumina or HTCCMost common is alumina or HTCC Superior strength, moisture, and temperature toleranceSuperior strength, moisture, and temperature tolerance High processing temperature requires molybdenum or tungsten High processing temperature requires molybdenum or tungsten

conductorsconductors

Encapsulants, Lids, and AdhesivesEncapsulants, Lids, and Adhesives

Package type and application specific:Package type and application specific: Copper lids or slugs in contact with the silicon can Copper lids or slugs in contact with the silicon can

provide an improved thermal interfaceprovide an improved thermal interface Low cost molding compounds or “globtops” can be Low cost molding compounds or “globtops” can be

used to seal and protect devicesused to seal and protect devices Variety of adhesives are used to attach the device to Variety of adhesives are used to attach the device to

the package:the package: Silver filled epoxySilver filled epoxy Gold/gold-silicon compoundsGold/gold-silicon compounds

Electrical CharacteristicsElectrical CharacteristicsBasic parameters of a package are:Basic parameters of a package are:

Line resistanceLine resistance Loading capacitanceLoading capacitance InductanceInductance

Models used to evaluate SCPs must account for Models used to evaluate SCPs must account for all elements of a packageall elements of a package

A good package exhibits minimum switching A good package exhibits minimum switching noise at the frequencies of operationnoise at the frequencies of operation

Packaging EfficiencyPackaging Efficiency Ratio of IC area to Package areaRatio of IC area to Package area

Very critical in portable electronicsVery critical in portable electronics

ReliabilityReliability A major issue withA major issue with

Medical devicesMedical devices High up-time devicesHigh up-time devices Automotive and airborne componentsAutomotive and airborne components

Full testing suite might take 4+ months to runFull testing suite might take 4+ months to run Accelerated testing of expected loads:Accelerated testing of expected loads:

Thermal shockThermal shock Shipping shockShipping shock VibrationVibration HumidityHumidity Chemical exposureChemical exposure

CostCost Price premium for clock speedPrice premium for clock speed Relative cost of package to IC will determine Relative cost of package to IC will determine

what format is usedwhat format is used Higher cost BGAs and CSPs can be justified for Higher cost BGAs and CSPs can be justified for

decreased sizedecreased size

Future TrendsFuture Trends Trends driven by size, cost, reliability and Trends driven by size, cost, reliability and

increasing electrical performance.increasing electrical performance.