Research Activities on Defect Improvement of CMP Process in 1x nm Foundry Device
1JI CHUL YANG, 2Hong Jin Kim, 2Venu. Govindarajulu,1Dinesh Koli and 2Jason Mazzotti
1 CMP, Advanced Technology Development (ATD) , 2 CMP, Advanced Module Enginnering (AME)
Confronting Reality in semiconductor field.
• Scaling Challenges
• Device Structure
• Flow Complexity
• New Material Introduction
• Complex Interdependencies
2
Critical Insights
Needed to Manage
Dynamics
CMP is becoming COMPLEX!
• CMP steps doubled from 28nm to 10nm node in order to enable new integration schemes such as replacement metal gate or self-aligned contact.
• Higher increased in 10nm CMP steps at MOL due to the complexity of contact module from gate and contact engineering.
3
16 TSV Cu
15 9-10 Cu
14 TSV Cu W-CA/CB
13 9-10 Cu SIOC
12 W-CA/CB TI ILD
11 RM GP
10 W-TS MO
9 W-Gate SiN Cap
8 TSV Cu POC W-Gate
7 9-10 Cu ILD2 ILD2
6 W-CA/CB ILD1 ILD1
5 W-TS GP TI ILD
4 9-10 Cu Al Gate MO GP
3 W ILD2 RB MO BEOL
2 Oxide ILD1 STI2 Nit Buff MOL
1 STI STI STI1 STI FEOL
28nm 20nm 14nm 10nm
FEOL
FEOL FEOL
MOL
MOL MOL
Num
ber
of
Ste
p (
A.U
)
CMP process challenges
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20nm 14nm 10nm
Selectivity
Materials
FEOL: SiN, Ox
MOL: SiN, Ox, W, TiN, Al
BEOL: Cu, Ta, TaN, TiN
FEOL: Si, SiN, Ox, a-Si
MOL: W, SiN, Ox, poly Si,
New Materials
BEOL: Cu, Ta, TaN, TiN
FEOL: Si, SiN, Ox, low k
MOL: W, SiN, Ox, poly,
New materials
BEOL: Cu, Ta, TaN.
Lower Resistivity material.
3sigma < 100 (A.U) 3sigma < 66 (A.U) 3sigma < 46 (A.U) Uniformity (100x100um)
Dishing/
Erosion Higher PD < 100 (A.U) Higher PD <83 (A.U) Higher PD < 66 (A.U)
More new materials are expected in the future nodes in order to meet stringent process
requirement in CMP
Increasing challenge in 3 D’s
• Must deliver minimal & stable non-uniformity
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Silicon Wafer
Within-die uniformity Within-wafer uniformity
Within-macro uniformity
ICPT 2015 keynote Speaking material , Mark Doherty , GF
Increasing challenge – defect translation
• Increased # layers = increased defect translation
GLOBALFOUNDRIES Confidential 6
FEOL CMP
BEOL CMP
ICPT 2015 keynote Speaking material , Mark Doherty , GF
Unforgettable and endless problem in CMP
GLOBALFOUNDRIES Confidential 7
Micro and Nano Scratches
GLOBALFOUNDRIES Confidential 8
Improvement activities for Micro Scratches
Macro 1 Macro 2 Macro 3
Co
nve
nti
on
al
Ab
rasi
ve
Nan
op
arti
cle
Ab
rasi
ve
Nanoparticle-Ceria: CMP Performance
9
Case I: Poly CMP
Mic
ro/n
an
osc
ratc
h d
en
sity
(re
lati
ve)
1.0
0.8
0.6
0.4
0.2
0.0
Lot IDs
Nano-sized cerium hydroxide slurry buffing
Case II: Inter-layer Dielectric (ILD)
Nano-ceria based slurry showed microscratch
reduction in multiple process steps with different
integration scheme, however most processes are
limited to buffing CMP only so far Planarity and
selectivity control is the key challenges (i.e., proper
slurry chemistry) with nano-scale abrasive application
for CMP slurry (removal rate is tunable with easy and
comparable to conventional ceria based slurry)
Macro to Macro Variation
Nanoparticle-ceria abrasive Slurry Nanoparticle-
ceria abrasive Slurry
Venu. at el. CMPUGM AVS Jul. 11, 2016, Austin USA
Soft Pad Effect on Microscratch
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Soft pad
Soft pad
Microscratch Trend Post CMP Pad Thickness: Planarity
Removal Rate: ~10% drop
Microscratch reduction can be achieved by soft pad
implement, however, planarity and removal rate
degraded either (this is reported many times in
different conferences, publications, and business
reports). For the soft pad application, proper pad
conditioning is necessary to maintain polishing
performances.
Soft pad
Venu. at el. CMPUGM AVS Jul. 11, 2016, Austin USA
Process Scheme for Microscratch Reduction
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CMP: Scratch generating process and scratch removal process as well!
Non-selective buffing CMP help to scratch reduction selectivity and uniformity control is challenge for this application
Venu. at el. CMPUGM AVS Jul. 11, 2016, Austin USA
GLOBALFOUNDRIES Confidential 12
GLOBALFOUNDRIES Confidential 12
Advantages of CVD Tip Formation
Guaranteed Quality
No Design Limitation : tip to tip distance, Tip height
distribution, etc.
Can control pad surface roughness and polishing Debris
Tip Height Control
H1(HA-HB), H2(HB-HC) controlling
H1 H2 A C B C A
3D Patterning
Conditioner Design Change to improve scratches
Working with SHINHAN Diamond & 3M
JI Chul Yang, 60th KCMPUGM, Suwon, South Korea, 2015
Strategies for Scratch Mitigation
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• Soft Pad w/ Proper
Conditioning
• Ultrafine Abrasive Particle
• Recipe Optimize (Low
Down Force, Slurry Flow)
• Cleaner Brush Treatment
• CMP Friendly Process
Scratch SOLELY can be minimized?
GLOBALFOUNDRIES Confidential 14
In-Wafer Uniformity (iAPC)
Challenges of CMP Process
Removal rate drop as pad life (removal rate stability)
Incoming height variation: variation in multiple upstream
processes add up
CMP loading effect on removal rate
- Polishing rate is not constant
- Sinusoidal removal behavior observed
- Early stage of polishing (< 10s) is not predictable
iAPC: Integrated Advanced Process Control
Implement of on-board metrology
In-situ Metrology
CMP
http://blog.nus.edu.sg/me4105precisionengineering2
012/types-of-metrology-equipments/
+
iAPC Algorithm and Process Sequence
• Polishing time set by self-learning process: Empirical
RW removal rate set
RW time cal. Post thickness
- target RW time adjusted
RW removal rate reset
Feedback to the next rework
Main CMP
On board Metro
Rework CMP
Rework time adjusted
Out of target
On target
Hong Jin Kim, at el. TechConnect June. 14-17 Washington, DC, USA
Without iAPC With iAPC
• Incoming process variability CMP needs to accommodate and compensate it and tight gate height control in-situ (or real time) process control improve wafer to wafer variation
Gate Height Control with iAPC
Hong Jin Kim, at el. TechConnect June. 14-17 Washington, DC, USA
● >50% Reduction in raw level delta to target (contact height)
Contact W CMP with iAPC
Contact CMP
Contact height
Hong Jin Kim, at el. TechConnect June. 14-17 Washington, DC, USA
Cu CMP with IAPC
GLOBALFOUNDRIES Confidential 20
WTW Rs control demonstrated and in use
Need further WID/WIW/WTW enhancement
Endpoint improvements (On-platen / In-situ?)
Cu CMP
Example of Rs control by iAPC
Without integrated APC With integrated APC
With integrated APC
[Invited Talk] Ji Chul Yang, 60th anniversary Korean CMP User Group
Meeting , “Defect Reduction of CMP process in Logic Device” Suwon, Korea,
Nov.5.2015.
In-situ Cu height control with Barrier EPD and Dielectric removal amount control
2. Dielectric removal amount
control with
in-situ optical sensor
1. Cu CMP
2. Barrier
CMP Start
2-1. Barrier
Clear
In-situ monitoring flow
2-2. Dielectric
Removal Amount
Control
1. Cu CMP - > Cu clear + O.P.
Ji Chul Yang, at el. ICPT2015, 2015. Sep. 30 – Oct. 2, Arizona, USA
GLOBALFOUNDRIES Confidential 22
Cleaner Defect
Cu CMP Defect – lots of cleaner defect type
GLOBALFOUNDRIES Confidential 23
Ring Scratches
Organic Residue
Brush Particle
Cu Flake
Recipe Test
GLOBALFOUNDRIES Confidential 24
- Recipe is major driven solution for CMP defect
GLOBALFOUNDRIES Confidential 25 GLOBALFOUNDRIES Confidential 25
No Treatment
With Treatment
Brush Surface Modification
Working with Rippey
Changing profile by different Process condition
GLOBALFOUNDRIES Confidential 26
Cu Protrusion
Tool Configuration for effective cleaning
GLOBALFOUNDRIES Confidential 27
Typical Brush
Particle Size
Rem
oval E
ffic
iency
Two Fluld Jet
Pencil Brush
Mag Tank & IPA Dryer
Target 100 %
Performance
[Invited Talk] Ji Chul Yang, 60th anniversary Korean CMP User Group
Meeting , “Defect Reduction of CMP process in Logic Device” Suwon, Korea,
Nov.5.2015.
In Conclusion,
• Fundamental Studies Structures & Materials
• Defect-Preventive “Selectable” Selectivity Process Design
• Advanced Diagnostics Manufacturing-Friendly
(FDC, SPC sensor) Equipment Design
• Defect Management The Next “Silver Bullet”
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