N. C. Wang
Graphene Interconnects for 7- and 5-nm Technology NodesNing C. Wang1, Chi-Shuen Lee1, Chris D. English1
,
Saurabh Sinha2, Brian Cline2, Greg Yeric2,
H.-S. Philip Wong1, Eric Pop1
ORNL Beyond CMOS 2017 Workshop
11-30-2017
1Dept. of Electrical Engineering, Stanford University, Stanford, CA 943052ARM Inc., Austin, TX 78735
N. C. Wang
Ex
aB
(Billio
ns
of
GB
)
0 4
0K
2006 Year 2020
Unstructured dataWide variety & complexity
“Swimming in sensors, drowning in data”
• Mine, search, analyze data in near real-time
• Data centers, mobile phones, robots
Abundant Data Explosion
Source: H.-S.P. Wong (Stanford)
N. C. Wang 2
ENERGY
CV
I
2CV
L W
Device Level (“Bottom Up”)
System Level (“Top Down”)
Fabrication
restrictions
Device
models
System
requirements
Gate-level
performance
CMOS Inverter
“Good”
Design
A Circuit Designer’s Perspective
CMOS Design Window
Devices do not exist by themselves but as part of a system
N. C. Wang 3
Intel performance counter monitors 2 CPUs, 8-cores/CPU + 128GB DRAM
Compute Memory
Abundant-data applications: Energy measurements
5%
95%
18%
82%
Genomics Natural Language Processing
Source: S. Mitra (Stanford)
Huge Memory Wall: Processors, Accelerators
N. C. Wang 4
Increasing Interconnect Resistance
0
0.1
0.2
0.3
0.4
0
100
200
300
400
5 10 15 20 25 30 35
Cw
ire(fF
/μm
)
Critical Dimension (nm)
Rvia
(Ω/v
ia),
R
wir
e(Ω
/μm
)
C.-S. Lee, H.-S.P. Wong, et al., IEDM 2016
• Cu wire and via resistances increase rapidly with scaling
• Affects all aspect of system design (speed, area, power)
↓Ion
↑ Delay
↑ Repeaters
↑Energy, Area
N. C. Wang 5
Wire Limited Memory Performance
Resistive wires limit operating margins, energy
efficiency, and speed
Wire Width (nm)
wire width
J. Liang, H.-S.P. Wong, et al., ACM Journ. on Emerg. Tech. in Comp. Sys.,9,1 (2013).
Rj
Rj – Wire Resistance per Junction (Ω)
Wire Width =
Wri
te M
arg
in (
Vaccess/V
dd)
selected cell
N. C. Wang 6
Wire Limited Compute PerformanceD
ela
y
Length
• Local wire parasitics limit circuit performance
• FinFET specific parasitics further restrict performance
Ring Oscillator Delay Decomposition
20 16 14 10 710
Node (nm)
Interconnects
FinFETs
S. Sinha et al., ISLPED 2012
N. C. Wang 7
Grain
Boundary
Scattering
Side Wall
Scattering
Low-k
Diel.Cu
Copper (Cu) Resistivity vs. Linewidth
Local interconnect resistivity dominated by “size effects”
Bulk Resistivity
Li, JES-06
Pyzyna, VLSI-15
Sun, PRB-10
Roberts, IITC-15
Steinhögl, PRB-02
Side Wall
Grain
Boundary
Cu Interconnect
Cross Section
N.C. Wang, E. Pop, et al., IEEE IITC 2017
N. C. Wang 8
Resis
tivity (
µΩ
-cm
)
Graphene (Gr) vs. Cu Resistivity
[1] D. Kondo et al., IEEE IIITC 2012 [2] N.C. Wang et al. IEEE DRC 2012
Cu
Gr [2], ρmid
Gr [2], ρlow
ρGr < ρCu below ~40 nm due to:
1) Lower bulk resistivity
2) Reduced edge scattering
Doped Graphene [1]:
ρlow = 1.5×10-6 Ω-cm
ρmid = 4×10-6 Ω-cm
Linewidth (nm)
Graphene with
FeCl3 intercalation,
D. Kondo [1]
N. C. Wang 9
Graphene Interconnect Technologies
FeCl3
WH =
5,10,
20 nm
+ ↑ Line width
+ ↓ Liner resistivity
+ Enhanced reliability [1]
+ Exp. Demonstrated [1]
+ Doped ρGr < ρCu,W
+ Cpara. suppression
+ Planar processing
- CMOS compatibility
Horizontal
Graphene
Graphene Based
Cu Liner
Performance Impact
Feasibility
[1] L. Li, H.-S.P. Wong, et al., 2016 IEDM
TaN
Cu
W
H =
2W
TaN
Atomically thin sheet
of carbon
(thickness = 0.34 nm)
Suppressed “size effect”
(ρGr < ρCu)
Graphene
High breakdown current
(>100x Cu)
Gr
N. C. Wang 10
Rapid Benchmark Methodology
MO
LB
EO
L Gra
ph
en
e
Parasitic
Extraction
Timing
Layer Width
M1 16 nm
M2-3 18 nm
ARM Figure of
Merit (FOM)
7-nm Back End-of-Line
(BEOL) Specification [1]:
[1] L.T. Clark, G.Yeric, et al., Microelec. Journ., 53, 105 (2016).
IN
…
…
…
INV
NAND
NOR
G
TS
S
TS
S D
CA CB CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
Standard Cell
Timing
N. C. Wang 11
FOM Results (7-nm Gr Technologies)
1L
3L
VDD = 0.7 V
1L
3L
ρlo
w
Cu Baseline
Liner
Horizontal
Energy Delay Product (EDP):
ρlow
(5 nm)
ρmid
(10 nm)
ρlow
(10 nm)
ρlow
(20 nm)
ρmid
(20 nm)
ρm
id
ρlo
w
ρm
id
ρlo
w
~30%
5 nm10 nm20 nmClock Frequency (%)
2
( )AVG Delay Delay
AVG Delay
EDP Energy
t
P t
Delay
P t
N.C. Wang, E. Pop, et al., IEEE IITC 2017
ED
P (
%)
Cu B
aselin
e
N. C. Wang 12
ARM Core Synthesis, Place, and Route
Standard Cell
Library
Functional
Description
Parasitic
Extraction
Fabrication
Constraints
Conduct full-chip synthesis, place, and route for realistic performance projections
Synthesis, Place,
and Route
G
TS
S
TS
S D
CA CB CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
D
CLK
Q
Q’
M4 M4
Optimize: Power,
Area, Speed
N. C. Wang 13
ARM Core Synthesis, Place, and Route
Automatically optimize layout for power given performance and area targets by adjusting routing and cell sizing
If
CV
Target Frequency
Ac
tua
l F
req
ue
nc
y
Low Performance Design
High Performance
Design
Larger cells↑I ↑Frequency
N. C. Wang 14
Full Core Study – 7-nm Technology
MO
LB
EO
L
G
TS
S
TS
S D
CA CB CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
G
TS
S
TS
S D
CA CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
CBCB
G
TS
S
CA CA
V0 V0 V0
TS
S
M1 M1
V1 V1
M2 M2
D
V2 V2
M3 M3
…
Baseline MOL Only
MOL and BEOL
G SS D
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
CB
TS
CA CA
V0 V0 V0
TS
BEOLOnly
[1] L.T. Clark, G.Yeric, et al., Microelec. Journ., 53, 105 (2016).
• Maximize performance: Gr restricted to M1-M3, VDD = 0.7V,
sweep target clock freq.
• Assess MOL and BEOL impact on performance
7-nm Tech. Specs [1]:
LayerWidth
(nm)
Pitch
(nm)
M8 40 80
M6-7 32 64
M4-5 24 48
M2-3 18 36
M1 16 36
N. C. Wang 15
0
0.2
0.4
0.6
0.8
1
0.5 0.7 0.9 1.1
Full Core (7-nm) – Clock Frequency
Pow
er
(a.u
.)
Clock Frequency (a.u.)N.C. Wang, E. Pop, et al., IEEE IITC 2017
7-nm Tech. Specs:
LayerWidth
(nm)
Pitch
(nm)
M8 40 80
M6-7 32 64
M4-5 24 48
M2-3 18 36
M1 16 36BEOL
G SS D
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
CB
TS
CA CA
V0 V0 V0
TS G
TS
S
TS
S D
CA CB CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
MOL &
BEOL
Baseline MOL
G
TS
S
TS
S D
CA CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
CB
CB
G
TS
S
CA CA
V0 V0 V0
TS
S
M1 M1
V1 V1
M2 M2
D
V2 V2
M3 M3
• 5% frequency increase or 9% power reduction
~8% energy delay product (EDP) improvement
−9%
+5%
N. C. Wang 16
Full Core (7-nm) – Wire Utilization
Graphene Layers
Cu
Gr (H =
20 nm)
Non-optimal graphene to Cu transition (M3M4)
Area Utilization (%) =𝑀𝑒𝑡𝑎𝑙 𝑃𝑖𝑡𝑐ℎ × 𝑈𝑡𝑖𝑙𝑖𝑧𝑒𝑑 𝐿𝑒𝑛𝑔𝑡ℎ
𝑇𝑜𝑡𝑎𝑙 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 𝐴𝑟𝑒𝑎G
TS
S
TS
S D
CA CB CAV0 V0 V0
M1 M1V1 V1M2V2 V2M3 M3V3 V3
M4 M4
Via (V)
Interconnect (M)
Via
Count
[A.U
.]
Cu Gr
30
20
10
0V1V1
V2V2
V3V3
Interconnect
& Device
Cross Section
M2
N.C. Wang, E. Pop, et al., IEEE IITC 2017
N. C. Wang 17
• Asses n = 20 slowest (i.e. critical) data paths
• Reliance on M4 suppresses Gr (M1-M3) improvement
Full Core (7-nm) – Wire Delay Decomposition
V1M2
V2M3
M1M1V0CA
TSTS
M4
CAV0
V1M2
V3
V2M3
V3
Cross-SectionNOR2 NAND2
Net
Cross-Section
In Out
Data Path
NAND2
CellNet
NOR2
Cell
M2
M3
M4
M5
M6
M7
M8
N. C. Wang 18
Full Core Study – 5-nm Technology Details
G
TS
S
TS
S D
CA CB CAV0 V0 V0M1 M1V1 V1M2V2M3 M3V3 V3M4 M4
V2
0
1
2
3
0.4 0.8 1.2 1.6
En
erg
y/C
ycle
(a
.u.)
Clock Frequency (a.u.)
0.6 V
VDD=0.5 V
0.7 V
0.8 V
0.9V
PreferredCorner
C.-S. Lee, H.-S.P. Wong, et al., IEDM 2016
• Exploratory study: full Gr replacement full height, adjust
VDD, FET structure (LCON, LEXT), and target clock frequency
• Deeper dive into design and tool optimizations
M2
V4M5
V5M6
V6 V6 V6M7
5-nm Tech. Specs:
LayerWidth
(nm)
Pitch
(nm)
M6-7 24 48
M4-5 18 36
M1-3 12 24
N. C. Wang 19
• MLG: 60-70% lower Rwire compared to Cu
• Gr wire impact greater than at 7-nm, but less than expected
0.5
1
1.5
2
0.6 0.8 1 1.2 1.4 1.6
Energ
y/C
ycle
(a.u
.)
Clock Frequency (a.u.)
Cu
MLG
−16%
+9%
VDD: 0.5-0.8V
Assume same Rvia
Full Core (5-nm) – Clock Frequency
C.-S. Lee, H.-S.P. Wong, et al., IEDM 2016
5-nm Tech. Specs:
LayerWidth
(nm)
Pitch
(nm)
M6-7 24 48
M4-5 18 36
M1-3 12 24
N. C. Wang 20
Full Core (5-nm) – Delay Contribution of Rwire+Rvia
• Rwire + Rvia contribute to 20-30% critical path (n = 20) delay in optimized designs.
0%
10%
20%
30%
40%
50%
0.4 0.6 0.8 1 1.2 1.4
% o
f R
wir
e+
Rvia
in C
ritical P
ath
Dela
y
Clock Frequency (a.u.)
90%
VDD: 0.5-0.8V
151 samples
Post timing closure
Cu
MLG
C.-S. Lee, H.-S.P. Wong, et al., IEDM 2016
N. C. Wang 21
Full Core (5-nm) – Wire vs. Transistor Resistance
• RFET ≡ VDD/ION (3-fin, VDD=0.6 V, IOFF=1 nA/μm, ρCON=2×10-9 Ω-cm2 )
• Wire: Cu + 2-nm barrier, aspect ratio = 2
0
2
4
6
8
10
12
0 10 20 30
FE
T,
Wire R
esis
tance
(kΩ
)
Wire Length (μm)
INV_X1*(Low Ion)
INV_X8(High Ion)
23 μm
M2
M4
M6
*X: number of fingers in a cell
If
CV
C.-S. Lee, H.-S.P. Wong, et al., IEDM 2016
N. C. Wang 22
Full Core (5-nm) – Impact of Rwire on Area
Lower Rwire Less buffers, less wide/fat metal wires
Less via count (less congestion), smaller die area!
4
5
6
0.7 0.8 0.9 1 1.1
Tota
l V
ia N
um
ber
(a.u
.)
Clock Frequency (a.u.)
– 5-10%
VDD: 0.6V
4
5
6
0.7 0.8 0.9 1 1.1Tota
l C
ell
Are
a (
a.u
.)
Clock Frequency (a.u.)
– 5-10%
CuMLG
Cu
MLG
MLG: 60-70% lower Rwire vs. Cu at 5-nm
C.-S. Lee, H.-S.P. Wong, et al., IEDM 2016
N. C. Wang 23
• Graphene may offer three-fold benefit:
• Reduced size-effect at narrow linewidths (ρ↓)• Improved aspect ratio (C↓)• Liner reduction/elimination
• Graphene interconnects at system level:
• Up to ~30% EDP improvement • 9% higher speed or 16% lower energy consumption
• Routing optimization can improve local Rwire impact• Requires place-and-route to see the effect• Consider utilizing area instead of performance
improvement
Graphene Interconnect Conclusions
N. C. Wang 24
Thanks!
N. C. Wang 25
Wire Limited Memory Performance
Wire Width (nm)
10KΩ
100KΩ
J. Liang, H.-S.P. Wong, et al., ACM Journ. on Emerg. Tech. in Comp. Sys.,9,1 (2013).
Static, Ron = 1KΩ
N. C. Wang 26
Cu vs. Ru vs. Co vs. Gr
(a) (b)
Cu
Ru
Co
Gr(mid)
Gr(low)
hRMS = 2 nm hRMS = 0.5 nm
“Low”
Roughness
Realistic
Roughness
Cu Ru Co Gr
λMFP [nm] 39 4.8 7.77 30
λF [nm] 0.46 1.09 2.85 4
ρ [µΩ-cm] 1.68 7.8 6.2 1.5 (low), 4 (mid)
Cu
Ru
Co
Gr(mid)
Gr(low)
N. C. Wang 27
Why Graphene Interconnects?
Scattering specularity (2D model): 𝑝 𝜃 ∝ exp− 4𝜋𝑅𝑟𝑜𝑢𝑔ℎ/𝜆𝐹2
(λF,Gr > λF,Cu better edge roughness immunity)[1] N. Wang, E. Pop et al., 2012 IEEE DRC. [2] D. Kondo, N. Yokoyama, et al., 2014 IEEE IIITC.
Cu
Gr, ρmid
Gr, ρlow
Gr (2D Model [1])
Rrough,edge 2 nm
λMFP 30 nm
λF,Gr 4 nm
ρlow 1.5×10-6 Ω-cm [2]
ρmid 4×10-6 Ω-cm [2]
Cu (FS-MS Model)
Rcu 0.72
ρcu 1.68 × 10-6 Ω-cm
AR 2
pcu 0.8
λMFP,cu 39 nm
λF,Cu 0.46 nm
Model Parameters
Graphene
N. C. Wang 28
𝜌0𝜌𝑟𝑜𝑢𝑔ℎ
= 1 −6𝜆𝑀𝐹𝑃
𝜋𝑊න
0
Τ𝜋 2
cos2 𝜃 sin2 𝜃 𝑑𝜃 න
0
Τ𝜋 2
sin𝜓
1 − exp − 4𝜋h/λFermi2 sin2 𝜃 sin2𝜓 1 − exp −
2𝑊 sin𝜓𝜆𝑀𝐹𝑃 sin 𝜃
1 − exp − 4𝜋h/λFermi2 sin2 𝜃 sin2𝜓 exp −
2𝑊 sin𝜓𝜆𝑀𝐹𝑃 sin 𝜃
𝑑𝜓
Resistivity Equations
𝜌0𝜌𝑟𝑜𝑢𝑔ℎ
= 1 −2𝜆𝑀𝐹𝑃
𝜋𝑊න0
𝜋
𝑑𝜃 sin2 𝜃 cos𝜃 ሻ1 − 𝑝(𝜃 −ሻ1 − 𝑝(𝜃ሻ 2ex p( − Τ𝑊 𝜆𝑀𝐹𝑃 cos𝜃
ሻ1 − 𝑝(𝜃ሻex p( − Τ𝑊 𝜆𝑀𝐹𝑃 cos 𝜃
p(θ)=exp[-(4πh/λFermi)2cos2θ]
Sambles-Soffer (2D)
Sambles-Soffer (3D)
FS-MS (3D)
𝜌 = 𝜌0 ൘1
3
1
3−𝛼
2+ 𝛼2 − 𝛼3ln 1 +
1
𝛼+3
8𝐶 1 − 𝑝
1 + 𝐴𝑅
𝐴𝑅
𝜆𝑀𝐹𝑃
𝑊
𝛼 =𝜆𝑀𝐹𝑃𝑅
𝑑(1 − 𝑅ሻ
𝜆𝑀𝐹𝑃 = mean free path C = fit parameter R = reflectivity coefficient
AR = aspect ratio W = width p = specularity coefficient
d = grain boundary dis. h = RMS edge roughness
Where:
N. C. Wang 29
Lumped Model Analysis
Pitch
(nm)
wMin
(nm)
h
(nm) AR RC/L2
Graphene
(ρLow)
M1-3 36 18 20 1.11 8.08E-03
M4-5 48 24 20 0.83 5.68E-03
M6-7 64 32 20 0.63 4.35E-03
Cu
M1-3 36 18 38 2.11 1.53E-02
M4-5 48 24 52 2.17 5.04E-03
M6-7 64 32 68 2.13 2.44E-03
N. C. Wang 30
DISPEL: DevIce-to-System Performance EvaLuation Platform
Physical Design
Standard
Cells
Extracted Netlist
Layout Sizing
Parasitic Extraction
Timing/Power
Characterization
Timing/Power Lib
Transistor
Interconnect
Tech LEF
Synthesis
Cell Placement
DFT
Gate-Level
Netlist
Clock Tree
Synthesis
Signal Routing
RC Extraction
Timing Closure
Static Timing
Analysis
RTLTiming
Constraint
Design-Technology
Co-Optimization
System Power,
Performance, Area
PDK Development
[C.-S Lee, H.-S. P. Wong, IEDM, 2016]
N. C. Wang 31
Graphene Interconnect Technologies
TaN
CuFeCl3
MoO3
W
H = 2WH = 2WW
H =
5,10,
20 nm
TaN
+ ↑ Line width
+ ↓ Liner resistivity
+ Enhanced reliability [1]
+ Exp. Demonstrated [1]
+ Doped ρGr < ρCu,W
+ Cpara. suppression
+ Planar processing
- CMOS compatibility
+ Ultimate “size-effect” immunity
+ Edge contacts
- No known method
- High-k liner (Cpara.)
Horizontal
Graphene
Vertical
Graphene
Graphene Based
Cu Liner
Performance Impact
Feasibility[1] L. Li, H.-S.P. Wong, et al., 2016 IEDM
W
N. C. Wang 32
FOM Results (7-nm Gr Technologies)
1L3L
VDD = 0.7 V
1L
3L
ρlo
wFocus ARM core on horizontal graphene
Cu Baseline
ρmid
ρlow
Vertical
Cu Baseline
Liner
Horizontal
Energy Delay Product (EDP)
ρlow
(5 nm)
ρmid
(10 nm)
ρlow
(10 nm)
ρlow
(20 nm)
ρmid
(20 nm)
ρm
id
ρlo
w
ρm
id
ρlo
w
ρlo
w
ρm
id
~23%
5 nm10 nm20 nmClock Frequency (%)
2
1AVG
CLK
DP Pf
E
N. C. Wang 33
FOM Results – Graphene Liner
~5% performance increase at ~3% power penalty
1Layer
3Layer
Cu
Baseline
H = 2W
W
TaN
TaN
VDD = 0.7 V
1L
ayer
3L
ayer
(%)
(%)
Clock Frequency (%)
N. C. Wang 34
1L
ayer
3L
ayer
HM
20
HL20
HM
10
HL10
HL5
FOM Results – Horizontal Graphene
Horizontal configuration favorable to reduce capacitance
HL20
HL10HM20
W
H = 5,10,20 nm
HL5HM10
L = ρlow (1.5×10-6 Ω-cm)
M = ρmid (4×10-6 Ω-cm)(%
)(%
)
Clock Frequency (%)
N. C. Wang 35
FOM Results – Vertical Graphene
Vertical configuration performance degraded by MoOx liner
HM20
HL5
VL
VM
H =
2W
W
1L
ayer
3L
ayer
HM
20
HL20
HM
10
HL10
HL5
VL
VM
L = ρlow (1.5×10-6 Ω-cm)
M = ρmid (4×10-6 Ω-cm)(%
)(%
)
VDD = 0.7 V
Clock Frequency (%)
N. C. Wang 36
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
0.00 0.20 0.40 0.60 0.80 1.00
En
erg
y D
ela
y P
rod
uc
t (A
.U.)
Normalized Frequency
Baseline Cuh = 20 nm
Graphene
h = 38 nm Graphene
Energy Delay Product
2
1AVG
CLK
DP Pf
E
A ↓R↑,C↓
h = 38 nm
h = 20 nm
A ↑ R↓,C↑
N. C. Wang 37
Critical Path (n = 20) – Wire vs. Cell (7 nm)
Cell
Wire
N. C. Wang 38
Contact Resistance (RC) Impact (7 nm)
RVia
RConductor
RC
Total Via
Resistance
Scenario RC
Baseline, Graphene CV
(Default Cu Via)1x
Graphene LV
(ρC = 2×10-10 Ω-cm2)2x
Graphene MV
(ρC = 2×10-9 Ω-cm2)20x
• Transfer Length Method (TLM) derived contact resistance
• MOL+BEOL: lower maximum frequency, but EDP improvement retained for LV case (MV case fails)
MOL+BEOL Replacement
MOL and
BEOL
G
TS
S
TS
S D
CA CB CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
N. C. Wang 39
Contact Resistance (RC) Impact (7 nm)
• MOL-only case: EDP improvement observed with RC↑
• Fewer buffer insertions (reduced up to 16%) with slower cells
MOL Only Replacement
MOL
Only
G
TS
S
TS
S D
CA CA
V0 V0 V0
M1 M1
V1 V1
M2 M2
V2 V2
M3 M3
CB
RVia
RConductor
RC
Total Via
Resistance
Scenario RC
Baseline, Graphene CV
(Default Cu Via)1x
Graphene LV
(ρC = 2×10-10 Ω-cm2)2x
Graphene MV
(ρC = 2×10-9 Ω-cm2)20x
N. C. Wang 40
Resis
tivity (
µΩ
-cm
)
Gr Resistivity vs. Linewidth
[1] N. Wang, E. Pop et al., 2012 IEEE DRC. [2] D. Kondo, N. Yokoyama, et al., 2014 IEEE IIITC.
Cu
Gr [1], ρmid
Gr [1], ρlow
ρGr < ρCu below ~40 nm due to:
1) Lower bulk resistivity
2) Reduced edge scattering
Doped Graphene [2]:
ρlow = 1.5×10-6 Ω-cm
ρmid = 4×10-6 Ω-cm
λF,Gr = 4 nm > λF,Cu = 0.46 nm
P(θ) = exp[-(4πhRMS/λF)2cos2θ]
Edge specularity (2D model):
Linewidth (nm)
PGr > PCu
Diffuse (P 0) Specular (P 1)
θ θ
N. C. Wang 41
Critical Path – Average Wire Length
M3
M2
M4
Graphene
Graphene
Copper
Copper
Copper
Graphene Technology
M2, M3 and M4 longer (!) with graphene replacement
Avg
Le
ngth
(µm
/in
sta
nce)
Copper
Baseline TechnologyA
vg
Le
ngth
(µm
/in
sta
nce)
Avg
Le
ngth
(µm
/in
sta
nce)
Avg
Le
ngth
(µm
/in
sta
nce)
Avg
Le
ngth
(µm
/in
sta
nce)
Avg
Le
ngth
(µm
/in
sta
nce)
N. C. Wang 42
Critical Path – Graphene vs. Copper, M3
Graphene Technology Baseline Technology
Total Wire
Length
Number of
Instances
Wire length, usage increases proportionally similar avg. length
M3 M3
M3M3
Top Down View Top Down ViewM3
M3
M3M3
M3
Copper
Copper
Graphene
Graphene
N. C. Wang 43
Critical Path – Graphene vs. Copper, M4
Graphene Technology
Number of
Instances
Similar length, but fewer instances longer wires & delays
M4
M4
Top Down View
Baseline Technology
Top Down View
M4
M4M4
M4
Total Wire
Length
Copper
Copper
Copper
Copper
N. C. Wang 44
Critical Path – Delay “Effort”
Assess wire effort with weighed average:
Average Weight
I JM
max Jtot
M
max
I J
Cl
C
lR
R
Where:
M = metal layer (2-8)
RCmax = net resistance and capacitance
ltot = total net length
J = nets in a path
I = total critical paths
N. C. Wang 45
Wire Distribution on Critical Paths
• (∑xRwire,Mx) / RINV_X1 ≈ 17%
0
1
2
3
4
5
6
7
Avg.
Wire L
ength
per
Sta
ge (
μm
)
M2 M3 M4 M5 M6
M2
M3
M2
average
N. C. Wang 46
• High Rwire System performance sensitive to Rvia
• Need more vias for buffering/routing
0.8
1
1.2
1.4
1.6
0 1 2 3 4 5
*Core
ED
P (
a.u
.)
Rvia Multiplier
low Rwire
high Rwire
+24%
+39%
Impact of Via Resistance (5-nm)
C.-S. Lee et al., IEDM 2016
RVia
RConductor
RC
Rvia
RV
Rwire
