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GUSTECH presents:
A micro-Course on
SPI 4 Ultra-320
Micro-Course on Ultra320; GUSTECH; v4 July 2003
2
Ultra-320 Topics
• Overview of U320 & T10 Documents
• Inquiry Information
• PPR Message & Negotiation Details
• Physical Interface Enhancements •
A few details on Training & Flow Control
• Information Units Update
• A few Mode Pages
Assumes w
orking
knowledge of all p
rior
SCSI tech
nology
Micro-Course on Ultra320; GUSTECH; v4 July 2003
3
U320 Main Features & T10
• Doubles transfer rate of U160 (SPI-3) via:
• Bus signaling enhancements
• Implementation of Information Units and addition of optional Read Streaming
• Implementation of Quick Arbitration
• Many others
• Project 1365D• This document is based upon
SPI-4, revision 10; 6 May 02
• Also refer to SAM, SPC, and appropriate Device Specific Command Documents
Micro-Course on Ultra320; GUSTECH; v4 July 2003
4
Inquiry Information“Who are you & what do you do?”
• SPI-4 Version Descriptor Codes:– 0B40 no version claimed
– 0B56 ANSI INCITS.362.200x
– 0B54 T10/1365D rev 7
– 0B55 T10/1365D rev 9
– 0B59 T10/1365D rev 10
Byte(s) Inquiry data (field, function)
6 ADDR16 in bit 0, and others
7 WBUS16, SYNC, and others
56 ST/DT Clocking, QAS & IUS
58 & 59 SAM compliance Descriptor Code
60 & 61 SPI compliance Descriptor Code (SPI-4)
62 & 63 “Protocol” compliance Descriptor Code
64 & 65 SPC compliance Descriptor Code (SPC-3)
66 & 67 Device Command Set code (SBC-2)
68 & 69 Version Descriptor Code #6
70 & 71 Version Descriptor Code #7
72 & 73 Version Descriptor Code #8Reference SPC-3, rev. 8,
tables 57 & 63
Micro-Course on Ultra320; GUSTECH; v4 July 2003
5
Inquiry Information“Who are you & what do you do?”
Byte(s) Inquiry data (field, function)
6 ADDR16 in bit 0, and others
7 WBUS16, SYNC, and others
56 ST/DT Clocking, QAS & IUS
58 & 59 SAM compliance Descriptor Code
60 & 61 SPI compliance Descriptor Code (SPI-4)
62 & 63 “Protocol” compliance Descriptor Code
64 & 65 SPC compliance Descriptor Code (SPC-3)
66 & 67 Device Command Set code (SBC-2)
68 & 69 Version Descriptor Code #6
70 & 71 Version Descriptor Code #7
72 & 73 Version Descriptor Code #8Reference SPC-3, rev. 8, tables 64, 65 & 66
• ADDR16=1 supports ID[15:0]
• WBUS16=1 supports DB:15:0]
• SYNC=1 supports synchronous data
transfers
• CLOCKING=11 supports
both ST & DT transfers
• QAS=1 supports Quick Arbitration
and Selection
• IUS=1 supports Information Unit
transfers
Micro-Course on Ultra320; GUSTECH; v4 July 2003
6
Parallel Protocol RequestBIT
BYTE7 6 5 4 3 2 1 0
0 Extended Message (01h)1 Extended Message (additional) Length (06h)2 Parallel Protocol Request (04h)3 Transfer Period Factor = 08h for “Fast-160”
Note: Fast-160 data is latched every 6.25nS
4 reserved
5 REQ/ACK OFFSET6 Transfer Width Exponent = 1 for WIDE7 PCOM
P_ENRTI RD_ST
RMWR_FL
OWHOLD_
MCSQAS_R
EQDT_RE
QIU_RE
Q
Reference SPI-4, rev. 10, table 71
Remember: DT is
WIDE only, always
Remember: REQ/ACK OFFSET = 0 means Asynchronous
Micro-Course on Ultra320; GUSTECH; v4 July 2003
7
Parallel Protocol Request details
• Precompensation enable• Retain training
information• Read streaming and read
flow control enable• Write flow control
enable
• Hold margin control settings
• QAS enable request
• DT clocking enable request
• Information units enable request
BIT
BYTE7 6 5 4 3 2 1 0
7 PCOMP_EN
RTI RD_STRM
WR_FLOW
HOLD_MCS
QAS_REQ
DT_REQ
IU_REQ
Reference SPI-4, rev. 10, table 9
Micro-Course on Ultra320; GUSTECH; v4 July 2003
8
Parallel Protocol Request details
• Precompensation enable=1 (set by “OTHER” SCSI device) indicates that the device
receiving this bit set to ‘1’ should enable its Precompensation Transmitters (CONTROL BIT)
• Retain training information=1 device can save Training Information and the Target does
NOT need to retrain on each connection
• Read streaming and read flow control enable=1 Target should enable
read streaming and read flow control
• Write flow control enable=1 Target should enable write flow control during write
streaming
BIT
BYTE7 6 5 4 3 2 1 0
7 PCOMP_EN
RTI RD_STRM
WR_FLOW
HOLD_MCS
QAS_REQ
DT_REQ
IU_REQ
Reference SPI-4, rev. 10, sections 4.12.4.6.6 through 4.12.4.6.9
Micro-Course on Ultra320; GUSTECH; v4 July 2003
9
Parallel Protocol Request details
• Hold Margin Control Settings=1 target should hold any margin control settings with the margin control subpage of the port control mode page
• QAS enable request=1 is a request that Quick Arbitration and Selection be enabled
• DT clocking enable request=1 is a request that DT clocking be enabled
• Information Units enable request=1 is a request that Information Unit Transfers be enabled
BIT
BYTE7 6 5 4 3 2 1 0
7 PCOMP_EN
RTI RD_STRM
WR_FLOW
HOLD_MCS
QAS_REQ
DT_REQ
IU_REQ
Reference SPI-4, rev. 10, sections 4.12.4.6.2 through 4.12.4.6.5
Any change in the negotiated state of IU_REQ, the target shall: Abort all tasks for that initiator and go to BUS FREE phase
Micro-Course on Ultra320; GUSTECH; v4 July 2003
10
Parallel Protocol Request details
• VALID Combinations when Transfer Period=08h:• PCOMP_EN = 0 or 1; RTI = 0 or 1; RD_STRM = 0 or 1; WR_FLOW = 0 or 1;
• HOLD_MCS = 0 or 1; QAS_REQ = 0 or 1; DT_REQ=1; IU_REQ=1
BIT
BYTE7 6 5 4 3 2 1 0
7 PCOMP_EN
RTI RD_STRM
WR_FLOW
HOLD_MCS
QAS_REQ
DT_REQ
IU_REQ
Reference SPI-4, rev. 10, table 11
Remember: DT is WIDE only, always
Remember: REQ/ACK OFFSET = 0
means Asynchronous
Any change in the negotiated state
of IU_REQ, the target shall: Abort
all tasks for that initiator and go to
BUS FREE phase
Micro-Course on Ultra320; GUSTECH; v4 July 2003
11
pre-U320 Data Clocking
20h 39h 15hDEh 05h 3Ch 69hF7h
DB[7-0], drivenby Target or
Initiator
Single Transition Data Phase on Narrow Bus
P0 = Odd Parity
REQ or ACK
9683h 31D0h 6931h03FBh 9655h fill CRCCRC
Double Transition Data Phase on Wide Bus with CRC “available”
P_CRCA = parity or CRC
Available
DB[15-0], drivenby Target or
Initiator
REQ or ACKU160’s Data Group Transfers example
Reference SPI-4, rev. 10, figure 5
DT DATA IN shown
Micro-Course on Ultra320; GUSTECH; v4 July 2003
12
Double Transition PACING
DB[15-0], driven
by Target orInitiator
REQ or ACK
Reference SPI-4, rev. 10, figure 8
View at the transmitting device
It is up to the receiving device
to “adjust” all signals to match
synchronous DT DATA
waveforms as depicted on the
bottom of slide 11Let’s see how this is made possible…
6.25nS
12.5nS 80MHz
Micro-Course on Ultra320; GUSTECH; v4 July 2003
13
Double Transition PACING details
View at the transmitting device
View at the receiving device
REQ or ACK
“any” DBx
“any” DBy
“any” DBz
REQ or ACK
“any” DBx
“any” DBy
“any” DBz
Waveforms
Signal rounding
Amplitude reduction
Signal skew
Micro-Course on Ultra320; GUSTECH; v4 July 2003
14
Double Transition PACING details
Reference SPI-4, rev. 10, figure 9
Playing Pieces
LVD Transmitters
Precompensated Drivers
mux
muxData
CRC
Buf
fer
This is only a partial model; not actual circuitry
Transmitting SCSI DEVICE
Receiving SCSI DEVICE
Optional Signal Adjustment
Skew Compensation
Clock Shifter
Receivers
Buffer
SCSI Bus
Per signal line: If changing states(0 to 1, or 1 to 0) then use
“strong” drive; if not changingstates, use “weak” drive
“open loop compensation”
& Table 32 for Precompensation
Micro-Course on Ultra320; GUSTECH; v4 July 2003
15
Double Transition PACING details
REQ or ACK
“any” DBx
“any” DBy
“any” DBz
Receiver Equalization with FilteringAdaptive Active Filter
Skew Compensation
Clock Shift REQ or ACK
“any” DBx
“any” DBy
“any” DBz
Waveform Restoration
Reference SPI-4, rev. 10, figure 10
TunedTunedwithwith
““trainintrainingg””
Adjustable,
Closed-loop
amplifier
followed by a
Steep-rolloff
Low-pass filter
Micro-Course on Ultra320; GUSTECH; v4 July 2003
16
Double Transition PACING details
DT DATA IN: Initiator’s Receiver Training
Reference SPI-4, rev. 10, Section 10.7.4.2.2
Section A Training: DOG lines = DT Data INSignal group “ALL”=
P_CRCA, P1 & DB[15:0]
200nS= 32 transfers
200nS
800nS = 128 transfersIf PCOMP_EN = 1; strong drive…
SEL
ALL &REQ
If PCOMP_EN = 1; still strong drive…
Section B Training:
ALL
REQ
100nS 300nS= 48 transfers
Since the “ALL” signals are repeating as:11001100110011…
the precompensation drivers will bealternating between strong & weak
Section C Training:
REQ
P1
DB[15:0]& P_CRCA Repeating pattern:
0000010011111011…Total of 8 sets of patterns (only 5 shown)
800nS = 128 transfers
P1 “phase change”will signal valid data
NOTE: See section 10.7.4.2.3 for DT DATA OUT phase training technique
Micro-Course on Ultra320; GUSTECH; v4 July 2003
17
Double Transition PACING details
• P1 is now used to indicate the change of the data validity state by reversing the phase (appears as a lack of a
change in state) of the (normally free running) P1 coincident with REQ or ACK assertion edges (slide 18 example)
• P_CRCA asserts when the current SPI data stream IU is the last SPI data stream IU of the current read or write stream
• Read flow control is mandatory if the optional read streaming is enabled (RD_STRM=1). The mandatory write streaming uses write flow control if enabled (WR_FLOW=1)
Flow Control
Reference SPI-4, rev. 10, Sections 10.7.4.3.1 & 4.11.3.3 & table 39
Micro-Course on Ultra320; GUSTECH; v4 July 2003
18
Double Transition PACING details
DT DATA IN: P1 Data Validity Signaling ex.
Reference SPI-4, rev. 10, Section 10.7.4.3.1, & Figure 79
DB[15:0]
REQ
P1
P1 “phase change”will signal valid data
End of “training”See end of slide 16
P1 “phase change”will signal valid data
P1 “phase change”will signal invalid data
P1 “phase change”will signal invalid data
Micro-Course on Ultra320; GUSTECH; v4 July 2003
19
Double Transition PACING details
• Have explored just some of the techniques used to ensure the highest signal quality possible
• U320 uses CRC32 data integrity checking at the end of each Information Unit to verify the information is correct
Micro-Course on Ultra320; GUSTECH; v4 July 2003
20
Cyclic Redundancy CheckByte 1 Byte 0 Byte 3 Byte 2
Bit: 15 8 7 0 15 8 7 0DATA
TransmissionWide Bus
timeByte 0 Byte 1 Byte 2 Byte 3
Bit: 7 0 7 0 7 0 7 0
Bit: 31 24 23 16 15 8 7 0
Byte 0 Byte 1 Byte 2 Byte 3Bit: 0 7 0 7 0 7 0 7
Bit: 31 24 23 16 15 8 7 0
Bit-Swapon Byte
Boundaries
Bit-Swapon Byte
Boundaries
CRC 0 CRC 1 CRC 2 CRC 3
Bit: 7 0 7 0 7 0 7 0
Bit: 31 24 23 16 15 8 7 0
Bit: 0 7 0 7 0 7 0 7
Bit: 31 24 23 16 15 8 7 0
CRC 0 CRC 1 CRC 2 CRC 3
CRCCalculation
on 32-bitBoundaries
CRCTransmission CRC 1 CRC 0 CRC 3 CRC 2
Bit: 15 8 7 0 15 8 7 0
Wide Bus
CRC Generation followed by Bit (1’s complement) Inversion
Endof
Data
Reference SPI-4, rev. 10, Figure 80
Micro-Course on Ultra320; GUSTECH; v4 July 2003
21
Cyclic Redundancy Check
The 32-bit generator polynomial used, that equals 104C11DB7h is:x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
The 32-bit unique remainder, that equals C704DD7Bh is:
x31 + x30 + x26 + x25 + x24 + x18 + x15 + x14 + x12 + x11 + x10 + x8 + x6 + x5 + x4 + x3 + x + 1
Total Bytes Data Pattern Sent in Data Group Word 1 CRC Word 2 CRC
32 00h, 00h for all words 55ADh 190Ah
32 FFh, FFh for all words AB0Bh FF6Ch
3200h, 01h, 02h, 03h,
04h, ..., 1Fh7E8Ah 9126h
CRC Test Cases:
Reference SPI-4, rev. 10, Section 11.3.4
Micro-Course on Ultra320; GUSTECH; v4 July 2003
22
Quick Arbitration
• Optional method of transferring SCSI bus control without an intervening BUS FREE
• Three step process for implementation:1. Discovery of support of QAS (Inquiry CDB & Data)2. Negotiation for QAS usage (PPR MSGs OUT & IN)3. Execution of QAS via QAS REQUEST message IN
and the new & very unique protocol– Saves approximately 2uS of overhead per unique I/O process– Targets “shall” implement the Fairness Algorithm (see Appendix B)– Problems include “bus starvation”
Reference SPI-4, rev. 10, Section 10.4.3
Micro-Course on Ultra320; GUSTECH; v4 July 2003
23
Quick Arbitration
DB[7-0]T6 55h = QAS REQUEST
REQT6
ACKI7
“DOG”T6 MSG IN Phase
BSYT6
SEL
QAS REQUEST actuatesdisconnection of T=6 from I=7
“logic” levels depicted
HiZ
90nSmax
HiZ
90nS max
HiZ
90nS min, 200nS max
90nS min
25h
T0, T2, & T5Arbitrating
20h
T5 wins quickArbitration
1uS minDecidewinner
HiZT5 drives SEL
HiZ
HiZ
T6 releasesWithin 200nS
T0 & T2 releaseWithin 200nS
NormalRESELphase
followsafter 1uS
delay
Reference SPI-4, rev. 10, Section 10.4.4
? nS
? nS
DT DATA Phase
REQ & ACK not shown for brevity and extreme simplification
Micro-Course on Ultra320; GUSTECH; v4 July 2003
24
Information Units PACKETIZED SCSI
• Method of transferring SCSI bus Information using negotiated Synchronous Transfer rates and Wide bus widths (“shall” use for Pacing U320)
• Three step process for implementation:1. Discovery of support of IU (Inquiry CDB & Data)
2. Negotiation for IU usage (PPR MSG OUT & IN)
3. Execution of Information Units phases using DT DATA IN and DT DATA OUT phases
Micro-Course on Ultra320; GUSTECH; v4 July 2003
25
Packetized SCSI details
• Four types of SPI Information Units:1. L_Q = contains L_Q NEXUS information for existing I_T NEXUS and is always
paired with one of the following:
2. COMMAND = single, last or multiple commands with task attributes and
management flags (messages) for unique I_T_L_Q NEXUS;
3. DATA = DT DATA IN, DT DATA OUT, DT STREAM DATA
IN, and DT STREAM DATA OUT for unique I_T_L_Q NEXUS;
4. STATUS = auto-sense data with status, and packetized failure codes for
unique I_T_L_Q NEXUS.
Reference SPI-4, rev. 10, Section 14.1 & others cited above
Section 14.3.2
Section 14.3.1
Section 14.3.3
Section 14.3.4
Section 14.3.5
Micro-Course on Ultra320; GUSTECH; v4 July 2003
26
Packetized SCSI more details
SPI Information Unit “normal progression”
SPI L_Q IU
SPI L_Q IU
SPI L_Q IU
Establish I_T NexusArbitration/Selection
CompletesNexus:
I_T_L_Q
SPI COMMAND IU
SPI DATA IU
SPI STATUS IU
Includes Task Attributes andManagement Flags; single,multiple & last commands
Includes DATA IN andDATA OUT, STREAMING DATA IN, and STREAMING DATA OUT
Includes “Auto-sense” =Error sense data, and
Packetized failure codesNOTE: All four IU types terminate their transfers with iuCRC (described earlier), which can also occur at specified intervals in the transfers. Reference slide 20.
Paired
with:
Paired
with:
Paired
with:
If more commands
If more data
If more data or status
Micro-Course on Ultra320; GUSTECH; v4 July 2003
27
Packetized SCSI more details
• After I_T NEXUS, “logical” connections, disconnections and reconnections are used, changing L_Q values as needed
• Logical disconnections SHALL occur (back to just the I_T NEXUS) at the completion of any:
1. Each SPI command IU2. Each SPI status IU3. Each SPI data IU4. Any SPI L_Q if data length = zero; and5. The last SPI data stream IU
– if there are no phase changes to MSG OUT or MSG IN– If a change to MSG IN or OUT occurs, then existing
I_T_L_Q NEXUS is maintained
Reference SPI-4, rev. 10, Section 14.2
Micro-Course on Ultra320; GUSTECH; v4 July 2003
28
Packetized SCSI more detailsSPI Information Unit Phase Sequences “overview”
BUS FREE
DTDATA
MESSAGEIN
MESSAGEOUT
RESELECTION SELECTION
ARBITRATION
Hard Reset orProtocol Error
Reference SPI-4, rev. 10, Figure 83
Slides 29 32
Micro-Course on Ultra320; GUSTECH; v4 July 2003
29
Packetized SCSI more details
SPI Information Unit Sequence during initial connectionSELECTION
SPI L_Q(always Init to Targ)
(logical connect)
SPI COMMAND(always Init to Targ)
(logical disconnect)
BUSFREE(unexpected
physicaldisconnect)
BUSFREE
DTDATA
IN
MSGIN
MSGOUT
(physicaldisconnect)
(QAS orWDTR)(to SPI L_Q/DATA or
SPI L_Q/STATUS)
I_T_L_QNexus remains
in place
I_T Nexus coming in
I_T Nexusleaving
I_T Nexusis gone here
Can bemanycommands
Attention Condition
Refe
rence
SPI-
4, re
v. 1
0, Fi
gure
85
Asynchronous Narrow
Micro-Course on Ultra320; GUSTECH; v4 July 2003
30
Packetized SCSI more details
SPI Information Unit Sequence during data type transfers
RESELECTION
SPI L_Q(always Targ to Init)(logical reconnect)
SPI DATA
(logical disconnect)
BUSFREE
DT DATAIN
MSGIN
MSGOUT
(physicaldisconnect)
(to SPI L_Q/DATA orSPI L_Q/STATUS)
I_T_L_QNexus remains
in place
I_T Nexuscoming in
I_T Nexusleaving
Initiator treats as having received a DISCONNECT
MSG IN; I_T Nexusis gone here
(data pointer saved)
(data pointer restored)
DT DATA INfrom SPI STATUS
or DATA
DT DATA OUTfrom SPI COMMAND
or DATA
Attention Condition
DT DATA OUTor DT DATA IN
Refe
rence
SPI-
4, re
v. 1
0, Fi
gure
86
Micro-Course on Ultra320; GUSTECH; v4 July 2003
31
Packetized SCSI more details
SPI Information Unit Sequence during data stream type transfers
RESELECTION
SPI L_Q(always Targ to Init)(logical reconnect)
SPI DATA
(logical disconnect)
BUSFREE
DT DATAIN
MSGIN
MSGOUT
(physicaldisconnect)
(to SPI L_Q/DATA orSPI L_Q/STATUS)
I_T_L_QNexus remains
in place
I_T Nexuscoming in
I_T Nexusleaving
I_T Nexusis gone here
(data pointer saved)
(data pointer restored)
DT DATA INfrom SPI STATUS
or DATA
DT DATA OUTfrom SPI COMMAND
or DATA
Attention Condition
DT DATAIN or OUT
Refe
rence
SPI-
4, re
v. 1
0, Fi
gure
87
Micro-Course on Ultra320; GUSTECH; v4 July 2003
32
Packetized SCSI more details
SPI Information Unit Sequence during status transfers
RESELECTION
SPI L_Q(always Targ to Init)(logical reconnect)
SPI STATUS(always Targ to Init)
(logical disconnect)
BUSFREE
DT DATAIN
MSGIN
MSGOUT
(physicaldisconnect)
(to SPI L_Q/DATA)
I_T_L_QNexus remains
in place
I_T Nexuscoming in
I_T Nexusleaving
I_T Nexusis gone here
(data pointer restored)
MSG OUT
DT DATA OUTfrom SPI COMMAND
or DATA
Attention Condition
DT DATA INfrom SPI DATA
(to QAS)
Refe
rence
SPI-
4, re
v. 1
0, Fi
gure
88
Dat
a L
engt
h =
0(n
o st
atus
fol
low
s)(S
ee S
ecti
on 1
4.3.
5)
Micro-Course on Ultra320; GUSTECH; v4 July 2003
33
Packetized SCSI more details
BYTES: FUNCTION
0 TYPE (of IU following)
1 Reserved
2-3 TAG (like Q-tag)
4-11 Logical Unit Number (four levels)
12 Reserved
13-15 Data Length*
16-17 Reserved
18-19 iuCRC Interval
20-23 iuCRC
CODE: TYPE:
01h Last Command
02h Multiple Command
04h Data
05h Data Stream
08h Status
All others reserved
Table 54 – SPI L_Q IU Table 55 – TYPE
SPI L_Q Information Unit Details
iuCRC Interval is the length in bytes of the data to be sent before an
iuCRC is transferred. If zero, then only one iuCRC shall occur at the end of the SPI Information Unit.
TAG is a 16-bit unsigned integer,(TAG Queue Number)
Four levels of LUN are defined in SAM-2. Single level LUN
(00-FF) is found in Byte 5.
Reference SPI-4, rev. 10, Section 14.3.2
BIDI Direction: byte 16, bits 7 & 6: per SPI-4, rev. 10,
table 56
*Length of IU that follows, including “per stream size”: Initiator’s “comand” data length is 14h 90h.
Micro-Course on Ultra320; GUSTECH; v4 July 2003
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Packetized SCSI more details
SPI COMMAND and DATA Information Units Details
BIT
BYTE7-3 2 1 0
0 reserved
1 reserved Task Attribute
2 Task Management Flags (messages out)
3 Additional CDB Length RDDATA WRDATA
4-19 Command Descriptor Block (CDB) 16-bytes
20-n Additional CDB (if needed – Group 3 CDBs)
N+1->N+4 iuCRC
Table 51 – SPI COMMAND IU
CODE DESCRIPTION:
000b SIMPLE task
001b HEAD of Queue task (BULLY)
010b ORDERED task
011b Reserved
100b ACA task
101b – 111b
reserved
Table 52 – Task Attribute
CODE DESCRIPTION:
00h No task management for task
01h Abort Task (MSG 0Dh)
02h Abort Task Set (MSG 06h)
04h Clear Task Set (MSG 0Eh)
08h Logical Unit Reset (MSG 17h)
20h Target Reset (MSG 0Ch)
40h Clear ACA (MSG 16h)
Table 53 –Task
ManagementFlags
BYTE FUNCTION
0 -> N Data
N+1->N+4 iuCRC
SPI DATA IUTables 57 & 58 in SPI-4
Reference SPI-4, rev. 10, Sections
14.3.1 (command) & 14.3.4 (data)
Remainder of IU ignored
if code is not 00h
NO untagged CDBs
Micro-Course on Ultra320; GUSTECH; v4 July 2003
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Packetized SCSI more details
SPI STATUS Information Unit Details
BIT
BYTE7-4 3-2 1 0
0-1 reserved
2 reserved Reserved for FCP SNSVALID RSPVALID
3 STATUS
4-7 SENSE DATA LIST LENGTH (n-m)
8-11 Packetized Failures List Length (m-11)
12-m Packetized Failures (see Tables 60 & 61)
1+m -> n SENSE DATA
n+1 -> n+4 iuCRC
Table 59 – SPI STATUS Information Unit
BYTES FUNCTION
0-2 reserved
3 Packetized Failure Code
Table 60 – PacketizedFailures Field
CODES DESCRIPTION CODES DESCRIPTION
00h NO failure or Function Complete 04h TASK function not supported
01h Reserved 05h TASK function failed
02h COMMAND IU fields invalid 06h Invalid TYPE code received in L_Q IU
03h reserved 07h Illegal request received in SPI L_Q IU
Table 61 – Packetized Failure Codes
Reference SPI-4, rev. 10, Section 14.3.5
Micro-Course on Ultra320; GUSTECH; v4 July 2003
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Mode Pages for SPI-4• #02:
Disconnect – reconnect page
• #18: Logical Unit Control page
• #19: Port Control page
• #01: Margin Control• #02: Save training
configuration value• #03: Negotiated
Settings• #04: Report transfer
capabilities• #FF: Return all
supported subpages
Reference SPI-4, rev. 10, Section 18.1.1
subPages
Byte 0, Bit 6: SPF=1 for the Subpage format; subpage # is then in byte 1
Micro-Course on Ultra320; GUSTECH; v4 July 2003
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Port Control Mode Page• Margin Control parameters
include:– Driver Strength, Driver
Asymmetry, Driver Slew Rate, & Driver Precompensation.
Saved Training Configuration parameters include 4byte values for each of: DB[15:0], P_CRCA, P1, BSY, SEL, RST, REQ, ACK, ATN, C/D, I/O, and MSG
• #01: Margin Control
• #02: Save training configuration value
• #03: Negotiated Settings
• #04: Report transfer capabilities
• #FF: Return all supported subpages
Reference SPI-4, rev. 10, Sections 18.1.4.2 & 18.1.4.3; & Tables 87 & 89
Micro-Course on Ultra320; GUSTECH; v4 July 2003
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Port Control Mode Page• Negotiated Settings parameters
include: Transfer Period Factor, Req/Ack Offset, Transfer width, protocol options, Transceiver mode, & Sent/Received PCOMP_EN flags
• Report transfer capabilities includes: Minimum transfer period factor, Maximum REQ/ACK Offset, Maximum transfer width exponent, and protocol option bits supported.
• #01: Margin Control
• #02: Save training configuration value
• #03: Negotiated Settings
• #04: Report transfer capabilities
• #FF: Return all supported subpages
Reference SPI-4, rev. 10, Sections 18.1.4.4 & 18.1.4.5; & Tables 90 & 92
Transceiver Mode: 00 = unknown;
01 = Singled Ended; 10 = Low
Voltage Differential; & 11 = High
Voltage Differential
Micro-Course on Ultra320; GUSTECH; v4 July 2003
39
SPI-4 Annex List:• A: Additions needed for
LVD SCSI Drivers and Receivers
• B: SCSI Bus Fairness• C: Nonshielded connector
alternative 4• D: “warm” Plugging• E: SCSI Cable Testing• F: Simple Expander
Requirements• G: Expander
Communication Protocol
• H: Connecting different widths
• I: Transmission lines for SE Fast-20
• J: Measuring SE pin capacitance
• K: SCSI ICONs
• L: Backplane construction guidelines
• M: SPI-4 SCSI-2 terminology mapping
Reference SPI-4