Hello, and welcome to the op amp technology overview, developed by Art Kay, Thomas Kuehl, and Tim Green of TI’s

Precision Op Amps group.

What is the difference between a CMOS, Bipolar, and JFET amplifier? When should you use one over another? When

should you use an amplifier with no input crossover distortion, and what is input crossover distortion? What about Zero-

Drift, Chopper, and auto-zero amplifiers? This presentation will help you understand how to quickly in the select the

right op amp based on technology type.

1

2 2 •2 •2 •2

Texas Instruments offers a wide variety of Amplifiers for your application needs.

We offer High Speed Op Amps (>50MHZ Bandwidth), Low Power Op Amps

(<10uA of quiescent current). In addition we have both low voltage and high

voltage Comparators. Texas Instruments also offers Precision (<1mV input offset

voltage) Op Amps, General Purpose Op Amps (>1mV input offset voltage). For

the Audio applications we also offer Lower Power Audio and Haptics Amplifiers

along with Piezo Drivers. For Medium and High Power Audio we offer both

Linear and Class D type Amplifiers.

In our presentation here we will compare Bipolar op amps versus CMOS & JFET

op amps. In addition the differences between CMOS and JFET will be shown.

We will start first with a reminder of how the different transistors (Bipolar, CMOS,

JFET) operate. The important input op amp parameters of Vos, Ib and Drift of

these key parameters will be defined. Different ways to trim input offset voltage

will be demonstrated. Noise, a key specification for many signal chain designs,

will be compared for JFET, MOSFET, and Bipolar op amps. There are several

types of input structures for op amps which we will compare and contrast.

3

Op amp topologies use one of three different transistor types (Bipolar, CMOS, JFET) for their differential input pairs. A quick reminder of how these transistors behave will help understand the follow-on detailed discussion of op amp types. When the term bipolar, CMOS, or JFET op amp is used it is referring to the type of transistors used in the input differential pair (+/-input ) of the op amp. An NPN bipolar transistor is shown as a current controlled device. Both the CMOS and JFET devices are N-Channel and are voltage controlled devices.

The NPN Bipolar Transistor is a current controlled device. The collector current is equal to the base current times a current high gain factor called hfe. The emitter current is the summation of the collector current and the base drive current. Since hfe is usually high, Ib is small when compared to Ic. Therefore, Ie is about equal to Ic. A bipolar op amp will have transistor bases connected to its inputs and therefore require some drive current into these inputs.

The N-Channel CMOS device is a voltage controlled device. It can be viewed as a voltage controlled resistor in its linear region of operation such that the drain to source resistance or Rds_on is controlled by the gate to source voltage or Vgs. For a typical N-Channel device Vgs=0V turns it off and Vgs > 2V will begin to turn it on. A CMOS op amp will have transistor gates connected to its inputs and therefore require next to no input drive current since it is a voltage controlled device.

The N-Channel JFET device is a voltage controlled device. It can be viewed as a voltage controlled resistor in its linear region of operation such that the drain to source resistance or Rds_on is controlled by the gate to source voltage or Vgs. For a typical N-Channel device Vgs=0V turns it on and Vgs < -2V will begin to turn it off. A JFET op amp will have transistor gates connected to its inputs and therefore require next to no input drive current since it is a voltage controlled device.

4

Here is a general op amp model that can be used for offset and bias current

analysis. The same model is used for CMOS, Bipolar, and JFET amplifiers. The

general equations used to determine the output error voltage from the bias

current and offset voltage are given for reference. Notice that the bias current

will interact with both the feedback network and the source impedance to

translate into an offset voltage. The input offset voltage, Vos, is modeled as an

error voltage in series with the +input. Vos is gained up by the non-inverting

gain of the op amp and appears at Vout as the error term, Vo_vos. The input

bias current on the +input, IB+, flows through the source resistance, Rs, which

creates an input offset voltage which is gained up to Vout as an error voltage,

Voib+. The input bias current on the –input, IB-, flows through the parallel

combination of R1 and RF. Think of Vout as a short for this calculation. IB- times

R1//RF creates an input offset voltage which is referred to the +input and gained

up to Vout as an error term, Voib-. The final error voltage at the output,

Vo_os_ib is the summation of all error terms (Vo_vos, Voib+, and Voib-).

5

This shows a simplified diagram of the inside of the amplifier for both a bipolar

and CMOS amplifier. Here we are focusing on the input stage. Looking at the

bipolar device, the offset voltage is set as the mismatch of the base to emitter

voltage Q1 and Q2. If the transistors are perfectly matched, the Vbe values will

cancel out and offset will be zero. In practical cases, the mismatches generate

an offset voltage in the millivolt range. The resistors Ros1 and Ros2 can be

adjusted (trimmed) so to minimize the offset. In the case of bipolar amplifiers,

the offset drift is directly proportionate to the offset voltage. So trimming Ros1

and Ros2 minimizes both offset and offset drift. The trim of CMOS devices is

more complex. In the case of CMOS devices, offset drift is adjusted by trimming

R1 and R2. Next, the offset is adjusted by trimming Ros1 and Ros2. Thus,

CMOS devices require at least two steps to minimize offset and offset drift, and

in some cases additional iterations are needed.

6

The OPA211 is representative of a high performance operational amplifier that

utilizes the attributes of a modern bipolar transistor technology to provide very

high dc, ac and noise performances. Typically, bipolar based op amps have

usable power supply levels up to 36 V, and sometimes higher. The OPA350 is an

example of a precision CMOS op amp. It is ideally suited for low-voltage, single-

supply applications where high electrical performance is required. Traditionally

CMOS amplifiers have been in the 5V supply and lower. Later we will see some

new generation CMOS op amps that are usable up to 36V.

7

This slide shows the inherent drift of bipolar devices compared to CMOS

devices. In the case of bipolar devices the drift is linear and directly proportional

to the offset. In fact, for each millivolt of offset you will get about 3.3uV/C of

offset drift. So, a device with a 1mV offset would have a drift of 3.3uV/C. CMOS

devices are non linear and their drift can be unpredictable. Trimming CMOS

devices will require a two temperature test and an iterative multi-step trim.

In general, because of the different characteristics of bipolar and CMOS you can

expect to see better offset and offset drift in bipolar devices. This is not always

the case though as some CMOS devices go through a lot of effort to optimize

offset and for some bipolar devices offset may not be optimized. The point is

that it is easer to get low offset and offset drift using a bipolar technology. Later

on we will see some tricks used in CMOS processes to eliminate trim and get

lower offset and drift specifications.

8

This slide shows what a real world laser trim looks like. At the top of the page is

a picture of an op amp die. Each wafer will have many hundreds or perhaps

thousands of die on a wafer. Specifically we show two resistors that are laser

trimmed on this device: quiescent current, and offset voltage. The resistors are

a thin film, like NiCr or SiCr. The laser is used to burn away or open sections of

resistance making the total resistance higher. This trimming can actually be

done as the device operates. So, for example, you can monitor offset voltage

and trim the resistor until the total offset is zero. Unfortunately, the laser

trimming action can disturb the circuit operation, which can introduce errors or

require very slow pulsed trimming. At wafer, the trimming may produce very

accurate results. However, the wafer is sawed into die and is packaged. This

process normally causes some shift in the offset so some of the accuracy is lost.

Note that laser trimming has been used for years, and may new methods have

been developed. So, some may think that laser trimming is obsolete. This is

not true, however, as this is the only practical way to trim bipolar circuits.

CMOS circuits can use package level trimming as we will see later in this

presentation.

9

The OPA1612 and OPA320S are two op amps designed for very different

markets, but both rely upon thin-film resistor laser trimming to minimize voltage

offset and drift. The trimming is accomplished at the wafer level. An added

bonus is the quiescent current can be trimmed for an optimal operating value

when the op amp is at probe and under the laser.

10

In package level trimming the device is trimmed after it is packaged. This has

the advantage of avoiding the packaging shifts that happen when die are

packaged. Package level trimming involves digitally communicating with the

device and blowing fuses that “trim” the resistor. In fact, the fuses will be read at

power up and the resistors will be adjusted by shorting out segments using

digital switches. Since most op amps don’t have a digital interface, the digital

communications generally occurs through the output of the device. By changing

the loading on the output you can create a digital pattern to program the device.

Note that after the device is programmed a “write protect” fuse is blown so that

you can never re-program the device. The big advantage of package level trim

is that it is done at final test where all of the packaging stresses on the die will

be accounted for.

11

Here are examples of the OPA376 low-voltage and OPA192 high-voltage CMOS

op amps that use active electronic trimming techniques (e-trimTM) to reduce and

minimize their naturally occurring voltage offset and drift.

12

Let’s look at the inside of CMOS and bipolar amplifiers again to consider the

difference in bias current across the technology. In the case of bipolar devices,

the bias current is from the base current of the device. This will very depending

on the process but often is in the range of 100nA. In the case of CMOS devices

on the other hand, the bias current is almost completely from leakage of the

input diodes. The input gate current is negligible as the impedance is very large

(Tera-ohms). Typical the room temperature bias current will be about 1pA. Thus

the bias current for a CMOS device is often 100,000 times smaller than that of a

bipolar device.

13

One way to minimize the bias current for bipolar devices is a method called bias

current cancellation. In bias current cancellation, the base current of the input

transistors is monitored and an equal but opposite current is summed into the

input to cancel the bias current. Of course, it is not possible to perfectly cancel

the bias current so some residual current will remain. Typical circuits will get a

100x improvement in bias current reducing it from 100nA to 1nA.

14

The OPA209 and OPA211 are both high performance bipolar input operational

amplifiers. The OPA209 includes input bias current cancellation circuitry, while

the OPA211 does not. It can be seen that the typical and maximum input bias

currents are significantly different for the two op amps. If keeping the input bias

current low is important in a low-noise application, then the OPA209 may be

choice. One clue to if a bipolar input device has input bias current cancellation

is that the input bias current will be approximately equal to the input offset

current.

15

One thing to remember with low bias current amplifiers is the effect of IB over

temperature. In MOSFET amplifiers, the bias current can double every 10°C.

You can see in the example on the right with the OPA350 that the input bias

current increases significantly at temperatures above 25°C. If you only

considered the room temperature value of IB and then operated the amplifier at

elevated temperature, you would have significant errors. Notice that the vertical

axis of the plot uses a logarithmic scale.

With the bipolar amplifier, the initial input bias current at room temperature is

often large enough such that the relative change in input bias current over

temperature is minimized. You can see in the example on the left with the

OPA277 that the input bias current starts to increase at temperatures above

75°C, but note that the vertical axis uses a linear scale.

16

The 1/f noise corner of an op amp is often considered to be a figure of merit.

The noise corner is the place at which the 1/f and broad band noise curves

interest or the bend in the curve. The 1/f noise corner is much higher for CMOS

devices. JFET and bipolar have comparable 1/f noise although bipolar is

generally somewhat better. In fact, the JFET input is often selected to provide

very low Ib with good 1/f noise performance. In other words with JFET, you get

good Ib performance like a CMOS device, with good noise performance like a

bipolar device.

The current noise is shown in the red box. Note that current noise doesn’t

always have a curve as current noise for FET devices is generally considered to

be flat over frequency. Also note that the current noise is substantially smaller

with CMOS and JFET devices than with bipolar devices. Finally, note that the

bipolar current noise may have a 1/f component that makes it much higher at

low frequencies.

17

Here three high performance op amps that use the three key op amp

technologies, which we have presented, have their voltage noise density

compared. The OPA227 was shown in the previous graph to have the lowest 1/f

corner frequency and lowest voltage noise. Its noise performance is followed by

the JFET input OPA827 amplifier which is just slightly higher. The OPA350

voltage noise is considerably higher at 1 kHz compared to the other two

amplifiers, but is expected because of considerably higher 1/f frequency of the

CMOS process and design.

18

For rail-to-rail input CMOS devices, the two input transistor pairs will have independent and uncorrelated input offset voltages. This usually means that the input offset will be different for the two different input pairs. Thus, when we transition from one pair to the other, the offset voltage will abruptly change values. The figure on the right shows an example of the abrupt transition in input offset voltage. The green region shows the Vos when the p-channel input pair is active for common mode voltages between -0.3V and 3.5V. The p-channel pair has an offset of about 100uV. The red region show the Vos when the n-channel input pair is active for common mode voltages between 4V and 5V. The n-channel pair has an offset of about -200uV. When the common mode transitions past 3.5V the offset transitions from 100uV to -200uV. The abrupt transition in offset can appear as distortion in the output signal, known as “input crossover distortion” since it occurs during the crossover from one input pair to the other.

Taking a closer look at the specifications table, you will notice that the common mode rejection is low if the entire common mode range is considered. In some amplifier specifications you will see two separate specifications for common mode rejection ratio (CMRR) in the two different regions. In these cases the CMRR of each independent region can be very good, but the overall CMRR may be degraded if you include the crossover distortion. When looking at a rail-to-rail op amp data sheet, the different regions over which the CMRR is specified can be helpful for determining the crossover region.

19

The OPA703, a 12 V CMOS op amp, and the OPA314, a CMOS low-voltage op

amp utilize complementary N-channel and P-channel input differential pairs. The

graphs show the noticeable voltage offset shift that occurs as the input common-

mode voltage transitions from the region where the P-channel pair is active (N-

channel inactive) and then the N-channel pair becomes active (P-channel

inactive). For many applications this may not be an issue; especially, if that

portion of the CMV region can be avoided.

20

What does crossover distortion look like? Let’s consider an example when the

amplifier is in unity gain and has the common mode transition near 4V. The

input is a sine wave centered on 2.5V with an amplitude of 4Vpp. Because of the

non-inverting configuration, the input signal is also equal to the common mode

signal. When the input signal transitions above 4V, the offset transitions from

2.5mV to -5mV. Although this is a fairly large offset shift, it is difficult to see it on

the output signal diagram. Zooming in at around 4V, however, allows us to see

the output distortion introduced by the offset shift. In many applications, this

crossover distortion is not as significant as in this example. As with any error

source, consider your error budget and decide if this error can be tolerated.

21

Here we show a simplified representation of the charge pump used in the

OPA365. In this case, the charge pump boosts the supply voltage by 1.8V while

not needing to supply much current. This is enough to overcome the Vsat + Vgs

positive rail limitation on the p-channel input pair. One concern that often

accompanies charge pump circuits is that they use a switched capacitor to

achieve the voltage boost. The switching generates noise, but in the case of the

OPA365 the amount of noise is minimized by the very low ripple design.

Despite this, it is sometimes possible for the charge pump noise to affect the

behavior of the op amp. The charge pump in the OPA365 switches at 10MHz

while the bandwidth of the amplifier is 50MHz, so in lower gain configurations

the charge pump noise will be passed by the amplifier. Generally, the charge

pump noise is small relative to the broadband noise of the amplifier.

Also note that the charge pump signal can feed through the external power

supply. In this case, it can combine with other power supply noise sources and

create harmonics of the charge pump signal. For this reason it is best to use

proper decoupling on the op amp power supply pins. In some cases using a

ferrite between the amplifier and other sensitive circuits may also help.

22

The OPA365 and OPA322 are examples of CMOS op amps that use a high

frequency, low-noise charge pump to generate a higher, internal dc voltage

source used to power the op amp input stage. Doing so allows the P-channel

inputs to operate over the entire input common-mode voltage (CMV) range

avoiding the crossover region offset shift that accompanies an input stage

comprised of complementary N-channel/P-channel differential pairs.

23

Zero drift amplifiers with rail-to-rail inputs actually use the same complementary

n-channel and p-channel input configuration as shown earlier in the video, so

they do exhibit some degree of crossover distortion. However, the offset of the

amplifier is corrected by digital calibration, so the magnitude of the offset

transition and the crossover distortion is greatly diminished. We will examine

how a “Chopper” amplifier works in subsequent slides.

24

Another way to minimize offset and offset drift is with a zero drift amplifier. Zero drift is a general term used for any amplifier that has an internal calibration method that minimizes offset and drift. There are two common types of zero drift amplifiers: chopper and auto-zero. The auto-zero amplifier samples the offset and uses this value to correct the error. We will not discuss the auto-zero further here, but just know that it has similar characteristics and specification to the chopper amplifier.

Before discussing the chopper amplifier let’s look at a standard two stage op amp internal structure (shown at the top of the page). The two stage op amp will have a very small differential input signal (Vin). This input is translated to a current by the transconductance stage. The second stage is a transimpedance stage and it converts the current back to a voltage by charging the miller capacitance Cc.

The chopper amplifier has the same two stages. The main difference is that the input and output of the first stage has a set of switches that flips the input signal once every calibration cycle. In the next slides we will see how this can minimize the offset and offset drift.

Finally notice the table compares uncorrected versus zero drift and laser trim methods. In general, the zero drift method gives the best drift performance.

25

The OPAx333 series of CMOS operational amplifiers use a proprietary auto-

calibration technique to simultaneously provide very low offset voltage and near-

zero drift over time and temperature. It is a low-voltage, low operating current op

amp. The OPA2188 relies upon the same auto-calibration technology used for

the OPA333, but is processed on a HV CMOS process allowing for use with

supplies up to 36 V. Its operating current is higher to support lower noise, wider

bandwidth and faster slew rate than is obtained with the micro-power OPA333.

26

These summary slides will provide a quick reference guide to the trade-offs in specifications

when considering CMOS, Bipolar, and JFET op amp topologies. We’ve used a simple system of

X and check marks to show the relative strengths and weaknesses of each topology. While there

is too much information to be read here, you can refer back to this slide set at your convenience.

First we have summarized the differences between input offset voltage, input offset voltage drift,

input bias current, input bias current drift, and input offset current.

Vos: CMOS, largest Vos, complex trim, unless Chopper or Auto-zero.

Bipolar, smallest Vos, laser trim only, simple trim

JFET, larger than Bipolar, laser trim only, complex trim

Vos Drift: CMOS, largest drift, complex trim, unless Chopper or Auto-zero.

Bipolar, linear drift, laser trim only, simple trim

JFET, larger drift than Bipolar, laser trim only, complex trim

Ib: CMOS, lowest Ib (pA)

Bipolar, high Ib, can be minimized with Ib cancellation (nA)

JFET, Lowest Ib (pA)

Ib Drift: CMOS, doubles every 10C, ESD diode leakage dominant (pA to nA)

Bipolar, small change over temperature (nA)

JFET, doubles every 10C, ESD diode leakage dominant (pA to nA)

Ios: CMOS, Ios comparable to Ib (but pA)

Bipolar, high Ib, can be minimized with Ib cancellation (nA)

JFET, lowest Ib, Ios comparable to Ib (but pA)

27

Next we compare the broadband noise, 1/f or low-frequency noise, presence of anti-parallel differential input diodes, integrated digital logic, rail-to-rail input and output, and output voltage vs. load capabilities of the different topologies.

Broadband Noise: CMOS, largest noise

Bipolar, smallest noise

JFET, slightly larger than Bipolar, smaller than CMOS

1/f Noise: CMOS, largest noise, >1kHz 1/f frequency, Chopper can eliminate 1/f noise

Bipolar, lowest noise, 1/f frequency <10Hz

JFET, lower than CMOS, higher than Bipolar noise, 1/f frequency <100Hz

Anti-parallel differential input diodes: CMOS, may or may not be needed – check datasheet

Bipolar, generally required

JFET, generally not required – check datasheet

Integrated Digital: CMOS, yes for Auto-zero or Chopper or e-Trim

Bipolar, no

JFET, no

Rail to Rail Input: CMOS, yes

Bipolar, no

JFET, not common

Rail to Rail Output: CMOS, close to rail (i.e. 10mV)

Bipolar, within 200mV of rail

JFET, within 200mV of rail

Output vs. Load: CMOS, falls off quickly with load due to Rds_on

Bipolar, relatively flat until current limit

JFET, relatively flat until current limit

28

We will spend the next few slides discussing some easy ways to help quickly

pick the right op amp for your application.

29

The first selection criteria is to answer for your application what Voltage (Supply

Voltage) , Current (Quiescent Current), and Speed (Bandwidth) you will need to

meet your end design goals.

30

After your op amp choices have been narrowed down by the 1st Criteria

Selection, you can continue to narrow your final choices by the 2nd Criteria

Selection Process.

For Voltage: Input Offset Voltage, Input Noise Voltage, Common mode Input

Voltage Range, and Output Swing.

For Current: Output Current, Input Bias Current, Input Current Noise.

For Speed: Slew Rate and Output Impedance (a key parameter for driving

capacitive loads or dynamic transient lads such as driving SAR ADCs)

For Other: Package, Single/Dual/Quad available, Price

31

Before we end let’s take a quick look at additional resources on www.ti.com you

may find of interests.

32

IF you are interested in further information on op amp process and topologies

consider these TechNotes.

33

Also available on www.ti.com are additional training and support tools. TI

Designs offer comprehensive sub-system designs with calculations, simulations,

and measured real world results. TINA-TI is an easy to use, GUI based, full

featured SPICE simulator. A Parametric Cross-Reference to find similar TI

Devices by parameters to what you are using now. The WEBENCH Filter Design

is a powerful way to easily design Active Filters. The DIP Adapter EVM offers a

quick way to convert surface mount ICs to the standard dual in-line package

type for connecting wires to or installing on breadboard platform. Check out our

Amplifier Quick Search which uses Current, Voltage, And Speed to help simplify

the op amp selection process. For direct cross-reference by part number use the

TI Cross Reference tool. For quick building block op amp circuit ideas check

out the Analog Engineer’s Circuit Cookbook. For a universal Pocket reference

look at the Analog Engineer’s Pocket Reference. And finally for 24-hour or less

response to technical questions about Texas Instruments products use the E2E

Forum located e2e.ti.com

34

35