HSPICE COMPATIBLE MODELING AND PERFORMANCE ANALYSIS OF CARBON
NANOTUBE FIELD EFFECT TRANSISTORS
A Thesis
by
TEJAS SHANMUKHA SWAMY
Submitted to the College of Graduate Studies
Texas A&M University-Kingsville
in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
December 2013
Major: Electrical Engineering
iii
ABSTRACT
HSPICE Compatible Modeling and Performance Analysis of Carbon Nanotube Field Effect
Transistors
(December 2013)
Tejas Shanmukha Swamy
Bachelor of Engineering, PES Institute of Technology, Bangalore
Chairman of Advisory Committee: Dr. Reza Nekovei
Scaling down of Semiconductor Devices in nanometer range has been almost stagnated due to
various obstacles faced such as decrease in trans-conductance, source to drain tunneling, gate
oxide current leakage, increase in propagation delay, less control over gate region, device
mismatch and mobility degradation. Research is continuously in progress to implement Carbon
Nanotubes (CNT) in Field Effect Transistor (FET) known as Carbon Nanotube Field Effect
Transistor (CNFET). It is found that CNFET based digital circuits could enhance the
performance over regular Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) like
better channel control, increase in current density and electron mobility, better threshold voltage
and increase in trans-conductance. This thesis work provides detailed explanation of properties
of Carbon Nanotubes and study of the Model of CNFETs which is implemented in HSPICE.
Digital circuit using this model is tested for its performance and is compared with performance
of similar MOSFET circuit. Other research progresses in this field are studied and the present
simulation results are verified.
iv
ACKNOWLEDGMENTS
I take this opportunity to thank all the special personalities for their constant
encouragement, optimistic motivation and precious support throughout my research endeavor.
I sincerely thank my advisor Dr. Reza Nekovei for the valuable guidance during each
phase of research, showing patience and filling out the confidence to ascend every challenge in a
progressing manner. This research would not have been possible without his kind and generous
imparting of knowledge and showing the right direction to proceed.
I would like to express my heartfelt gratitude to the supervisory committee members –
Dr. Lifford McLauchlan and Dr. Amit Verma for sharing their precious time and providing
valuable reviews on this research. I extend my sincere thanks to the Dean of Graduate studies,
Dr. Mohamed Abdelrahman for his timely suggestions and advisements during the progress of
research and providing with required lab resources.
I always cherish and thank the endless love and selfless support of my family. I thank all
of my friends for making this journey a special one and creating lots of memorable moments.
I thank the Almighty for all the Divine blessings and strength in making this thesis work
possible.
v
DEDICATION
to my Parents…
vi
TABLE OF CONTENTS
Page
ABSTRACT ................................................................................................................................... iii
ACKNOWLEDGMENTS ............................................................................................................. iv
DEDICATION ............................................................................................................................... vi
TABLE OF CONTENTS ............................................................................................................... vi
LIST OF FIGURES ....................................................................................................................... ix
LIST OF TABLES ......................................................................................................................... xi
CHAPTER I .................................................................................................................................... 1
INTRODUCTION .......................................................................................................................... 1
1.1 Present Scenario and Future Scope of Semiconductors ........................................................ 1
1.2 Thesis Objective .................................................................................................................... 4
1.3 Thesis Inspiration .................................................................................................................. 5
CHAPTER II ................................................................................................................................... 7
LITERATURE SURVEY ON CARBON NANOTUBES ............................................................. 7
2.1 Carbon Nanotubes ................................................................................................................. 7
2.2 CNFETs ............................................................................................................................... 10
CHAPTER III ............................................................................................................................... 14
CIRCUIT EQUIVALENT CNFET MODEL ............................................................................... 14
3.1 Real Time Challenges ......................................................................................................... 14
vii
3.2 Gate Capacitance Modeling ................................................................................................ 15
3.2.1 Gate to channel capacitance ......................................................................................... 15
3.2.2 Outer fringe gate capacitance ....................................................................................... 17
3.2.3 Gate to gate capacitance ............................................................................................... 18
3.3 Intrinsic Channel Region Modeling .................................................................................... 20
3.4 Complete Device Model...................................................................................................... 21
CHAPTER IV ............................................................................................................................... 23
IMPLEMENTATION OF DIGITAL CIRCUIT IN HSPICE ...................................................... 23
4.1 Modeling of HSPICE Compatible CNFET Parameters ...................................................... 23
4.1.1 Device parameters of the model ................................................................................... 24
4.1.2 Global parameters of the model .................................................................................... 26
4.2 N type CNFET DC Analysis ............................................................................................... 27
4.3 P type CNFET DC Analysis ............................................................................................... 28
4.4 Inverter using CNFET ......................................................................................................... 29
CHAPTER V ................................................................................................................................ 32
PERFORMANCE ANALYSIS AND SIMULATION RESULTS .............................................. 32
5.1 Transfer Characteristics: CNFET vs MOSFET .................................................................. 32
5.2 Load Driving Capability of CNFET and MOSFET Inverters ............................................. 35
5.3 Estimation of Power Delay Product for CNFETs and MOSFETs ...................................... 37
viii
CHAPTER VI ............................................................................................................................... 42
SIMILAR RESEARCH PROGRESS ON CARBON NANOTUBE FIELD EFFECT
TRANSISTORS ............................................................................................................................ 42
6.1 Performance Analysis by Estimation of PDP of CNFET and MOSFET Models ............... 42
6.2 Performance Testing of CNFET on Scalability and Parasitic Effects ................................ 45
6.3 Transient Analysis between CNFET and MOSFET Comparators...................................... 46
CHAPTER VII .............................................................................................................................. 49
SUMMARY OF THE RESEARCH WORK ................................................................................ 49
7.1 Conclusive Remarks ............................................................................................................ 49
7.2 Scope for Future Work ........................................................................................................ 50
REFERENCES ............................................................................................................................. 51
APPENDIX ................................................................................................................................... 55
VITA ............................................................................................................................................. 62
ix
LIST OF FIGURES
Page
Figure 1. Gate oxide current leakage for NMOS at 45 nm ............................................................. 2
Figure 2. Gate oxide current leakage for NMOS at 65 nm ............................................................. 2
Figure 3. (a) Unrolled graphite sheet (b) Rolled CNT lattice structure ......................................... 8
Figure 4. (A) Single Walled CNT (B) Multi Walled CNT ............................................................. 8
Figure 5. Elevation and Section views of Carbon Nanotube structures ......................................... 9
Figure 6. (a) Structure of CNFET (b) Electrostatic capacitor model ............................................ 10
Figure 7. Energy band diagram for (a) SB-FET (b) MOSFET-like FET .................................... 12
Figure 8. (a) The 3-D representation of CNFET including multiple channels and the related
parasitic gate capacitances (b) The 2-D view of the cross section in the channel region ..... 15
Figure 9. 6-Capacitor model for the intrinsic channel region ....................................................... 20
Figure 10. 4-Capacitor complete circuit model of CNFET .......................................................... 21
Figure 11. DC analysis of N type CNFET .................................................................................... 27
Figure 12. DC analysis of P type CNFET..................................................................................... 28
Figure 13. Symbolic representation of CNFET ............................................................................ 29
Figure 14. Circuit of an inverter using CNFETs........................................................................... 30
Figure 15. (A) Transfer characteristics of an inverter using CNFET model. (B) Variation of input
current drawn with change in input voltage. (C) Current drawn from power source Vdd vs
Vin ......................................................................................................................................... 33
Figure 16. (A) Transfer characteristics of an inverter using MOSFET model. (B) Variation of
input current drawn with change in input voltage. (C) Current drawn from power source
Vdd ........................................................................................................................................ 34
Figure 17. Load Capacitance vs propagation delay in CNFET and MOSFET inverters.............. 36
x
Figure 18. Frequency response of CNFET inverter ...................................................................... 38
Figure 19. Frequency Response of MOSFET inverter ................................................................. 39
Figure 20. PDP of CNFET and MOSFET inverter models .......................................................... 40
Figure 21. 10 Transistor SET D-FLIP FLOP ............................................................................... 42
Figure 22. PDP of CNFET and MOSFET D-Flip Flop for LVSB Bias design ............................ 43
Figure 23. PDP of CNFET and MOSFET D-Flip Flop for STGB Bias design ............................ 44
Figure 24. PDP of CNFET and MOSFET D-Flip No Body Bias design ..................................... 44
Figure 25. Performance of an inverter at different diameters of CNTs ........................................ 45
Figure 26. Effects of Parasitics ..................................................................................................... 46
Figure 27. Rise time Propagation Delay for CNFET and CMOS Comparator ............................ 47
Figure 28. Fall time Propagation Delay for CNFET and CMOS Comparator ............................. 47
xi
LIST OF TABLES
Page
Table 1. Device Parameter Definitions ......................................................................................... 25
Table 2. Global Parameter Definitions ......................................................................................... 26
Table 3. Load Capacitance vs Propagation Delay in CNFET and MOSFET Inverters ................ 36
Table 4. Power Delay Product of CNFET Inverter....................................................................... 39
Table 5. Power Delay Product of MOSFET Inverter ................................................................... 40
Table 6. Performance Comparison of CNFET and CMOS Comparators ..................................... 48
1
CHAPTER I
INTRODUCTION
The world has witnessed continuous growth in the field of semiconductors. Research was
always concentrated on building smaller and faster circuits. As more efforts are put in for the
enhancement in the performance, lowering the cost of production and shrinking the die size,
transistors are scaled down each day and the maximum number of transistors are accommodated.
This means researcher’s work was mainly based on reducing the size of Field Effect Transistors
(FET). Metal Oxide Semiconductor field Effect Transistors (MOSFET) technology was one the
biggest advancement in the VLSI industry. As scaling down of MOSFETs has reached its
saturation limit due to transistor size entering into nanometer range, it has been observed that
there is degradation in the performance of well tempered MOSFETs [1 - 3]. Hence, other means
to enhance device performance are looked upon. Scaling down of power supply helps in building
low power devices but also leads to increase in delay which degrades the performance of digital
circuits [4].
1.1 Present Scenario and Future Scope of Semiconductors
Scaling down of semiconductor devices further, more into sub micron level (<45nm), has
been almost stagnated due to various problems faced in the performance of transistors. Some of
the major problems faced are gate oxide current leakage due to thinning of the gate oxide layer,
low trans-conductance, source to drain tunneling increases as length of the gate decreases,
increased delay, less gate control, device mismatch, and mobility degradation. This has caused
awareness for the search of other materials similar to silicon for building transistors.
2
Nanotechnology is an area where more scientists are working to continue the growth in
the field of semiconductors. Alone silicon is no longer considered for fast and high speed
circuits. Inventions of new material which can replace silicon are a big leap.
Figure 1. Gate oxide current leakage for NMOS at 45 nm [5]
Figure 2. Gate oxide current leakage for NMOS at 65 nm [5]
Above is the graphical analysis of gate current leakage of a Negative Metal Oxide
Semiconductor (NMOS) of 45nm and 65nm process technology, respectively. It is observed that
there is an exponential increase in the gate current leakage when voltage is applied. It is observed
that gate current leakage is significantly higher when gate physical length is reduced to 45nm
3
from 65nm.The gate current leakage of 65nm NMOS at 1V was around 6pA whereas it is greater
than 55pA in the case of 45nm NMOS at the same voltage. This indicates that, by scaling down
of transistors, performance of transistors too scales down rapidly [5].
This constraint of scaling down of MOSFETs has led to research on finding an alternative
for silicon. Research has led to various methodologies like Silicon Germanium (Si-Ge)
transistors, Single Electron Transistors (SET), Field Effect Transistors (FETs) using Carbon
Nanotubes and FETs using Quantum Dot Gate (QDG) technology. Much progress has been
observed in developing Carbon Nanotubes and studying them. Si-Ge transistors have been useful
in improving the performance, to some extent, but scaling has always been the issue.
SETs have helped in scaling of transistors of gate length < 10nm but, it has been
observed to be very sensitive to its surroundings. It produces high noise peaks with any presence
of nearby electrons which is its main limitation making its operating range narrow.
QDGFETs have been a new area of research for producing high performance digital circuits,
although not much progress has been achieved in fabricating QDGFETs due to their complex
nature.
Carbon Nanotube Field Effect Transistor (CNFET) is an area where considerable
research has progressed in its theoretical analysis and practical fabrication of FETs using Carbon
Nanotubes.
Carbon Nanotubes are preferred over other technologies due to their exceptional physical
and electrical properties.
4
Some of the salient features as to why CNFETs are preferred are:
Fabrication of Carbon Nanotubes has come into existence and fabrications of CNFETs
are similar to that of regular MOSFETs.
Device structure and principle of operation are similar to MOSFETs so that infrastructure
of CMOS fabrication can be modified and reused for fabrication of CNFETs.
Results on research about CNFETs have shown to be far better than the performance of
MOSFETs.
1.2 Thesis Objective
Although significant research has been done on CNFETs, complete implementation in IC
design is not in existence due to incomplete analysis and performance comparison of CNFETs
with regular bulk MOSFETs. Hence this has led researchers from all over the world to analyze
and compare the performance of CNFETs so that they can come up with a new and promising
technology for the future.
A group of researchers at Stanford University have come up with a near to realistic model
in SPICE for CNTs. This model was designed after detailed study on CNTs and its properties of
complex quantum mechanisms. Parameters like gate capacitance with high-k gate dielectric
material, parasitic capacitances and screening effects due to capacitances were considered in
modeling of CNTs [6]. This model has been studied and analyzed. Using this model, a digital
circuit is rigged up in SPICE and tested for its performance. Similar a digital circuit is also
rigged up using MOSFET and its performance is analyzed and compared with a CNFET circuit.
Chapter II provides literature survey on CNTs and its modeling. Detailed explanation on
CNTs is provided. Synthesis of CNTs is studied and its physical, chemical and electrical
properties are analyzed.
5
Chapter III explains about modeling of equivalent circuit of CNFETs in 3 step analyses,
starting from gate capacitance modeling. Later intrinsic gate channel region is modeled using
gate capacitance model, from which complete device equivalent circuit model is deduced.
Implementation of a digital circuit in HSPICE for CNFET is explained in chapter IV.
Similar digital circuit is implemented using regular MOSFETs in HSPICE. These circuit models
are simulated and simulation results are analyzed in chapter V. Analysis like DC analysis, Load
driving capabilities of CNFETs and MOSFETs, and also performance analysis by estimating
power delay product is carried out.
Chapter VI gives information regarding similar research progress in analyzing the
performance of CNFETs. Some of the simulation results displayed are analysis by calculation of
power delay product, performance variation by scaling and inclusion of parasitics, and also of
transient analysis.
Chapter VII summarizes the whole report and gives an insight of future work which may
be conducted.
1.3 Thesis Inspiration
At current situation where scaling of transistors have almost stagnated, emerging with
another new technology and implementation of that technology would be a daunting task.
Replacement for silicon with other materials in real world would mean a massive change in the
semiconductor industry. From design specification team until the tape out team would have to
change their whole processes and technologies suiting the new process. This could be a very
risky situation with investment of huge amount of money and time. Output of this change may
not produce the required results. Hence firstly there is a need to analyze any given new
technology theoretically before implementing it practically.
6
In this case, where we are talking about replacing CNTs to build FETs, need for
analyzing the properties of CNTs are of utmost importance. Designing a theoretical model and
testing it for all potential possibilities regarding real world challenges would be the first step
towards transition from one technology towards another. Obtaining positive results would ensure
that implementation would have a high probability of becoming a successful implementation
with the help of theoretical analysis.
In this research work, an effort is made in analyzing CNTs. A SPICE model developed
by researchers from Stanford University have been utilized in testing the performance of
CNFETs by implementation of FETs using a SPICE simulator called HSPICE and comparing the
results with similar MOSFET circuit models.
7
CHAPTER II
LITERATURE SURVEY ON CARBON NANOTUBES
This section gives an overview of various research advancements on CNTs and a detailed
explanation on their physical, chemical and electrical properties. This section also explains
various processes and methodologies of preparing CNTs and fabrication of CNFETs from CNTs.
2.1 Carbon Nanotubes
The electronic configuration of a Carbon atom is 1s2, 2s
2, 2p
2 in its ground state. Since in
graphene, covalent bonding is formed between adjacent Carbon atoms due to sp2 hybridization of
the two outermost shells, the inter-carbon-atomic distance within the hexagonal lattice which is
formed is approximately 1.44 Å and the angle between carbon-carbon bonds being 120 degrees.
The lattice constant is calculated to be 2.49 Å [7]. Due to sp2 hybridization, carbon atoms have a
strong force of attraction and this is the main reason for many unique properties in CNTs.
CNTs are a thin layer of graphite sheet which are rolled up in the form of hollow tubes
[8] where carbon atoms bond with each other in a particular direction or chiral vector on the
surface of the tube which indicates the type of CNT formed. They can be either a single layered
tube which is known as Single Walled Carbon Nanotubes (SWCNTs) or multi layered tube
which is known as Multi-Wall Carbon Nanotubes (MWCNTs) [9]. In this thesis work, only
SWCNTs are concentrated upon.
8
Figure 3. (a) Unrolled Graphite Sheet (b) Rolled CNT Lattice Structure [7]
Figure 4. (A) Single Walled CNT (B) Multi Walled CNT [10]
The length of the CNT depends on the direction of alignment of carbon atoms. When a
CNT is formed from a graphene sheet, there would be a constraint on permissible electronic
states on the circumference of the tube.
9
Figure 5. Elevation and Section Views of Carbon Nanotube Structures [11]
SWCNTs are nothing but a single layer of graphite sheet rolled up for about a diameter of
1-2nm and attached together at the end along a vector chirality making it to look like a tube or
cylinder. Depending on the nanotube’s chirality or direction of alignment of carbon atoms, CNTs
are classified into metallic or semiconducting CNTs. Semiconducting CNTs can be separated by
metallic CNTs by burning out metallic CNTs. Semiconducting CNTs are used for fabrication of
FETs and in turn digital circuits. Around 30% of synthesized CNTs are metallic in nature. The
major part of this can be separated from semiconducting CNTs by selective Etching [12]. Above
figure depicts the possible combinations of CNTs.
10
2.2 Carbon Nanotube Field Effect Transistors (CNFETs)
The principle of operation of CNFET is found to be very similar to working of regular
MOSFETs as both the devices are found to utilize the source to gate potential to control the
current flow from source to drain. CNFET like MOSFET is a four terminal device having
semiconducting CNT as the conducting channel at the gate by bridging the source and drain.
Figure 6. (a) Structure of CNFET (b) Electrostatic Capacitor Model [11]
Since the diameters of CNTs are in few nanometers, FETs with narrow gate lengths can
be fabricated. Above is the diagram depicting the structure of CNFET and the electrostatic
capacitance model.
11
Based on the mechanism of device operation CNFETs are classified into two types:
1. Schottky Barrier (SB) Controlled FET (SB-CNFET)
2. MOSFET-like FET
Architecture of SB-CNFET consists of a single CNT on top of a conductive plane which
is the gate region. The ends of CNT are connected to metal contacts which are the source and
drain of CNFET, and are separated by dielectric material. The gate length is usually around
300nm which is many times greater than bulk FETs. This type of CNFET incorporates CNT to
cover the full length of the gate, and hence it provides a strong coupling capacitance to all the
regions of the channel length. SB-CNFET works on the principle of tunneling the majority of
charge carrier schottky barriers at the end contacts. The device performance of SB-CNFET and
also the on-current is determined by the contact resistance which is due to tunneling barriers [7].
MOSFET-like CNFET incorporates channels spanned by partial CNTs which results in
low coupling capacitance. This type of CNFET reduces the ability of gate to control charge
carrier movements from source to drain by varying the thickness of potential barrier at source
and drain. This type of CNFET also known as bulk switched CNFETs which modulate the
potential at the gate region and also its availability of channel for charge carriers. It exhibits
unipolar behavior. This is due to suppressing of either PFET (electron) or NFET (hole) transport
with a heavily doped source or drain. Therefore the conductivity is altered by the gate to source
bias of the non-tunneling potential in the channel region [7]. This device shows n-type
characteristics. P-type devices could be constructed by trapping negative charges in the gate
dielectric to reduce the potential barriers to holes.
12
MOSFET-like FET offer several advantages over Schottky Barrier controlled CNFET
like, thickness of potential barrier at source and drain junctions are greatly reduced. This reduces
transistor conductivity and current capacity. Also the sensitivity of metal-nanotube interface
would not be the current controlling feature of the device.
Below are the energy band diagrams for SB-CNFET and MOSFET-like FET.
Figure 7. Energy Band Diagram for (a) SB-FET (b) MOSFET-like FET [7]
CNTs were first found back in 1998. From then on research is in full flow fabrication and
designing of digital circuits using CNTs. Later in 2006, a five-stage CMOS type CNT ring
oscillator was fabricated using p-type palladium gates and n-type aluminum gates [13]. This ring
oscillator works around the frequency of 70MHz to 74MHz.
Even though the discovery of Carbon Nanotube was back in 1998 and fabrication or
synthesis of CNT methods have evolved, not much progress has been witnessed for VLSI Circuit
Design. In order for CNTs to emerge as a new, advanced and a revolutionary technology, tools to
determine the performance of CNTs are required. This led to Analysis of CNTs from a different
perspective that is analysis by modeling of CNTs and studying its characteristics. Studying CNTs
from a theoretical perspective would give more options of synthesizing and involving CNTs into
13
other applications as well. The requirements for a good device model would include analyzing
the device or circuit performance, as well as the performance dependence on geometry which
include:
Reasonable accuracy for both small and large signal analysis,
Very good scaling factors,
Reasonable run times.
Efforts have been made on modeling of semiconducting CNTs in recent times for CNT
interconnects [15] as well as CNFET Digital Logic Applications [16]. From all the research
done, it was inferred that SB-CNFET had superior DC performance than MOSFET-like FET.
But AC performance of SB-CNFET turned out to be the opposite of that of its DC performance.
This concluded that SB-CNFET was not suited for high frequency Digital Circuit design. Hence
in this thesis work MOSFET-like FET would be considered for modeling and testing its
performance.
14
CHAPTER III
CIRCUIT EQUIVALENT CNFET MODEL
In recent few years, one dimensional FETs with cylindrical conducting channels has been
reported due to enhancement in the electrostatic performance over regular bulk CMOS. Either a
planar gate structure or gate-all-around in a uniform dielectric material was initially used with
single conducting channel to analyze and evaluate the device performance and gate capacitance.
In the devices, where in high-k dielectric is not same as substrate dielectric, there could be error
in approximation to about 10-40%. Additionally, as drive current which are delivered from a
single channel is small, multiple channels are required per gate to achieve higher performance
than traditional CMOS circuits [11].
3.1 Real Time Challenges
The maximum frequency of operation for any digital circuit depends on the transistors
speed that is mainly dependent on the parasitic gate capacitance, which includes gate to gate
(source or drain) coupling capacitance (Cgtg) and outer fringe gate capacitance (Cof). Hence it is
very essential to understand the various components of total gate capacitance (Cgg) with utmost
accuracy in order to predict and evaluate the one dimensional transistor’s performance [17].
Modeling of CNTs in FETs consists of two steps:
Analytical model for the gate capacitance, Cgg which includes components like screening effect
and outer fringing field effects which are presented and can be incorporated in HSPICE [16].
From this SPICE compatible model for the gate capacitance, very near to realistic estimate of
circuit performance including the parasitic capacitances and also the screening effect due to
multiple parallel channels, can be deduced [18].
15
3.2 Gate Capacitance Modeling
Gate Capacitance modeling includes modeling of all the parameters which are influenced
for increase in capacitance and might be involved in the non linearity in device performance.
High-k gate dielectric materials with a multiple dielectric constants are considered.
Figure 8. (a) The 3-D representation of CNFET including multiple channels and the related
parasitic gate capacitances (b) The 2-D view of the cross section in the channel region [7]
The above figure describes the multiple cylindrical tubes along with capacitances. The
significant and important capacitances which are modeled are:
Gate to channel capacitance (Cgc)
Gate outer fringe capacitance (Cof)
Gate to gate, or gate to source or drain coupling capacitance (Cgtg)
3.2.1 Gate to channel capacitance
The gate to channel capacitance accounts for the majority of the capacitance among all
the three capacitances. First, the gate to channel capacitance for unit length is calculated for a
planar gate structure with high k-dielectric material in this section where multiple parallel
16
conducting cylindrical channels are considered. The dimension of the diameter is very small
when compared with the length of the nanotube. Thus, the end effects of nanotubes in the axial
direction are negligible. Hence they are not considered. It is also assumed that gate width is
much larger than the diameter of the channel. Initially Cgc,inf which is the capacitance between a
single isolated cylinder and the gate is calculated.
Boundary conditions which need to be considered are:
Tangential component of the electric field which is continuous along the boundary.
The normal component of the electrical field which is continuous across the boundary.
The solutions are:
x1 = x2 = x3 y1 = -y0 y2=y0
Q1 = λ1*Q ………. (1)
Q2 = λ2*Q ………. (2)
where k1 and k2 are two different dielectric constants and λ1 and λ2 are the factors which
cause interface as k1 is not equal to k2.
From the above analysis, Gate to Channel Capacitance is expressed as:
………. (3)
where Cgco is the capacitance when k1 and k2 are equal, and Cgc imag is the equivalent
series capacitance due to the image charges when k1 is not equal to k2 and Cgc imag can be
simplified to,
………. (4)
17
Due to the screening effect, there would be an extra voltage difference in the first
cylinder and the gate which causes real and image line charges on the second cylinder.
This difference comes mainly from two sources:
1) Image charges of k1 are not equal to k2 where a single image line charge is approximated.
2) The gate capacitances are classified only into two groups known to be Cgc_e and Cgc_m, which
does not depend on the number of channels present per gate.
3.2.2 Outer fringe gate capacitance
For analyzing device speed very precisely, it is critical to include parasitic gate
capacitances which are an outer fringe capacitance (Cof) and a gate to gate capacitance (Cgtg).
An outer fringe gate capacitance is mainly due to the shape and sizing of the device. For
estimation of an outer fringe capacitance, inner fringe capacitances are ignored and uniform
dielectric materials are assumed. Variation of Cof for the Nanotube of gate length equal to 32nm
long, when gate height is reduced to 10nm from 64nm is less than 10% which is negligible from
the perspective of change in device performance. Thus it would be very reasonable and
convenient to take the assumption of Cof as independent to change in Lgate and Wgate [7].
First the capacitance between the isolated cylinder and the gate is estimated which is
Cof inf. It is by:
………. (5)
where αof_sr is the factor present due to the screening effect either from gate, source or
drain. αof_sr = 1 if the height of the adjacent gate, source or drain Hadj = 0, and αof_sr = 0.5 if Hadj =
Hgate which is the most probable scenario.
18
The simulation results of earlier research represent that it would be relevant to group the
fringe capacitances into two types. They would be:
the capacitance between gate and source or capacitance between gate and drain at the end (Cof_e)
The capacitance between gate and source or drain in between or middle (Cof_m).
These capacitances can be deduced to be:
………. (6)
………. (7)
where, both η1 and α are functions of N. η1=1 and α=1 for N=2, For N greater than 2,
extra potential drop are imposed by line charges which decreases abruptly with logarithmic scale
with the distance Lsd, and τ1 and τ2 are empirically set as 2.5 and 2, respectively [7].
3.2.3 Gate to gate capacitance
Gate to gate capacitance is nothing but the mutual capacitance effect due to the presence
of another gate within the vicinity of an FET. Gate to gate capacitance consists of two types of
capacitances. They are:
Gate to gate normal capacitance per unit length (Cgtg_nr).
Gate to gate fringe capacitance per unit length (Cgtg_fr).
Cgtg_nr is the capacitance caused by normal electric field within the parallel plates, which can be
expressed as,
………. (8)
19
where,
Hgate = Height of the gate
Lsd = Normal Distance between the two parallel plates
The effective radiuses of the two parallel cylinders are calculated and using that information
Gate to Gate Fringe Capacitance per unit length can be calculated. The Expression of Cgtg_fr is,
………. (9)
where, the parameter is the screening factor due to adjacent gate, source or drain.
From the above equations, Expression for total Gate to Gate Capacitance is obtained which is
given by,
………. (10)
where, τbk is the factor due to the effect of present of back plates in the expression Cgtg_fr.
The above expression for total Gate to Gate Capacitance accounts for accurate calculation with
negligible numerical mismatch with the results in simulation.
From the above analysis of estimation of complete Gate Capacitance, it can be expressed
as:
Cgg = Cgc * Lg + fmiller * 2(Cof + Cgtg * Wpitch) ………. (11)
where fmiller is a pre determined miller factor which is set to 1.5 for the above designed
model.
The above model successfully describes the gate capacitance for a high-k dielectric
material including the screening effect. Accuracy of the above model is found to be less than
20
10% for cylindrical channels and less than 15% for square cross-section channels when channel
diameter is substituted by square width.
From the analysis of this model it is found that, by increasing the number of channels per
gate or by reducing the height of the channel device speed, the capacitance can be enhanced.
3.3 Intrinsic Channel Region Modeling
In this section, equivalent circuit of the intrinsic channel region of MOSFET-like
CNFETs are presented which includes some non- idealities in channel region. This model also
includes some of the real world scenarios like the quantum confinement effects on axial,
circumferential directions, the acoustical or optical phonon scattering in the channel region, and
the screening effect by the parallel CNTs in CNFETs [7].
Below is the equivalent circuit of intrinsic channel region:
Figure 9. 6-Capacitor Model for the Intrinsic Channel Region [7]
From the above circuit, capacitances from source to gate (Csg), drain to gate (Cdg) and
bulk to gate (Cbg) are calculated and analyzed.
Below are the expressions of the respective capacitances:
………. (12)
21
………. (13)
………. (14)
where,
Ctot = Cox + Csub + Cc,
Cox is Gate Oxide Capacitance,
Lg is the Gate Length,
Cqs is the quantum capacitance at the source and Cqd is the quantum capacitance at the
drain. The above model successfully explains all the characteristics of the channel in a CNFET in
detail. From this analysis, it helps in modeling CNFET in HSPICE and tests its performance.
3.4 Complete Device Model
Obtaining a model for intrinsic Channel Region has helped in analyzing CNFETs in
detail. With the help of this model, a complete device model for CNFET can be deduced to
understand the complete working of this device. Below is the proposed equivalent circuit of a
complete CNFET including real world non idealities:
Figure 10. 4-Capacitor Complete Circuit Model of CNFET [7]
22
This proposed model explains the complete characteristics of a CNFET model including
elastic scattering in the channel region, the channel quantum resistance and the doped source or
drain region parasitic capacitance and also the Schottky Barrier resistance at the junction at the
doped CNT and the source or drain metallic contacts.
This chapter explains about the modeling of CNTs in building FETs. It involves three
steps: 1) the gate capacitance is modeled, 2) the intrinsic Channel Region is deduced from the
gate capacitance model, and 3) a complete CNFET circuit equivalent model is derived.
23
CHAPTER IV
IMPLEMENTATION OF DIGITAL CIRCUIT IN HSPICE
In the previous chapter, an HSPICE compatible model was derived starting from CNTs.
Using this, models for FETs are deduced using which N-CNFET and P-CNFET can be
constructed. With the help of these two devices, a digital circuit similar to CMOS technology can
be constructed which represents CNFETs.
In this chapter, we design an inverter using CNFET. For implementation of this circuit,
N-CNFET and P-CNFET are implemented separately. Later both are connected to form an
inverter. This inverter model has been tested for its performance. First a DC operation is
analyzed. Later its transfer characteristics are presented and a CMOS equivalent inverter circuit’s
performance is compared.
4.1 Modeling of HSPICE Compatible CNFET Parameters
SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis, which is
a general purpose circuit simulation EDA tool from Synopsys. HSPICE is one of the versions in
the family of SPICE which is usually used for simulation and testing of MOSFET, JFET,
CNFET and other advanced models.
HSPICE was selected for this research work as lower versions of SPICE such as
LTSPICE which could not handle models of CNTs. HSPICE would produce more accurate
results than the former one. HSPICE has already been used for modeling of CNFETs before and
its performance has been tested by the researchers from Stanford University who were
responsible for analysis and design of this HSPICE equivalent model.
Designing a model for CNTs in FETs would include all of the physical and electrical
properties of the device in a system understandable format that is in the form of a netlist. A
24
netlist is a set of codes which determines the connectivity of an electronic circuit. Models for
describing the nature of the device could also be included. Other files such as libraries or other
netlist having sub circuits could be included in a netlists making a hierarchical structure.
The model which is designed here for CNTs contain library files (CNFET.lib and
PARAMETERS.lib) which contains the characteristics of CNFET and its parameters. The
parameters modeled are very close to realistic parameter characteristics and are defined on the
analysis of their electrical and physical nature.
Two types of FETs are required for designing a digital circuit. They are,
N type CNFET
P type CNFET
While designing N and P type CNFETs, various parameters like gate dimensions (length
and breadth), dimensions of CNT (diameter, length, chirality etc), Dielectric constant of the gate,
power supply etc., must be considered [19]. These parameters have been set to a pre determined
values in the library files of CNFET.
4.1.1 Device parameters of the model
Device parameters describe the characteristics of the FET device. In this model, the pre
determined values of the device parameter are given in Table 1:
25
Table 1. Device Parameter Definitions
Device
Parameter
Description Default Value
Lch Physical Channel Length (L_channel) 32 nm
Lss The length of doped CNT source side extension
region
32 nm
Ldd The length of doped CNT drain side extension
region
32 nm
Efi Fermi level of Doped CNT (Efo) 0.6eV
Kgate Dielectric constant of high-k dielectric material
(Kox)
16
Tox Thickness of high-k top gate dielectric material 4 nm
Csub The coupling capacitance between the channel and
the substrate
20 pF/m
Ccsd Coupling capacitance between gate and
source/drain regions
0 pF/m
Pitch Distance between the 2 adjacent CNTs in the same
device
20nm
Wgate Width of the metal gate (sub_pitch) 6.4 nm
(n1,n2) Chirality of Semiconducting CNT (19, 0)
tubes Number of tubes in a device 1
26
4.1.2 Global parameters of the model
Global parameters are those which can change the default values of the device parameters
of an FET device depending on the characteristics of the device. Global Parameters are given in
the Table 2:
Table 2: Global Parameter Definitions
Global
Parameter
Description Default Value
L_channel Physical Channel Length 32 nm
L_sd The length of doped CNT source/drain extension
region
32 nm
Efo Fermi level of n+/p+ doped source/drain CNT
regions
0.6eV
Kox Dielectric constant of high-k dielectric material 16
Ccsd Coupling capacitance between gate and
source/drain regions
0 pF/m
sub_pitch Sub Lithographic (CNT gate width) pitch 6.4 nm
Klowk Dielectric constant of low-k oxide material 2
Ksub Dielectric material of back gate dielectric material 4
lambda_op Optical Phonon backscattering in metallic CNTs 15 nm
lambda_ap Acoustic Phonon backscattering in metallic CNTs 500 nm
photon Optical phonon energy 0.16eV
Leff mean free path in p+/n+ doped CNT 15 nm
phi_M work fuction of source/drain metal contact 4.6eV
phi_S CNT work function 4.5eV
27
These parameter values can be altered depending on the kind of CNFET which has to be
fabricated. In this research work, values of parameters mentioned above are considered. From
these values, we can build an FET using semiconducting CNTs of dimensions length of gate =
32nm and width of gate = 6.4nm which would be way smaller than present day CMOS
fabrication technology.
4.2 N Type CNFET DC Analysis
Testing any FET would start from studying its DC analysis. In this section N type
CNFET is built in HSPICE using the models of CNT and its DC characteristic are analyzed.
Below is the DC analysis waveform for an N type CNFET:
Figure 11. DC Analysis of N Type CNFET
Supply voltage is set to 0.9V and Vgg is varied from 0V to Vsupply in the steps of 0.01V for
every change in 0.09V change in Vdd. We obtain 9 different waveforms depending on the
different values of Vdd.
28
Below is the code for generation of DC analysis:
.DC Vgg START = 0 STOP = 'Supply' STEP = '0.01*Supply'
+ SWEEP Vdd START = 0 STOP = 'Supply' STEP = '0.1*Supply'
We observe that a maximum current of around 60uA when Vdd = 0.9V
4.3 P Type CNFET DC Analysis
Similar to DC analysis of N type CNFET, P type CNFET is built using the model of
CNTs in HSPICE. Below is the waveform describing the variation of saturation current due to
varying Vdd
Figure 12. DC Analysis of P Type CNFET
As the majority charge carriers in P type CNFET are holes, which would be in opposite
direction of conventional current, we get negative current Vss which is varied. The same
29
procedure is followed as done for N type CNFET for DC analysis but Vss would be varied from -
0.9V to 0V in steps of 0.01V.
Below is the code for generation of DC analysis:
.DC Vgg START = 0 STOP = '-Supply' STEP = '-0.01*Supply'
+ SWEEP Vdd START = 0 STOP = '-Supply' STEP = '-0.1*Supply'
4.4 Inverter Using CNFET
As CNFETs are still an upcoming technology in the semiconductor industry, there is no
standard symbolic representation for CNFET. But it has been represented by past researchers by
the symbol given below. The same symbol would be followed in this research work:
Figure 13. Symbolic Representation of CNFET
In this thesis work for the purpose of testing CNFETs performance an inverter is rigged
up using N and P type CNFETs. It would be easier to construct an inverter and test its
performance. An inverter was specifically chosen as it is the most primitive digital circuit
performance and also it would be a reference which would help in approximating the
performance of other circuits.
30
Figure 14. Circuit of an Inverter Using CNFETs
Since there is no standard symbolic representation of the CNFET, the same symbol is
used to represent for both P and N type CNFETs. Circuit connections for building any circuit
using CNFETs would be the same as circuits which are built using CMOS. Figure 14 represents
an inverter using CNFETs. It can be implemented in HSPICE with the following netlist:
* NCNFET
XCNT1 3 1 0 0 NCNFET Lch=Lg Lgeff='Lgef' Lss=32e-9 Ldd=32e-9
+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbn='Vfn' Dout=0 Sout=0 Pitch=20e-9 n1=m n2=n
tubes=3
* PCNFET
XCNT2 3 1 2 2 PCNFET Lch=Lg Lgeff='Lgef' Lss=32e-9 Ldd=32e-9
+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbp='Vfp' Dout=0 Sout=0 Pitch=20e-9 n1=m n2=n
tubes=3
31
XCNT1 and XCNT2 represent the label of the two FETs. NCNFET and PCNFET are the
model names which are described in the library file CNFET.
With the help of this netlist, either transient, DC or AC analysis can be performed which
is explained in detail in the next chapter with its results.
32
CHAPTER V
PERFORMANCE ANALYSIS AND SIMULATION RESULTS
In this chapter simulation results of CNFETs are obtained and a comparison of its
performance with a CMOS digital circuit is done. Other comparison results from past researches
are also explained.
For evaluating the performance of any digital circuit, few things are taken into
consideration, like the size of the digital circuit, propagation delay of the circuit, total power
consumption, load driving capabilities of the circuit etc.. Few of the performance parameters are
considered and compared with the CMOS circuit in this chapter.
For research purposes, the CMOS inverter circuit of 50nm technology model obtained
from the website www.mosis.com is considered. The gate dimensions of W=200nm, L=100nm
for NMOS and W=600nm, L=100nm are constructed in HSPICE and its performance is noted.
5.1 Transfer Characteristics: CNFET vs MOSFET
Transfer characteristics are the response of output voltage with respect to change in input
voltage. This also gives us information regarding current drawn from the power source Vdd
which helps use in analyzing approximate power drawn by the circuit.
In this section, transfer characteristics for an inverter using both the models of CNFET
and MOSFET are studied and analyzed.
33
Below is the obtained Transfer Characteristics of an inverter using a CNFET model:
Figure 15. (A) Transfer characteristics of an inverter using a CNFET model. (B) Variation
of input current drawn with change in input voltage. (C) Current drawn from power
source Vdd vs Vin
We observe from the transfer characteristic curve that the transition of output voltage is
quite fast and transition is almost at the center (0.24V to 0.26V). Noise margins (Vil and Vih) are
34
also very small. Current drawn from input voltage is very small which increases to maximum
value around 500fA and current from power source Vdd reaches a peak of around 450nA which is
a comparatively small quantity. Below is the obtained transfer characteristics of an inverter using
a 50nm MOSFET model.
Figure 16. (A) Transfer characteristics of an inverter using a MOSFET model.
(B) Variation of input current drawn with change in input voltage. (C) Current drawn
from power source Vdd
From the above transfer characteristic curve, we observe that the transition is not as good
as the response from the CNFET model. It can also be observed that the noise margin is higher in
35
the inverter built using MOSFET. The current drawn from the input voltage does not have a
linear change with the input voltage. We observe change of around 20nA(12nA to -8nA) which
is about 40 times to that of CNFET inverter. Current drawn from the power source Vdd has a
peak of about 7uA which is around 15 times greater than the peak current drawn from a CNFET
inverter.
By these comparisons of the performance of the two models, we can get an overview of its
performance when a bigger and much more complex digital circuit is tested. As transfer
characteristics does not give the full picture of the comparison of the performance of the two
models, other kinds of analysis like, load driving capabilities, frequency response, transient
response, etc., would help us get a better view about the circuits performance.
5.2 Load Driving Capabilities of CNFET and MOSFET Inverters
Load driving capabilities determine the ability of the FET to drive the forward load,
which can be estimated by the propagation delay in the response. FET, which drives a load with
less delay in its response, would be considered having greater load driving capability. This test
also determines choosing the critical operating frequency for the digital circuit.
Here, a comparison between performances of CNFET and MOSFET inverters load
driving capabilities are shown using the transient response of the inverter by varying the load.
The load is chosen to have capacitance of values varying from no load to 100fF. Capacitance of
100fF can be a very small capacitance, but when an inverter is considered being of dimensions of
width of 6.4nm and length of 32nm, 100fF is quite big capacitance to drive.
Capacitance has been chosen as a load in this scenario as capacitances are dealt with as
most frequently with loads in any digital circuits rather than resistances. Resistances are mainly
36
from wiring and intrinsic resistance of the device would constitute for a very small quantity
when compared with the parasitic and intrinsic channel capacitances.
Below is the simulation result of variation of propagation delay with change in load
capacitance:
Table 3. Load Capacitance vs propagation delay in CNFET and MOSFET inverters
Load Capacitance,
Cload (fF)
CNFET propagation
delay (ns)
MOSFET propagation
delay (ns)
no load ~0 0.4
0.1 0.02 0.7
1 0.05 0.9
10 0.5 1.5
100 5 4.5
Figure 17. Load Capacitance vs Propagation Delay in CNFET and MOSFET Inverters
37
From the above simulation result, it is observed that the propagation delay for a CNFET
inverter is negligible for very small capacitance values and increases drastically as load
capacitance increases. For a MOSFET inverter, it is observed that propagation delay is
considerably high for very low load capacitance and increases gradually. It is also observed that
propagation delay is greater in a CNFET inverter when the load capacitance is greater than 50fF
than the MOSFET inverter.
This nature of variation in the MOSFET inverter with an initial high propagation delay
and gradual increase later on would constitute for high intrinsic capacitance when compared to a
CNFET inverter.
Less propagation delay in a MOSFET inverter is observed at greater values of load
capacitance than CNFET inverters due to higher driving capabilities of MOSFET inverters which
have been modeled. This might be due to the sizing of the FETs in CMOS which have
dimensions of Width=200nm and Length=100nm for NMOS and Width=600nm and
Length=100nm for PMOS when compared to Width=6.4nm and Length=32nm for the CNFET
modeled inverter.
By this analysis, it is observed that for a more complex circuit, CNFET would have better
propagation delay at low values of load capacitance than its MOSFET counterpart. But since the
load driving capability is not as good as MOSFETs at higher load capacitances, CNFET based
circuits would require buffers for regeneration of signals more often than CMOS circuits. Even
though this kind of adverse effect is observed in CNFET based circuits, the sizing of FETs
should not be neglected as it has smaller dimensions when compared to CMOS circuits (nearly
200 times!). Considering the size of FETs of both the technologies, CNFETs ability of driving
the load is quite impressive.
38
5.3 Estimation of Power Delay Product for CNFETs and MOSFETs
Estimation of performance analysis is usually found by calculating the Power Delay
Product (PDP) of the digital circuit. It has been the most accurately measurable quantity for
measuring its performance. It considers both the power consumption and the delay of the digital
circuit.
Power dissipation can be calculated from the frequency response of the digital circuit. In
this research work operating range of frequency is chosen to be from 100MHz to 1GHz for the
purpose of calculating PDP. Load capacitance is chosen to be 5fF which is approximately
harmonic mean between the ranges chosen in the earlier section that is, 0.1fF to 100fF.
Propagation delay for CNFET and MOSFET inverter circuits from transient response is found to
be 0.3ns and 0.125ns, respectively.
Below are the simulation results of frequency response for both CNFET and MOSFET
inverter circuits.
Figure 18. Frequency Response of CNFET Inverter
39
Figure 19. Frequency Response of MOSFET Inverter
Table 4. Power Delay Product of CNFET Inverter
Frequency
(MHz)
Current,Ivdd(A) Voltage, Vgs(V) Power, P =
Ivdd*Vgs(W)
PDP (Ws)
100 5.50E-09 1.00E-04 5.50E-13 6.88E-23
200 7.50E-09 1.70E-04 1.28E-12 1.59E-22
400 1.25E-08 3.30E-04 4.13E-12 5.16E-22
600 1.80E-08 5.00E-04 9.00E-12 1.13E-21
800 2.40E-08 6.60E-04 1.58E-11 1.98E-21
1000 2.90E-08 8.20E-04 2.38E-11 2.97E-21
40
Table 5. Power Delay Product of MOSFET Inverter
Frequency
(MHz)
Current,Ivdd(A) Voltage, Vgs(V) Power, P =
Ivdd*Vgs(W)
PDP (Ws)
100 6.10E-05 3.80E-01 2.32E-05 6.95E-15
200 6.70E-05 3.50E-01 2.35E-05 7.04E-15
400 7.80E-05 2.75E-01 2.15E-05 6.44E-15
600 8.40E-05 2.15E-01 1.81E-05 5.42E-15
800 8.70E-05 1.70E-01 1.48E-05 4.44E-15
1000 8.90E-05 1.40E-01 1.25E-05 3.74E-15
Figure 18 and 19 represent the frequency response of inverters modeled using CNFET
and MOSFET models respectively. These frequency response plots give information about the
current consumption from the power source Vdd and voltage drop between gate and source
regions of both CNFET and MOSFET inverters. Using these values, total power dissipation is
calculated in Table 4 and Table 5 for inverters modeled using CNFET and MOSFET models. As
mentioned before, delay has been calculated for both the models and PDP has been calculated.
Figure 20. PDP of CNFET and MOSFET Inverter Models
41
Figure 20 presents the comparative study of PDP of inverters of CNFET and MOSFET
models operating between 100MHz and 1GHz frequency range. It is found that the PDP of an
CNFET modeled inverter is about 108 times lesser and about 10
6 times lesser than that of an
MOSFET modeled inverter at 100MHz and 1GHz, respectively. We observe that there is an
inverse exponential increase in the PDP of an CNFET modeled inverter whereas the PDP of an
MOSFET inverter is almost constant with a slight dip in its PDP value. The graph can be
extrapolated and can be predicted from this analysis that even beyond the GHz frequency range,
the performance of the CNFET modeled inverter is much better than an MOSFET inverter.
A more detailed and accurate analysis could have been carried out if an MOSFET model
lesser than 50nm technology model was available. But due to the constraint in obtaining a much
smaller technology model (<50nm) for CMOS, simulations are carried out with the 50nm
technology model.
42
CHAPTER VI
SIMILAR RESEARCH PROGRESS ON CARBON NANOTUBE FIELD EFFECT
TRANSISTORS
As implementation of CNFET on a chip is not in existence, research is in full swing to
know more about the fabrication of CNFETs as well as studying their nature and improvising it,
if possible. Many researchers have come forward in analyzing CNTs by implementing them in
SPICE or any other similar tools for analyzing their electrical and physical properties.
This chapter deals with research work on CNTs by other researchers across the globe.
Works on either comparing the performance of CNFET with MOSFET equivalent model,
varying the properties of CNTs and testing their results or introducing parasitics to CNFET and
testing their performances.
6.1 Performance Analysis by Estimation of PDP of CNFET and MOSFET Models
A CNFET model is utilized and a D-Flip Flop is constructed in SPICE. This D-Flip Flop
is rigged up using 10 Single Edge Triggered (SET) transistors [20].
Same CNFET model which was developed by the researchers of Stanford University has
been used. The performance of CNFETs are analyzed and compared over similar digital circuit
of 32nm CMOS technology.
Below is the circuit diagram of a D-Flip Flop which utilizes 10 SET Transistors:
Figure 21. 10 Transistor SET D-FLIP FLOP [20]
43
In this research work, three possibilities are considered when constructing the D-Flip
Flop. They are:
Low Voltage Swapped Body (LVSB) bias design – In this kind of design, the bulk of all PMOS
transistors are connected to ground and bulk of all NMOS transistors are connected to the power
supply voltage (Vdd).
Sub Threshold Grounded Body (STGB) bias design - In this kind of design, the bulk or substrate
of all NMOS and PMOS transistors are connected to ground.
No Body Bias (NBB) design - In this kind of design, the bulk of all PMOS transistors are
connected to the power supply voltage (Vdd) and bulk of all NMOS transistors are connected to
ground.
Below are the simulation results for estimation of PDPs of these three scenarios for the
comparison of performances of CNFET and MOSFET circuits:
Figure 22. PDP of CNFET and MOSFET D-Flip Flop for LVSB Bias design [20]
44
Figure 23. PDP of CNFET and MOSFET D-Flip Flop for STGB Bias design [20]
Figure 24. PDP of CNFET and MOSFET D-Flip No Body Bias design [20]
From the above simulation results it can be inferred that CNFET equivalent model for a
10 Transistor SET D-Flip Flop has better performance than its CMOS counterpart. PDP has been
found to be significantly low for CNFET than the 32nm MOSFET modeled D-Flip Flop. It is
also found that the No Body Bias design would produce the least power delay product among the
three configurations.
These simulation results are very much similar to the simulations conducted in the
previous chapter. Since the digital circuit is much more complex than an inverter, the PDP has
also increased. Overall, these results prove that performance of the CNFET model based D-Flip
Flop is much greater than the MOSFET equivalent digital circuit.
45
6.2 Performance Testing of CNFET on Scalability and Parasitic Effects
In this section analysis on Schottkey Barrier CNFETs are considered. Physical properties
of the FET are changed to observe the change in performance of the device.
The diameter of the CNT is varied and the throughput or the number of switching per
second versus power dissipation is noted. Simulation results are as shown below in Figure 25:
Figure 25. Performance of an Inverter at Different Diameters of CNTs [21]
This simulation result gives information regarding the power dissipation and the
throughput of the device for different diameter sizes of CNTs. The optimum size of diameter is
considered for which throughput is high and power dissipation is low. Diameters of 0.6nm and
2nm have much less throughput. Between 1nm and 1.56nm diameters, it has been found that
power dissipation for 1.56nm is slightly higher than 1nm. Hence, choosing from the above
dimensions, diameter of 1nm is most suited among the four dimensions given [21]. Choosing this
value would yield in maximum performance of the CNT device.
Another important component is degradation in performance are the parasitic effects on
the device. Hence it is important to analyze the effects of parasitics on the FETs and test its
performance.
46
Parasitic effects have been deduced and its effects are incorporated in the CNFET model
and tested in SPICE for its performance. Its performance is compared with CNFET and
MOSFET models without parasitics.
Figure 26. Effects of Parasitics [21]
The above simulation result explains clearly the effects of parasitics on the device. A
parasitic effect, such as capacitance due to thin gate oxide layer, has been extracted to the model.
It is found that the throughput has been reduced significantly to about 8.7*8.4 times the original
throughput without the effects of parasitics. We can also observe that the performance has been
degraded and has 8.4 times less throughput than the MOSFET model without parasitic effects.
6.3 Transient Analysis between CNFET and MOSFET Comparators
In this section another experimental analysis on the transient response of CNFET and
MOSFET models are discussed.
47
An HSPICE compatible CNFET model is constructed and a comparator is rigged up. This
comparator is tested for its performance against an MOSFET model for the same circuit.
parameters like propagation delay and power dissipation is noted and analyzed.
Figure 27. Rise Time Propagation Delay for CNFET and CMOS Comparator [22]
Figure 28. Fall Time Propagation Delay for CNFET and CMOS Comparator [22]
48
Figure 27 and 28 represents the transient response for the comparators using CNFET and
MOSFET models in HSPICE. Figure 27 illustrates the rise time delay for both the models. We
observe that the delay is very small for CNFET and is quite large for MOSFET model. Similarly,
we observe same kind of response for fall delay time in Figure 28. Below are the summary of the
simulation results between CNFET and MOSFET comparators:
Table 6. Performance Comparison of CNFET and CMOS Comparators [22]
Performance
Parameters
CMOS Comparator CNFET Comparator
Rise time delay 270ns 0.13ns
Fall time delay 28ns 0.03ns
Required drive to change
state
6.5mV 0.55uV
Average power 40.26uW 8.32uW
Table 6 displays the overall results of CMOS and CNFET comparators. Performance in
terms of delays in rise and fall time, the minimum input drive required for changing state and the
average power dissipation is noted [23]. It is found that the CNFET model fares better than the
MOSFET model in the areas and is sure to be one of the major uprising technologies in near
future.
49
CHAPTER VII
SUMMARY OF THE RESEARCH
The prime objective of this research work was to study the properties of CNTs,
implement a digital circuit using the existing HSPICE compatible model and analyze the
performance from the simulation results. A comparative study has been made with a CMOS
model by testing its performance. Other research works have also been explained and are
compared with the present simulation results and performance of CNFETs versus MOSFETs are
verified.
7.1 Conclusive Remarks
Initially, the need for improvising the semiconductor technology was explained. Many
promising and upcoming technologies were discussed and it was found that CNTs are most
promising among them all. Properties of CNTs and its fabrication procedures are explained.
Implementing FETs using CNTs and designing a HSPICE compatible model was given in detail
along with the realization of its equivalent circuit. Parameters and attributes of CNTs were
explained and values are defined. This model was used to implement a digital circuit in HSPICE.
A similar digital circuit was rigged using a 50nm technology SPICE compatible model.
Comparative simulation analysis was done to compare the performances of the two models. It
was found that the CNFET model has a superior DC and transfer characteristics over the
MOSFET model. Although load driving capability is not as good as MOSFET models for high
capacitive loads due to very smaller gate dimensions. Performance was also analyzed calculating
power delay product of the two models and CNFET was found to perform much better than
MOSFET.
50
Other research simulation results like performance analysis by calculating PDP, Transient
analysis, parasitic and scalability effects are explained and found to be in good terms with the
present research work.
7.2 Scope for Future Work
This research involved analysis of the properties of CNFETs and comparison of
performance over its MOSFET counterpart, which opens many doors for further study of
CNFETs and help in realization of CNFETs to real world scenarios. This analysis would help
researchers gain knowledge about the behaviour of the digital circuits built using CNTs and
performance can be estimated once fabrications of CNFETs are possible.
The present model which has been implemented uses a relatively simplified form band
structure for MOSFET-like FETs. This has resulted in implementation of CNFETs for only
applications involving low powered digital circuits. If a more complex band structure could be
implemented, then CNFETs could be implemented for low as well as high power applications.
This research would be a benchmark for improving the existing model of the CNFET as
close to real world effects as possible by including the parasitic effects due to wiring and other
devices in the digital circuit. Model can also be improved by involving the performance changes
due to variation in temperature, pressure etc. By this kind of analysis, new methods of fabrication
of CNFETs for improved performance can be designed.
51
REFERENCES
[1]. Stefan Rusu, Manoj Sachdev, Christer Swensen, Bram Nauta “Trends and Challenges in
VLSI Technology Scaling Towards 100nm”, 15th
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55
APPENDIX
A. Inverter using CNFET .TITLE 'Inverter using CNFET'
***************************************************
*For optimal accuracy, convergence, and runtime
***************************************************
.options POST
.options AUTOSTOP
.options INGOLD=2 DCON=1
.options GSHUNT=1e-12 RMIN=1e-15
.options ABSTOL=1e-5 ABSVDC=1e-4
.options RELTOL=1e-2 RELVDC=1e-2
.options NUMDGT=4 PIVOT=13
.param TEMP=27
***************************************************
*Include relevant model files
***************************************************
.lib 'CNFET.lib' CNFET
***************************************************
*Beginning of circuit and device definitions
***************************************************
*Supplies and voltage params:
.param Supply=0.9
.param Vg='Supply'
.param Vd='Supply'
*Some CNFET parameters:
.param Ccsd=0 CoupleRatio=0
.param m_cnt=1 Efo=0.6
.param Wg=0 Cb=40e-12
.param Lg=32e-9 Lgef=100e-9
.param Vfn=0 Vfp=0
.param m=19 n=0
.param Hox=4e-9 Kox=16
* Main Circuits
*****************************************************************
Vin 1 0 pulse(0v 1v 0ns 0ns 0ns 500ns 1000ns)
Vdd 2 0 1v
* nFET
XCNT1 3 1 0 0 NCNFET Lch=Lg Lgeff='Lgef' Lss=32e-9 Ldd=32e-9
+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbn='Vfn' Dout=0 Sout=0
Pitch=20e-9 n1=m n2=n tubes=3
* pFET
XCNT2 3 1 2 2 PCNFET Lch=Lg Lgeff='Lgef' Lss=32e-9 Ldd=32e-9
+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbp='Vfp' Dout=0 Sout=0
Pitch=20e-9 n1=m n2=n tubes=3
* nFET uniform-tubes model
56
*XCNT Drain Gate Source Sub NCNFET_uniform Lch=Lg Lgeff='Lgef'
Lss=32e-9 Ldd=32e-9
*+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbn='Vfn' Dout=0 Sout=0
Pitch=20e-9 n1=m n2=n CNTPos=1 tubes=3
* pFET uniform-tubes model
*XCNT Drain Gate Source Sub PCNFET_uniform Lch=Lg Lgeff='Lgef'
Lss=32e-9 Ldd=32e-9
*+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbp='Vfp' Dout=0 Sout=0
Pitch=20e-9 n1=m n2=n CNTPOS=0 tubes=3
CL 3 0 0.1fF *CL = 0.1fF to 100fF
*****************************************************************Measu
rements
*****************************************************************
* test nFETs, Ids vs. Vgs
*.DC Vgg START=0 STOP='Supply' STEP='0.01*Supply'
*+ SWEEP Vdd START=0 STOP='Supply' STEP='0.1*Supply'
* test pFETs, Ids vs. Vgs
*.DC Vgg START=0 STOP='-Supply' STEP='-0.01*Supply'
*+ SWEEP Vdd START=0 STOP='-Supply' STEP='-0.1*Supply'
*****************************************************************
.probe V(1), V(3)
.tran 0.1ns 1500ns
.AC DEC 10 1MEG 1000MEG
.end
B. Inverter using MOSFET .TITLE 'CMOS Inverter'
***********************************************
Vin 1 0 pulse(0v 1v 0ns 0ns 0ns 40ns 80ns)
Vdd 2 0 1v
m1 3 1 0 0 N_50n L=100n W=200n *AD=1.0e-11 AS=1.0e-11
m2 3 1 2 2 P_50n L=100n W=600n *AD=3.0e-11 AS=3.0e-11
CL 3 0 100fF
* NMOS Device
.model N_50n nmos (level = 54
+binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1
geomod = 0
+diomod = 1 rdsmod = 0 rbodymod= 1
rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
57
+tnom = 27 toxe = 1.4e-009 toxp = 7e-010
toxm = 1.4e-009
+epsrox = 3.9 wint = 5e-009 lint = 1.2e-008
+ll = 0 wl = 0 lln = 1
wln = 1
+lw = 0 ww = 0 lwn = 1
wwn = 1
+lwl = 0 wwl = 0 xpart = 0
toxref = 1.4e-009
+vth0 = 0.22 k1 = 0.35 k2 = 0.05
k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 2.8
dvt1 = 0.52
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0
dvt2w = 0
+dsub = 2 minv = 0.05 voffl = 0
dvtp0 = 1e-007
+dvtp1 = 0.05 lpe0 = 5.75e-008 lpeb = 2.3e-010
xj = 2e-008
+ngate = 5e+020 ndep = 2.8e+018 nsd = 1e+020
phin = 0
+cdsc = 0.0002 cdscb = 0 cdscd = 0
cit = 0
+voff = -0.15 nfactor = 1.2 eta0 = 0.15
etab = 0
+vfb = -0.55 u0 = 0.032 ua = 1.6e-010
ub = 1.1e-017
+uc = -3e-011 vsat = 1.1e+005 a0 = 2
ags = 1e-020
+a1 = 0 a2 = 1 b0 = -1e-020
b1 = 0
+keta = 0.04 dwg = 0 dwb = 0
pclm = 0.18
+pdiblc1 = 0.028 pdiblc2 = 0.022 pdiblcb = -0.005
drout = 0.45
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008
pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.2 pditsd = 0.23
pditsl = 2.3e+006
+rsh = 3 rdsw = 150 rsw = 150
rdw = 150
+rdswmin = 0 rdwmin = 0 rswmin = 0
prwg = 0
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074
alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009
cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004
cigbinv = 0.004
58
+eigbinv = 1.1 nigbinv = 3 aigc = 0.017
bigc = 0.0028
+cigc = 0.002 aigsd = 0.017 bigsd = 0.0028
cigsd = 0.002
+nigc = 1 poxedge = 1 pigcd = 1
ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 6.238e-010 cgdo = 6.238e-010 cgbo = 2.56e-011
cgdl = 2.495e-10
+cgsl = 2.495e-10 ckappas = 0.02 ckappad = 0.02
acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.21 kt1l = 0.0 kt2 = -0.042
ute = -1.5
+ua1 = 1e-009 ub1 = -3.5e-019 uc1 = 0
prt = 0
+at = 53000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010
njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10
xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010
njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10
xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5
pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1
cjswgs = 5e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005
mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33
pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005
tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005
tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006
dmcgt = 0e-007
+dwj = 0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb = 5
rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15
ngcon = 1)
* PMOS Device
.model P_50n pmos (level = 54
+binunit = 1 paramchk= 1 mobmod = 0
59
+capmod = 2 igcmod = 1 igbmod = 1
geomod = 0
+diomod = 1 rdsmod = 0 rbodymod= 1
rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 1.4e-009 toxp = 7e-010
toxm = 1.4e-009
+epsrox = 3.9 wint = 5e-009 lint = 1.2e-008
+ll = 0 wl = 0 lln = 1
wln = 1
+lw = 0 ww = 0 lwn = 1
wwn = 1
+lwl = 0 wwl = 0 xpart = 0
toxref = 1.4e-009
+vth0 = -0.22 k1 = 0.39 k2 = 0.05
k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 3.9
dvt1 = 0.635
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0
dvt2w = 0
+dsub = 0.7 minv = 0.05 voffl = 0
dvtp0 = 0.5e-008
+dvtp1 = 0.05 lpe0 = 5.75e-008 lpeb = 2.3e-010
xj = 2e-008
+ngate = 5e+020 ndep = 2.8e+018 nsd = 1e+020
phin = 0
+cdsc = 0.000258 cdscb = 0 cdscd = 6.1e-008
cit = 0
+voff = -0.15 nfactor = 2 eta0 = 0.15
etab = 0
+vfb = 0.55 u0 = 0.0095 ua = 1.6e-009
ub = 8e-018
+uc = 4.6e-013 vsat = 90000 a0 = 1.2
ags = 1e-020
+a1 = 0 a2 = 1 b0 = -1e-020
b1 = 0
+keta = -0.047 dwg = 0 dwb = 0
pclm = 0.55
+pdiblc1 = 0.03 pdiblc2 = 0.0055 pdiblcb = 3.4e-008
drout = 0.56
+pvag = 1e-020 delta = 0.014 pscbe1 = 8.14e+008
pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.2 pditsd = 0.23
pditsl = 2.3e+006
+rsh = 3 rdsw = 250 rsw = 160
rdw = 160
+rdswmin = 0 rdwmin = 0 rswmin = 0
prwg = 3.22e-008
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074
alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009
cgidl = 0.0002
60
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004
cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.69
bigc = 0.0012
+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012
cigsd = 0.0008
+nigc = 1 poxedge = 1 pigcd = 1
ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 7.43e-010 cgdo = 7.43e-010 cgbo = 2.56e-011
cgdl = 1e-014
+cgsl = 1e-014 ckappas = 0.5 ckappad = 0.5
acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.19 kt1l = 0 kt2 = -0.052
ute = -1.5
+ua1 = -1e-009 ub1 = 2e-018 uc1 = 0
prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010
njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10
xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010
njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10
xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5
pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1
cjswgs = 5e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005
mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33
pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005
tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005
tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006
dmcgt = 0e-007
+dwj = 0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb = 5
rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15
ngcon = 1 )
.tran 0.1ns 160ns
61
.AC single V(3) 1E6 1E9
*.AC LIN V(3) START = 1E6 STOP = 1E9 STEP = 1000
*.print V(3)
.end
62
VITA
Tejas Shanmukha Swamy was born in Bengaluru, India. He received Bachelor of Engineering
degree in Electronics and Communications Engineering from PES Institute of Technology, an
Autonomous institute under Visvesvaraya Technological University, India in June 2011. He
worked for a year at HCL Technologies, Bengaluru as a VLSI Design Engineer before he was
enrolled at Texas A&M University – Kingsville in August, 2012 for Masters Program in
Electrical Engineering and successfully completed the degree works by December, 2013.
Email id: [email protected]
