HTG-S500 User Manual Altera Stratix-V Dual 40 Gig Half-Size PCI … · 2020-06-29 · HTG-S500 User...

HTG-S500 User Manual

www.HiTechGlobal.com

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Altera Stratix-V Dual 40 Gig Half-Size PCI Express Networking Card

(Financial Data Processing Platform)


Version 1.0 June 2012 Copyright © HiTech Global 2002-2012



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Disclaimer

HiTech Global does not assume any liability arising out of the application or use of any product described

or shown herein; nor does it convey any license under its patents, copyrights, or mask work rights or any

rights of others. HiTech Global reserves the right to make changes, at any time, in order to improve

reliability and functionality of this product. HiTech Global will not assume responsibility for the use of any

circuitry described herein other than circuitry entirely embodied in its products. HiTech Global provides

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information as one possible implementation of a feature, application, or standard, HiTech Global makes no

representation that such implementation is free from any claims of infringement. End users are responsible

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Revision History

Date Version Notes

6/22/2012 1.0



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Table Of Contents

Chapter 1 - Introduction to Stratix V

1.1) Summary of Stratix-V FPGA Features 4

1.2) Stratix-V Family Serial I/O Protocol Support 5

Chapter 2 – Development Platform Introduction

2.1) Introduction 8

2.2) Features & Block Diagram 8

2.3) FPGA Bank Assignment 9

2.4) Clock Distribution 11

2.5) PCI Express 12

2.6) DDR III Memory 17

2.7) QDR-II Interface 24

2.8) 40F SFP+/QSFP+ Interfaces 29

2.9) Board To Board Ports 31

2.10 USB To UART Bridge 34

2.11) LEDs 35

2.12) Configuration 35

2.13) GPS 37



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Chapter 1: Introduction to Altera Stratix-V FPGAs

1.1) Overview

The Stratix® V FPGA family includes four device variants:

Stratix-V GX FPGAs with transceivers: Integrate up to 66 full-duplex, 14.1-Gbps transceivers and

up to 6 x72-bit DIMM DDR3 memory interfaces supporting 1,066 MHz

Stratix-V GS FPGAs with enhanced digital signal processing (DSP) capabilities and transceivers:

Integrate up to 3,926 18x18, high-performance, variable-precision multipliers, 48 full-duplex,

14.1-Gbps transceivers , and up to 6 x72-bit DIMM DDR3 memory interfaces supporting 1,066

MHz

Stratix-V GT FPGAs with transceivers: Integrate four 28-Gbps transceivers and 32 full-duplex,

12.5-Gbps transceivers with up to 4 x72-bit DIMM DDR3 memory interfaces supporting 1,066

MHz

Stratix-V E FPGAs: Up to 950K logic elements (LEs), 52-megabit (Mb) RAM, 704 18x18 high-

performance, variable-precision multipliers, and 840 I/Os

Table (1) illustrates key features of the Stratix-V family.

Feature Stratix-V

E

FPGA

Stratix-V

GS

FPGA

Stratix-V

GX

FPGA

Stratix-V

GT

FPGA

High-performance adaptive logic modules

(ALMs)

359,200 262,400 359,200 234,720

Variable-precision DSP blocks (18x18) 704 3,926 798 512

M20K memory blocks 2,640 2,567 2,660 2,560

External memory interface

Partial reconfiguration

fPLL

Design security

SEU mitigation

PCI Express Gen3, Gen2, Gen1 hard IP

blocks

- Up to 2 Up to 4 1

Embedded HardCopy Blocks and hard IP -

Transceivers - 14.1 Gbps /

48

14.1 Gbps /

66

28.05 Gbps /

4

12.5 Gbps /

32

Table (1) Summary of Stratix-V FPGA Features

http://www.altera.com/devices/fpga/stratix-fpgas/stratix-v/overview/stxv-overview.html#Table1




http://www.altera.com/products/devices/stratix-fpgas/about/fpga-architecture/stx-architecture.html

http://www.altera.com/products/devices/stratix-fpgas/about/fpga-architecture/stx-architecture.html

http://www.altera.com/technology/dsp/variable-precision/dsp-variable-precision.html

http://www.altera.com/products/devices/stratix-fpgas/about/trimatrix/stx-trimatrix.html

http://www.altera.com/technology/memory/devices/stratix-v/mem-stratix-v.html

http://www.altera.com/products/devices/stratix-fpgas/stratix-v/overview/partial-reconfiguration/stxv-part-reconfig.html

http://www.altera.com/products/devices/stratix-fpgas/stratix-v/overview/fpll/stxv-fpll.html

http://www.altera.com/products/devices/stratix-fpgas/about/security/stx-design-security.html

http://www.altera.com/products/devices/stratix-fpgas/about/single-event-upset/stx-single-event-upset.html

http://www.altera.com/technology/high_speed/protocols/pcie-hard-ip/pro-hard-ip.html


http://www.altera.com/products/devices/stratix-fpgas/stratix-v/overview/hard-ip/stxv-hip-block.html

http://www.altera.com/products/devices/stratix-fpgas/stratix-v/transceivers/stxv-transceivers.html



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1.2) Stratix-V Family Serial I/O Protocol Support

Serial transceivers of the Stratix-V devices support different ranges of serial protocol standards. Table (2)

illustrates the supported standards and protocols.

Serial Protocols

V GX/GS V GT

10G-SDI

CEI-11G/SR/LR

CPRI

DisplayPort - -

Fibre Channel

HiGig2

IEEE 802.3ae

10GBASE-R

IEEE 802.3ba

10GBASE-KR

IEEE 802.3ba 40G

IEEE 802.3ba 100G

Interlaken (10G)

PCI Express®Gen3

QDR InfiniBand

QPI

SFP+

SFI-5.2

SONET OC-192

XFP

CEI-6G/SR/LR

CPRI

DDR-XAUI

DisplayPort - -

http://www.altera.com/technology/high_speed/protocols/displayport/pro-displayport.html

http://www.altera.com/technology/high_speed/protocols/fibre_channel/pro-fibre_channel.html

http://www.altera.com/technology/high_speed/protocols/higig/pro-higig.html

http://www.altera.com/devices/fpga/stratix-fpgas/stratix-iv/transceivers/stxiv-40g-100g-ip-solutions.html







http://www.altera.com/technology/high_speed/protocols/cei-6g/pro-cei-6g.html

http://www.altera.com/technology/high_speed/protocols/cpri/pro-cpri.html




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Fibre Channel

HiGig+

HyperTransportTM

3.0

Interlaken

OTU-2 (G.709)

OTU-3

OTU-4

PCI Express Gen2

SAS

SFI-4.2

SFI-5.1

SPI-4.2

SPI-5.1

3G-SDI

10-Gbps Ethernet XAUI

ASI

Basic Mode

CPRI

DDR-XAUI

DisplayPort - -

Fibre Channel

GbE

GPON

JESD204A

OBSAI

SAS

SATA

SDI SD/HD


http://www.altera.com/technology/high_speed/protocols/higig/pro-higig.html

http://www.altera.com/technology/high_speed/protocols/interlaken/pro-interlaken.html


http://www.altera.com/technology/high_speed/protocols/spi_42/pro-spi_4.2.html

http://www.altera.com/technology/high_speed/protocols/10gb_ethernet/pro-10gb_ethernet.html

http://www.altera.com/technology/high_speed/transceiver/3125/trcv-3125.html

http://www.altera.com/technology/high_speed/protocols/cpri/pro-cpri.html



http://www.altera.com/technology/high_speed/protocols/gb_ethernet/pro-gb_ethernet.html

http://www.altera.com/technology/high_speed/protocols/gpon/pro-gpon.html

http://www.altera.com/technology/high_speed/protocols/obsai/pro-obsai.html

http://www.altera.com/technology/high_speed/protocols/sdi/pro-sdi.html



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SerialLite II

Serial RapidIO®

SFP+

SFI-4.2

SGMII

SONET OC-3/OC-12/OC-48

SPI-4.2

SPI-5.1

V-by-One - -

Table (2) Stratix-V Supported Serial Protocols

http://www.altera.com/technology/high_speed/protocols/seriallite/pro-seriallite.html

http://www.altera.com/technology/high_speed/protocols/rapid_io/pro-rapid_io.html

http://www.altera.com/technology/high_speed/protocols/sgmii/pro-sgmii.html

http://www.altera.com/technology/high_speed/protocols/spi_42/pro-spi_4.2.html



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Chapter 2:Development Platform Introduction

◙ 2.1) Introduction

The HTG-S500 series are powered by Altera Stratix-V GX and GS FPGA devices with different densities

and resources in KF40-F1517 package. Designed for high performance networking applications (i.e

configurable/customizable 40Gbps NIC, 40Gbps network analyzer, etc.), these platforms provide access to

two QSFP+ (40Gbps each) IEEE802.3ba compliant Ethernet ports,, 8-lane PCI Express Gen 3 (64Gbps),

one high-speed mezzanine connector (FMC), DDR3 and QDRII memory components .

Supported by 10G / 40G Ethernet, PCI Express Gen3, DDR3, and QDR-II reference designs along with

PCI Express Linux/Windows drivers; the HTG-S500 minimizes engineering efforts for complex design

integration and verification.

◙ 2.2) Features

► Altera Stratix-V 5SGXA5, 5SGXA7, 5SGXA9, or 5SGXAB

► x8 PCI Express Gen 3 edge connector

- Supported by IDT jitter attenuator chip providing clean PCI Express clock

► x2 QSFP+ IEEE802.3ba compliant Ethernet ports (40Gbps each)- or x8 SFP+ ports using the Avago

QSFP+ to SFP+

► x10 (256M words x 16 bit) DDR3 components

► x2 144Mb(8M x18) QDR-II SRAMs

► 1PPS GPS Synchronization

► Connectors for I/O expansion, board to board communication, or multiple boards stack up

- 16 LVDS ports (through two connectors installed on the front and back side of the

board)

- 12 Serial Transceiver ports (through two connectors installed on the front and back side

of the board)

► Serial EPCS Flash

► CPLD + P30 Flash configuration

► USB/UART

► IP protection circuitry

► PCI Express or Stand-Alone mode operation

► 6.6" x 2.5"

http://hitechglobal.com/IPCores/10GigEMAC.htm

http://hitechglobal.com/IPCores/40Gig_EthernetMAC.htm



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Figure (1) Block Diagram & Placement

◙ 2.3) FPGA Bank Assignment

Common footprint of different Stratix-V devices in KF40-F1517 package allows usage of the same PCB

multiple devices as shown by table (3)



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Features 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB

Logic Elements (K) 340 420 490 622 840 952

Registers (K) 513 634 740 939 1,268 1,437

14.1-Gbps

Transceivers 36 36 36 36 36 36

PCIe hard IP Blocks 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 1, 2, or 4 1, 2, or 4

Fractional PLLs 20 24 28 28 28 28

M20K Memory Blocks 957 1,900 2,304 2,560 2,640 2,640

M20K Memory

(MBits) 19 37 45 50 52 52

Variable Precision

Multipliers (18x18) 512 512 512 512 704 704

Variable Precision

Multipliers (27x27) 256 256 256 256 352 352

DDR3 SDRAM x72

DIMM Interfaces 4 4 6 6 6 6

User I/Os, Full-Duplex LVDS, 14.1-Gbps Transceivers

Package 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB

KF40-F1517 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36H 696, 174, 36H

Table (3) Supported Stratix-V Devices

The HTG-S500 platform is available with the GXA5, GXA7, GXA9, and GXAB Stratix-V FPGAs.

Different FPGA speed grades are also supported.

FPGA bank allocation for each interface is illustrated by figure (2).

Figure (2): FPGA Bank Assignment



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◙ 2.4) Clock Distribution

For effective utilization of the FPGA resources, the HTG-S500 board is supported by different low-jitter

crystal oscillators. These clock components provide maximum performance and flexibility for different

interfaces. Figure (3) illustrates the entire board’s clock diagram.

Figure (3): Clock Diagram



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◙ 2.5) PCI Express

The PCI Express® hard intellectual property (IP) block embeds the PCI Express protocol stack into the

Altera® FPGA. The hard IP block includes the transceiver modules, physical layer, data link layer, and

transaction layer. In Stratix® V GT, GX, and GS FPGAs, the hard IP block targets PCI Express Base

Specification Rev. 3.0, 2.0, and 1.1.

The HTG-S500 provides 8 lanes of PCI Express Gen3 end-point interface (8x8Gbps) through the edge

connectors and one embedded hard block PCI Express controller. Figure (4) illustrates high level block

diagram of the PCI Express block.

Figure (4): Hard Block PCI Express Block Diagram

The interface provides data throughput of approximately about 64Gbps from a host PC to the FPGA and

vice versa.

Table (4) and (5) illustrate FPGA pins assignment for the PCI Express signals.

A Side Signal Name FPGA Pin # FPGA Pin Name

A1 PCIE_PRSNT1_

A2 +12 VOLTS

A3 +12 VOLTS

A4 GND

A5 JTAG_TCK NC

A6 JTAG_TDI NC

A7 JTAG_TDO NC

A8 JTAG_TMS NC

A9 +3.3 VOLTS NC

A10 +3.3 VOLTS NC

A11 PCIE_PERST B32

A12 GND

A13 PCIE_REFCLKP AF34 PCIE_CLK0_L0_P



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AB34 PCIE_CLK2_L1_P

A14 PCIE_REFCLKN

AF35

AB35

PCIE_CLK0_L0_N

PCIE_CLK2_L1_N

A15 GND

A16 PER0P AU36 PCIE_TX[0]_P

A17 PER0N AU37 PCIE_TX[0]_N

A18 GND

A19 RESERVED NC

A20 GND

A21 PER1P AR36 PCIE_TX[1]_P

A22 PER1N AR37 PCIE_TX[1]_N

A23 GND

A24 GND

A25 PER2P AN36 PCIE_TX[2]_P

A26 PER2N AN37 PCIE_TX[2]_N

A27 GND

A28 GND

A29 PER3P AL36 PCIE_TX[3]_P

A30 PER3N AL37 PCIE_TX[3]_N

A31 GND

A32 RESERVED NC

A33 RESERVED NC

A34 GND

A35 PER4P AG36 PCIE_TX[4]_P

A36 PER4N AG37 PCIE_TX[4]_N

A37 GND

A38 GND

A39 PER5P AE36 PCIE_TX[5]_P

A40 PER5N AE37 PCIE_TX[5]_N

A41 GND

A42 GND

A43 PER6P AC36 PCIE_TX[6]_P

A44 PER6N AC37 PCIE_TX[6]_N

A45 GND

A46 GND

A47 PER7P AA37 PCIE_TX[7]_P

A48 PER7N AA36 PCIE_TX[7]_N

A49 GND

Table (4): PCI Express Upstream Connections Summary -A Side

B Side Signal Name FPGA Pin # FPGA Pin Name

B1 +12 VOLTS

B2 +12 VOLTS

B3 +12 VOLTS

B4 GND

B5 SMCLK

B6 SMDAT

B7 GND



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B8 +3.3 VOLTS

B9 JTAG_TRST_B

B10 +3.3 VOLTSAUX

B11 PCIE_WAKE_B A32

B12 RESERVED

B13 GND

B14 PET0P AV38 PCIE_RX[0]_P

B15 PET0N AV39 PCIE_RX[0]_N

B16 GND

B17 PCIE_PRSNT2_B

B18 GND

B19 PET1P AT38 PCIE_RX[1]_P

B20 PET1N AT39 PCIE_RX[1]_N

B21 GND

B22 GND

B23 PET2P AP38 PCIE_RX[2]_P

B24 PET2N AP39 PCIE_RX[2]_N

B25 GND

B26 GND

B27 PET3P AM38 PCIE_RX[3]_P

B28 PET3N AM39 PCIE_RX[3]_N

B29 GND

B30 RESERVED

B31 PCIE_PRSNT2_B

B32 GND

B33 PET4P AH38 PCIE_RX[4]_P

B34 PET4N AH39 PCIE_RX[4]_N

B35 GND

B36 GND

B37 PET5P AF38 PCIE_RX5]_P

B38 PET5N AF39 PCIE_RX[5]_N

B39 GND

B40 GND

B41 PET6P AD38 PCIE_RX[6]_P

B42 PET6N AD39 PCIE_RX[6]_N

B43 GND

B44 GND

B45 PET7P AB38 PCIE_RX[7]_P

B46 PET7N AB39 PCIE_RX[7]_N

B47 GND

B48 PCIE_PRSNT2_B

B49 GND

Table (5) PCI Express FPGA Pin Assignments



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2.5.1) PCI Express Clock

Figure (5) illustrates different sources for creation of required clock for PCI Express interface.

Figure (5): PCI Express Clock Circuit

To clean the 100MHz clock provided by host PC or Server, the HTG-S500 board is equipped with IDT

PCI Express Jitter Attenuator chip (ICS871S1022). The ICS871S1022 is a PLL-based clock generator

specifically designed by IDT for PCI Express Clock Generation applications. The device generates

100MHz, 125MHz, 250MHz or 500MHz from either a 25MHz fundamental mode crystal or a 100MHz

recovered clock.

The ICS871S1022 has two modes of operation: (1) high frequency jitter attenuator and (2) high

performance clock synthesizer mode. When in jitter attenuator mode, the ICS871S1022 is able to both

suppress high frequency noise components and function as a frequency translator. Designed to receive a

jittery and noisy clock from an external source, the ICS871S1022 uses FemtoClock® technology to clean

up the incoming clock and translate the frequency to one of the four common PCI Express frequencies.

When in synthesizer mode, the device is able to generate high performance SSC and non-SSC clocks from a

low cost external, 25MHz, fundamental mode crystal. The ICS871S1022 uses FemtoClock® technology to

generate low noise clock outputs capable of providing the seed frequencies for the common PCI

Express link rates.

The first two differential outputs (PCIE_CLK0 and PCIE_CLK2) of the Jitter Attenuator chip are used as

reference clocks for the serial transceivers of the Stratix-V FPGA use for the PHY interface. The 3rd

output

is used as Global Clock to the FPGA (as shown by figure (6) , the OEB signal should be pulled up to 3.3V)



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Figure (6): Jitter Attenuator Output Diagram

Table (6) illustrates different settings of the Jitter Attenuator chip for different output frequencies.

Inputs

CLK_SEL Input Frequency (MHz) N1:N0 N Divider Value Output Frequency

(MHz)

0 100 00 5 100

0 100 01 4 125

0 100 10 2 250

0 100 11 1 500

Table (6): Jitter Attenuator Output Setting



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◙ 2.6) DDR-III Interface

The HTG-S500 platform is populated with total of ten, 32Meg x 16 (4Gb) DDR3 components (Micron

MT41J256M16RE-125 or ISSI IS43TR16256A-125KBL)

Table (7) illustrates FPGA pin assignment for the DDR3 interfaces:

DDR3 Signal Name FPGA Pin #

DDR3_A_A[0] D21

DDR3_A_A[1] B23

DDR3_A_A[2] C22

DDR3_A_A[3] J22

DDR3_A_A[4] A23

DDR3_A_A[5] J21

DDR3_A_A[6] F23

DDR3_A_A[7] K21

DDR3_A_A[8] G23

DDR3_A_A[9] E23

DDR3_A_A[10] B20

DDR3_A_A[11] G22

DDR3_A_A[12] B22

DDR3_A_A[13] H23

DDR3_A_A[14] H22

DDR3_A_BA[0] H20

DDR3_A_BA[1] D22

DDR3_A_BA[2] A20

DDR3_A_CAS_N E21

DDR3_A_CK_N C21

DDR3_A_CK_P C20

DDR3_A_CKE0 A22

DDR3_A_CS0_N G21

DDR3_A_ODT0 G20

DDR3_A_RAS_N F21

DDR3_A_RST_N F20

DDR3_A_WE_N E20

DDR3_A_DM[0] C24

DDR3_A_DM[1] P26

DDR3_A_DM[2] C28

DDR3_A_DM[3] N28

DDR3_A_DM[4] B26

DDR3_A_DM[5] P28

DDR3_A_DM[6] E30



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DDR3_A_DM[7] L30

DDR3_A_DM[8] G34

DDR3_A_DM[9] L33

DDR3_A_DQ[0] D24

DDR3_A_DQ[1] D25

DDR3_A_DQ[2] F24

DDR3_A_DQ[3] A25

DDR3_A_DQ[4] C25

DDR3_A_DQ[5] H25

DDR3_A_DQ[6] G24

DDR3_A_DQ[7] G25

DDR3_A_DQ[8] J25

DDR3_A_DQ[9] N26

DDR3_A_DQ[10] L26

DDR3_A_DQ[11] T25

DDR3_A_DQ[12] N25

DDR3_A_DQ[13] U25

DDR3_A_DQ[14] M26

DDR3_A_DQ[15] P25

DDR3_A_DQ[16] A28

DDR3_A_DQ[17] A29

DDR3_A_DQ[18] G28

DDR3_A_DQ[19] E28

DDR3_A_DQ[20] B28

DDR3_A_DQ[21] F29

DDR3_A_DQ[22] H28

DDR3_A_DQ[23] D28

DDR3_A_DQ[24] J29

DDR3_A_DQ[25] M29

DDR3_A_DQ[26] V29

DDR3_A_DQ[27] R29

DDR3_A_DQ[28] J28

DDR3_A_DQ[29] P29

DDR3_A_DQ[30] U29

DDR3_A_DQ[31] K28

DDR3_A_DQ[32] E27

DDR3_A_DQ[33] C27

DDR3_A_DQ[34] G26

DDR3_A_DQ[35] J26

DDR3_A_DQ[36] D27

DDR3_A_DQ[37] F26



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DDR3_A_DQ[38] H26

DDR3_A_DQ[39] A26

DDR3_A_DQ[40] K27

DDR3_A_DQ[41] R27

DDR3_A_DQ[42] J27

DDR3_A_DQ[43] U27

DDR3_A_DQ[44] L27

DDR3_A_DQ[45] U26

DDR3_A_DQ[46] N27

DDR3_A_DQ[47] T27

DDR3_A_DQ[48] E31

DDR3_A_DQ[49] B31

DDR3_A_DQ[50] G30

DDR3_A_DQ[51] D30

DDR3_A_DQ[52] F30

DDR3_A_DQ[53] C30

DDR3_A_DQ[54] G31

DDR3_A_DQ[55] A31

DDR3_A_DQ[56] K31

DDR3_A_DQ[57] M30

DDR3_A_DQ[58] J31

DDR3_A_DQ[59] R31

DDR3_A_DQ[60] L31

DDR3_A_DQ[61] R30

DDR3_A_DQ[62] K30

DDR3_A_DQ[63] N30

DDR3_A_DQ[64] G32

DDR3_A_DQ[65] H34

DDR3_A_DQ[66] F32

DDR3_A_DQ[67] J34

DDR3_A_DQ[68] G33

DDR3_A_DQ[69] K33

DDR3_A_DQ[70] E32

DDR3_A_DQ[71] J33

DDR3_A_DQ[72] N33

DDR3_A_DQ[73] L34

DDR3_A_DQ[74] R32

DDR3_A_DQ[75] T31

DDR3_A_DQ[76] N34

DDR3_A_DQ[77] U31

DDR3_A_DQ[78] P32



20

DDR3_A_DQ[79] M33

DDR3_A_DQS_N[0] E25

DDR3_A_DQS_N[1] R26

DDR3_A_DQS_N[2] G29

DDR3_A_DQS_N[3] T30

DDR3_A_DQS_N[4] F27

DDR3_A_DQS_N[5] T28

DDR3_A_DQS_N[6] C31

DDR3_A_DQS_N[7] N31

DDR3_A_DQS_N[8] E33

DDR3_A_DQS_N[9] M32

DDR3_A_DQS_P[0] E24

DDR3_A_DQS_P[1] R25

DDR3_A_DQS_P[2] H29

DDR3_A_DQS_P[3] U30

DDR3_A_DQS_P[4] G27

DDR3_A_DQS_P[5] U28

DDR3_A_DQS_P[6] D31

DDR3_A_DQS_P[7] P31

DDR3_A_DQS_P[8] F33

DDR3_A_DQS_P[9] N32

DDR3_B_A[0] F18

DDR3_B_A[1] B16

DDR3_B_A[2] H16

DDR3_B_A[3] K19

DDR3_B_A[4] C16

DDR3_B_A[5] H17

DDR3_B_A[6] A16

DDR3_B_A[7] A19

DDR3_B_A[8] E17

DDR3_B_A[9] B19

DDR3_B_A[10] D19

DDR3_B_A[11] D16

DDR3_B_A[12] A17

DDR3_B_A[13] C18

DDR3_B_A[14] F17

DDR3_B_BA[0] K18

DDR3_B_BA[1] B17

DDR3_B_BA[2] G16

DDR3_B_CAS_N G18

DDR3_B_CK_N E19



21

DDR3_B_CK_P E18

DDR3_B_CKE0 D18

DDR3_B_CS0_N J18

DDR3_B_ODT0 H19

DDR3_B_RAS_N G19

DDR3_B_RST_N C19

DDR3_B_WE_N G17

DDR3_B_DM[0] E14

DDR3_B_DM[1] N14

DDR3_B_DM[2] E12

DDR3_B_DM[3] L12

DDR3_B_DM[4] G11

DDR3_B_DM[5] T10

DDR3_B_DM[6] K6

DDR3_B_DM[7] A5

DDR3_B_DM[8] B8

DDR3_B_DM[9] R9

DDR3_B_DQ[0] F14

DDR3_B_DQ[1] C15

DDR3_B_DQ[2] G15

DDR3_B_DQ[3] B14

DDR3_B_DQ[4] F15

DDR3_B_DQ[5] A14

DDR3_B_DQ[6] G14

DDR3_B_DQ[7] C14

DDR3_B_DQ[8] L15

DDR3_B_DQ[9] U12

DDR3_B_DQ[10] J15

DDR3_B_DQ[11] U13

DDR3_B_DQ[12] M14

DDR3_B_DQ[13] U14

DDR3_B_DQ[14] K15

DDR3_B_DQ[15] T13

DDR3_B_DQ[16] C12

DDR3_B_DQ[17] H13

DDR3_B_DQ[18] A13

DDR3_B_DQ[19] G12

DDR3_B_DQ[20] D12

DDR3_B_DQ[21] F12

DDR3_B_DQ[22] B13

DDR3_B_DQ[23] G13



22

DDR3_B_DQ[24] N12

DDR3_B_DQ[25] J12

DDR3_B_DQ[26] U11

DDR3_B_DQ[27] P13

DDR3_B_DQ[28] M12

DDR3_B_DQ[29] N13

DDR3_B_DQ[30] T12

DDR3_B_DQ[31] K12

DDR3_B_DQ[32] D10

DDR3_B_DQ[33] H10

DDR3_B_DQ[34] A11

DDR3_B_DQ[35] J10

DDR3_B_DQ[36] B10

DDR3_B_DQ[37] H11

DDR3_B_DQ[38] C10

DDR3_B_DQ[39] A10

DDR3_B_DQ[40] R11

DDR3_B_DQ[41] U9

DDR3_B_DQ[42] R10

DDR3_B_DQ[43] N10

DDR3_B_DQ[44] J11

DDR3_B_DQ[45] K10

DDR3_B_DQ[46] P11

DDR3_B_DQ[47] P10

DDR3_B_DQ[48] M6

DDR3_B_DQ[49] K7

DDR3_B_DQ[50] N6

DDR3_B_DQ[51] H7

DDR3_B_DQ[52] P7

DDR3_B_DQ[53] J7

DDR3_B_DQ[54] N7

DDR3_B_DQ[55] L6

DDR3_B_DQ[56] A6

DDR3_B_DQ[57] E6

DDR3_B_DQ[58] E7

DDR3_B_DQ[59] A3

DDR3_B_DQ[60] F6

DDR3_B_DQ[61] A4

DDR3_B_DQ[62] D7

DDR3_B_DQ[63] D6

DDR3_B_DQ[64] C9



23

DDR3_B_DQ[65] C8

DDR3_B_DQ[66] D9

DDR3_B_DQ[67] F8

DDR3_B_DQ[68] E8

DDR3_B_DQ[69] G8

DDR3_B_DQ[70] A8

DDR3_B_DQ[71] G9

DDR3_B_DQ[72] T9

DDR3_B_DQ[73] N9

DDR3_B_DQ[74] P8

DDR3_B_DQ[75] J9

DDR3_B_DQ[76] M8

DDR3_B_DQ[77] K9

DDR3_B_DQ[78] N8

DDR3_B_DQ[79] L8

DDR3_B_DQS_N[0] D15

DDR3_B_DQS_N[1] P14

DDR3_B_DQS_N[2] C13

DDR3_B_DQS_N[3] K13

DDR3_B_DQS_N[4] E11

DDR3_B_DQS_N[5] L11

DDR3_B_DQS_N[6] G6

DDR3_B_DQS_N[7] A7

DDR3_B_DQS_N[8] F9

DDR3_B_DQS_N[9] L9

DDR3_B_DQS_P[0] E15

DDR3_B_DQS_P[1] R14

DDR3_B_DQS_P[2] D13

DDR3_B_DQS_P[3] L13

DDR3_B_DQS_P[4] F11

DDR3_B_DQS_P[5] M11

DDR3_B_DQS_P[6] G7

DDR3_B_DQS_P[7] B7

DDR3_B_DQS_P[8] G10

DDR3_B_DQS_P[9] M9

REF_CLK_DDR3_A M23

REF_CLK_DDR3_B P16

Table (7) DDR3 FPGA Pin Assignment



24

2.6.1) DDR3 Clock

Figure (7) illustrates clock generation through the onboard 100MHz Oscillator (U13) and clock buffer

(U14)

Figure (7): DDR3 Clock Circuit

◙ 2.7) QDRII Memory

The HTG-S500 board is supported by two independent 8MX18 (144Mbit) Cypress QDRII SRAM

components (CY7C2663KV18). Each component is connected to the onboard Stratix-V FPGA via separate

address and data lines.

The CY7C2663KV18 is a 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture.

Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the

write port to access the memory array. The read port has dedicated data outputs to support read

operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture

has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus

that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for

read and write addresses are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize

data throughput, both read and write ports are equipped with DDR interfaces. Each address location is

associated with four 18-bit words that burst sequentially into or out of the device. Because data is

transferred into and out of the device on every rising edge of both input clocks (K and K), memory

bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”.

The device has an ODT feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area, and simplify board routing. Depth

expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs

pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Figure (8) illustrates block diagram of the QDR II device.



25

Figure (8): QDR-II Block Diagram

Additional product information is available at http://www.cypress.com/?mpn=CY7C2663KV18-450BZXC

Table (8) illustrates pin assignment for each QDR-II SRAM component.

QDRII Signal Name FPGA Pin #

QDRII_A_A[0] AL13

QDRII_A_A[1] AG13

QDRII_A_A[2] AM14

QDRII_A_A[3] AH15

QDRII_A_A[4] AK15

QDRII_A_A[5] AJ15

QDRII_A_A[6] AL14

QDRII_A_A[7] AK14

QDRII_A_A[8] AH13

QDRII_A_A[9] AA13

QDRII_A_A[10] AC13

QDRII_A_A[11] AD14

QDRII_A_A[12] AJ13

QDRII_A_A[13] AA12

QDRII_A_A[14] AB13

QDRII_A_A[15] AC14

QDRII_A_A[16] AF13

QDRII_A_A[17] AF14

QDRII_A_A[18] AN13

QDRII_A_A[19] AE14

QDRII_A_A[20] AN12

http://www.cypress.com/?mpn=CY7C2663KV18-450BZXC



26

QDRII_A_A[21] AE15

QDRII_A_BWS0 AW10

QDRII_A_BWS1 AU9

QDRII_A_CQ_N AH12

QDRII_A_CQ_P AR11

QDRII_A_D[0] AG10

QDRII_A_D[1] AC10

QDRII_A_D[2] AF10

QDRII_A_D[3] AH10

QDRII_A_D[4] AJ10

QDRII_A_D[5] AL10

QDRII_A_D[6] AM10

QDRII_A_D[7] AU10

QDRII_A_D[8] AV10

QDRII_A_D[9] AT9

QDRII_A_D[10] AR9

QDRII_A_D[11] AP9

QDRII_A_D[12] AN9

QDRII_A_D[13] AC9

QDRII_A_D[14] AD9

QDRII_A_D[15] AE9

QDRII_A_D[16] AG9

QDRII_A_D[17] AH9

QDRII_A_DOFF AB9

QDRII_A_K_N AP10

QDRII_A_K_P AN10

QDRII_A_ODT AB10

QDRII_A_Q[0] AD12

QDRII_A_Q[1] AE12

QDRII_A_Q[2] AJ12

QDRII_A_Q[3] AK12

QDRII_A_Q[4] AL12

QDRII_A_Q[5] AR12

QDRII_A_Q[6] AT12

QDRII_A_Q[7] AT11

QDRII_A_Q[8] AU11

QDRII_A_Q[9] AN11

QDRII_A_Q[10] AM11

QDRII_A_Q[11] AK11

QDRII_A_Q[12] AB12

QDRII_A_Q[13] AL11



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QDRII_A_Q[14] AC12

QDRII_A_Q[15] AE10

QDRII_A_Q[16] AF11

QDRII_A_Q[17] AG12

QDRII_A_QVLD AE11

QDRII_A_RPS AG14

QDRII_A_WSP AM13

QDRII_B_A[0] AB15

QDRII_B_A[1] AA15

QDRII_B_A[2] AR14

QDRII_B_A[3] AV13

QDRII_B_A[4] AT14

QDRII_B_A[5] AU15

QDRII_B_A[6] AG15

QDRII_B_A[7] AC15

QDRII_B_A[8] AB16

QDRII_B_A[9] AL15

QDRII_B_A[10] AP12

QDRII_B_A[11] AD15

QDRII_B_A[12] AA14

QDRII_B_A[13] AN15

QDRII_B_A[14] AN14

QDRII_B_A[15] AP13

QDRII_B_A[16] AD16

QDRII_B_A[17] AW14

QDRII_B_A[18] AR15

QDRII_B_A[19] AW13

QDRII_B_A[20] AP15

QDRII_B_A[21] AU14

QDRII_B_BWS0 AM16

QDRII_B_BWS1 AM17

QDRII_B_CQ_N AF19

QDRII_B_CQ_P AN19

QDRII_B_D[0] AJ17

QDRII_B_D[1] AG17

QDRII_B_D[2] AG16

QDRII_B_D[3] AH16

QDRII_B_D[4] AF16

QDRII_B_D[5] AE16

QDRII_B_D[6] AK17

QDRII_B_D[7] AL16



28

QDRII_B_D[8] AL17

QDRII_B_D[9] AN17

QDRII_B_D[10] AT17

QDRII_B_D[11] AR17

QDRII_B_D[12] AU16

QDRII_B_D[13] AU17

QDRII_B_D[14] AV17

QDRII_B_D[15] AV16

QDRII_B_D[16] AW16

QDRII_B_D[17] AW17

QDRII_B_DOFF AE18

QDRII_B_K_N AP16

QDRII_B_K_P AN16

QDRII_B_ODT AD17

QDRII_B_Q[0] AL18

QDRII_B_Q[1] AN18

QDRII_B_Q[2] AK18

QDRII_B_Q[3] AJ18

QDRII_B_Q[4] AP18

QDRII_B_Q[5] AH18

QDRII_B_Q[6] AG18

QDRII_B_Q[7] AP19

QDRII_B_Q[8] AR18

QDRII_B_Q[9] AE19

QDRII_B_Q[10] AG19

QDRII_B_Q[11] AH19

QDRII_B_Q[12] AJ19

QDRII_B_Q[13] AM19

QDRII_B_Q[14] AU18

QDRII_B_Q[15] AW19

QDRII_B_Q[16] AR19

QDRII_B_Q[17] AV19

QDRII_B_QVLD AT18

QDRII_B_RPS AV14

QDRII_B_WSP AT15

REF_CLK_QDRII_AB AF17

Table (8) QDRII Interface FPGA Pin Assignment



29

2.71) QDR-II Clock

Figure (9) illustrates clock generation through the onboard 100MHz Oscillator (U13) and clock buffer

(U14)

Figure (9) QDRII Clock Generation

◙ 2.8) 40G /QSFP+ Interfaces

Providing aggregated data rate of 80 Gbps through the front panel ports, the HTG-S500 board is supported

by two QSFP+ (40Gbps each) connectors. The QSFP+ ports are connected to eight serial transceivers of

the Stratix-V FPGA and clocked through either the on board 644.53125 MHz oscillators (U21). Using the

Avago Technologies AFBR-79E4Z –D (or equivalent solutions), each QSFP+ port can be used as four

SFP+ interfaces.

The AFBR-79E4Z -D is a Four-Channel Pluggable, Parallel, Fiber-Optic QSFP + Transceiver for

40GBASE-SR4 applications. This transceiver is a high performance module for short-range multi-lane data

communication and interconnect applications. It integrates four data lanes in each direction with 40 Gbps

aggregate bandwidth. Each lane can operate at 10.3125 Gbps up to 100 m using OM3 fiber. These

modules are designed to operate over multimode fiber systems using a nominal wavelength of 850nm. The

electrical interface uses a 38 contact edge type connector. The optical interface uses an 8 or 12 fiber

MTP® (MPO) connector.

Table (9) illustrates FPGA pin assignment for the QSFP+ port 0 and 1.

QSFP+ Signal Name FPGA Pin #

QSFP0_RX1_N H1

QSFP0_RX1_P H2

QSFP0_RX2_N K1

QSFP0_RX2_P K2

QSFP0_RX3_N M1

QSFP0_RX3_P M2

QSFP0_RX4_N P1

QSFP0_RX4_P P2

QSFP0_TX1_N G3

QSFP0_TX1_P G4



30

QSFP0_TX2_N J3

QSFP0_TX2_P J4

QSFP0_TX3_N L3

QSFP0_TX3_P L4

QSFP0_TX4_N N3

QSFP0_TX4_P N4

QSFP1_RX1_N H39

QSFP1_RX1_P H38

QSFP1_RX2_N K39

QSFP1_RX2_P K38

QSFP1_RX3_N M39

QSFP1_RX3_P M38

QSFP1_RX4_N P39

QSFP1_RX4_P P38

QSFP1_TX1_N G37

QSFP1_TX1_P G36

QSFP1_TX2_N J37

QSFP1_TX2_P J36

QSFP1_TX3_N L37

QSFP1_TX3_P L36

QSFP1_TX4_N N37

QSFP1_TX4_P N36

QSFP1_SDA_F AL30

QSFP1_IntL_F AK30

QSFP1_ModPrsL_F AM29

QSFP0_IntL_F AL29

QSFP1_RST_N_F AR28

QSFP0_SCL_F AP28

QSFP0_SDA_F AL28

QSFP0_RST_N_F AL27

QSFP0_ModPrsL_F AN28

QSFP1_SCL_F AM28

Table (9) QSFP+ Ports FPGA Pin Assignment



31

◙ 2.9 Board To Board Ports

The HTG-S500 board is supported with two pairs of board to board connectors providing access to 8 LVDS

(J11 and J4) and 6 Serial I/Os (J10 and J5)

Table (10) illustrates FPGA and connector pin assignments.

Board To Board Signal Name FPGA Pin # Connector #

B2B_Gb_QSE_RX0_N AF1 J10

B2B_Gb_QSE_RX0_P AF2 J10

B2B_Gb_QSE_RX1_N AD1 J10

B2B_Gb_QSE_RX1_P AD2 J10

B2B_Gb_QSE_RX2_N AB1 J10

B2B_Gb_QSE_RX2_P AB2 J10

B2B_Gb_QSE_RX3_N T1 J10

B2B_Gb_QSE_RX3_P T2 J10

B2B_Gb_QSE_RX4_N V1 J10

B2B_Gb_QSE_RX4_P V2 J10

B2B_Gb_QSE_RX5_N Y1 J10

B2B_Gb_QSE_RX5_P Y2 J10

B2B_Gb_QSE_TX0_N AE3 J10

B2B_Gb_QSE_TX0_P AE4 J10

B2B_Gb_QSE_TX1_N AC3 J10

B2B_Gb_QSE_TX1_P AC4 J10

B2B_Gb_QSE_TX2_N AA3 J10

B2B_Gb_QSE_TX2_P AA4 J10

B2B_Gb_QSE_TX3_N R3 J10

B2B_Gb_QSE_TX3_P R4 J10

B2B_Gb_QSE_TX4_N U3 J10

B2B_Gb_QSE_TX4_P U4 J10

B2B_Gb_QSE_TX5_N W3 J10

B2B_Gb_QSE_TX5_P W4 J10

B2B_Gb_QTE_RX0_N AV1 J5

B2B_Gb_QTE_RX0_P AV2 J5

B2B_Gb_QTE_RX1_N AT1 J5

B2B_Gb_QTE_RX1_P AT2 J5

B2B_Gb_QTE_RX2_N AP1 J5

B2B_Gb_QTE_RX2_P AP2 J5

B2B_Gb_QTE_RX3_N AM1 J5

B2B_Gb_QTE_RX3_P AM2 J5

B2B_Gb_QTE_RX4_N AK1 J5

B2B_Gb_QTE_RX4_P AK2 J5



32

B2B_Gb_QTE_RX5_N AH1 J5

B2B_Gb_QTE_RX5_P AH2 J5

B2B_Gb_QTE_TX0_N AU3 J5

B2B_Gb_QTE_TX0_P AU4 J5

B2B_Gb_QTE_TX1_N AR3 J5

B2B_Gb_QTE_TX1_P AR4 J5

B2B_Gb_QTE_TX2_N AN3 J5

B2B_Gb_QTE_TX2_P AN4 J5

B2B_Gb_QTE_TX3_N AL3 J5

B2B_Gb_QTE_TX3_P AL4 J5

B2B_Gb_QTE_TX4_N AJ3 J5

B2B_Gb_QTE_TX4_P AJ4 J5

B2B_Gb_QTE_TX5_N AG3 J5

B2B_Gb_QTE_TX5_P AG4 J5

B2B_Gb_R0_CLK0_N AF5

B2B_Gb_R0_CLK0_P AF6

B2B_Gb_R0_CLK1_N AD6

B2B_Gb_R0_CLK1_P AD7

B2B_Gb_R1_CLK2_N AB5

B2B_Gb_R1_CLK2_P AB6

B2B_LVDS_QSH_CLK_I_N AL23

B2B_LVDS_QSH_CLK_I_P AK23

B2B_LVDS_QSH_CLK_O_N AE21

B2B_LVDS_QSH_CLK_O_P AE20

B2B_LVDS_QSH_RX0_N AG23 J11

B2B_LVDS_QSH_RX0_P AF23 J11

B2B_LVDS_QSH_RX1_N AL22 J11

B2B_LVDS_QSH_RX1_P AK21 J11

B2B_LVDS_QSH_RX2_N AN23 J11

B2B_LVDS_QSH_RX2_P AM23 J11

B2B_LVDS_QSH_RX3_N AR22 J11

B2B_LVDS_QSH_RX3_P AP22 J11

B2B_LVDS_QSH_RX4_N AW22 J11

B2B_LVDS_QSH_RX4_P AV22 J11

B2B_LVDS_QSH_RX5_N AP21 J11

B2B_LVDS_QSH_RX5_P AN21 J11

B2B_LVDS_QSH_RX6_N AU21 J11

B2B_LVDS_QSH_RX6_P AT21 J11

B2B_LVDS_QSH_RX7_N AR21 J11

B2B_LVDS_QSH_RX7_P AR20 J11

B2B_LVDS_QSH_RX8_N AL21 J11



33

B2B_LVDS_QSH_RX8_P AL20 J11

B2B_LVDS_QSH_TX0_N AE23 J11

B2B_LVDS_QSH_TX0_P AD23 J11

B2B_LVDS_QSH_TX1_N AG22 J11

B2B_LVDS_QSH_TX1_P AF22 J11

B2B_LVDS_QSH_TX2_N AJ21 J11

B2B_LVDS_QSH_TX2_P AJ20 J11

B2B_LVDS_QSH_TX3_N AN22 J11

B2B_LVDS_QSH_TX3_P AM22 J11

B2B_LVDS_QSH_TX4_N AU23 J11

B2B_LVDS_QSH_TX4_P AT23 J11

B2B_LVDS_QSH_TX5_N AW23 J11

B2B_LVDS_QSH_TX5_P AV23 J11

B2B_LVDS_QSH_TX6_N AM20 J11

B2B_LVDS_QSH_TX6_P AN20 J11

B2B_LVDS_QSH_TX7_N AU20 J11

B2B_LVDS_QSH_TX7_P AT20 J11

B2B_LVDS_QSH_TX8_N AW20 J11

B2B_LVDS_QSH_TX8_P AV20 J11

B2B_LVDS_QTH_CLK_I_N AJ22 J11

B2B_LVDS_QTH_CLK_I_P AH22 J11

B2B_LVDS_QTH_CLK_O_N AE24 J11

B2B_LVDS_QTH_CLK_O_P AD24 J11

B2B_LVDS_QTH_RX0_N AN27 J4

B2B_LVDS_QTH_RX0_P AN26 J4

B2B_LVDS_QTH_RX1_N AR27 J4

B2B_LVDS_QTH_RX1_P AP27 J4

B2B_LVDS_QTH_RX2_N AL24 J4

B2B_LVDS_QTH_RX2_P AL25 J4

B2B_LVDS_QTH_RX3_N AR25 J4

B2B_LVDS_QTH_RX3_P AP25 J4

B2B_LVDS_QTH_RX4_N AW26 J4

B2B_LVDS_QTH_RX4_P AV26 J4

B2B_LVDS_QTH_RX5_N AU25 J4

B2B_LVDS_QTH_RX5_P AU24 J4

B2B_LVDS_QTH_RX6_N AP24 J4

B2B_LVDS_QTH_RX6_P AN24 J4

B2B_LVDS_QTH_RX7_N AG24 J4

B2B_LVDS_QTH_RX7_P AH24 J4

B2B_LVDS_QTH_RX8_N AA25 J4

B2B_LVDS_QTH_RX8_P AB25 J4



34

B2B_LVDS_QTH_TX0_N AU27 J4

B2B_LVDS_QTH_TX0_P AT27 J4

B2B_LVDS_QTH_TX1_N AU26 J4

B2B_LVDS_QTH_TX1_P AT26 J4

B2B_LVDS_QTH_TX2_N AW25 J4

B2B_LVDS_QTH_TX2_P AV25 J4

B2B_LVDS_QTH_TX3_N AM26 J4

B2B_LVDS_QTH_TX3_P AL26 J4

B2B_LVDS_QTH_TX4_N AT24 J4

B2B_LVDS_QTH_TX4_P AR24 J4

B2B_LVDS_QTH_TX5_N AG26 J4

B2B_LVDS_QTH_TX5_P AF26 J4

B2B_LVDS_QTH_TX6_N AN25 J4

B2B_LVDS_QTH_TX6_P AM25 J4

B2B_LVDS_QTH_TX7_N AK24 J4

B2B_LVDS_QTH_TX7_P AJ24 J4

B2B_LVDS_QTH_TX8_N AE26 J4

B2B_LVDS_QTH_TX8_P AD26 J4

Table (10): Board To Board Connectors FPGA Pin Assignment

◙ 2.10) USB To UART Bridge

The HTG-S500 board provides one UART port through a peripheral USB connector. The port is supported

by the Silicon labs CP2103 (U11) USB to UART controller chip.

The CP2103 is a highly-integrated USB-to-UART Bridge Controller providing a simple solution for

updating RS-232/RS-485 designs to USB using a minimum of components and PCB space. The CP2103

includes a USB 2.0 full-speed function controller, USB transceiver, oscillator, EEPROM, and

asynchronous serial data bus (UART) with full modem control signals . No other external USB components

are required.

The on-chip EEPROM may be used to customize the USB Vendor ID, Product ID, Product Description

String, Power Descriptor, Device Release Number, and Device Serial Number as desired for OEM

applications. The EEPROM is programmed on-board via the USB, allowing the programming step to be

easily integrated into the product manufacturing and testing process.

Royalty-free Virtual COM Port (VCP) device drivers provided by Silicon Laboratories allow a CP2103-

based product to appear as a COM port to PC applications. The CP2103 UART interface implements all

RS-232/RS-485 signals, including control and handshaking signals; so, existing system firmware does not

need to be modified. The device also features up to four GPIO signals that can be user-defined for status

and control information. Support for I/O interface voltages down to 1.8 V is provided via a VIO pin. In

many existing RS-232 designs, all that is required to update the design from RS-232 to USB is to replace

the RS-232 level-translator with the CP2103.

Direct access driver support is available through the Silicon Laboratories USBXpress driver set. Go to

www.silabs.com for the latest application notes and product support information for CP2103.

Table (11) illustrates FPGA pin assignment for the USB-TO-UART interface:



35

UART/USB Bridge (U11) Signal Name FPGA Pin #

UART_GPIO1 AE30

UART_DCD AD30

UART_RI AC30

UART_GPIO0 AB30

UART_TXD AB28

UART_GPIO3 AG30

UART_SUSPEND_N AF29

UART_GPIO2 AE29

UART_RST_N AF28

UART_DTR AA27

UART_DSR AA26

UART_RTS AC27

UART_RXD AB27

USB_PERI_PWR AE27

UART_CTS AD27

Table (11): USB To UART FPGA pin assignment

◙ 2.11) LEDs

Table (12) illustrates FPGA pin assignment for user LEDs

Signal Name FPGA Pin #

FPGA_USER_LED2 AT6

FPGA_USER_LED1 AR7

FPGA_USER_LED0 AR6

Table (12): User LED Interface FPGA pin assignment

◙ 2.12) Configuration

The HTG-S500 can be configured using one of the following options:

- JTAG header (J3)

- CPLD and FLASH Devices (U2 and U31)

- PCI Express (requires custom FPGA design)

Additional details for configuration of Stratix-V devices is available

http://www.altera.com/literature/hb/stratix-v/stx5_51010.pdf

Table (13) illustrates FPGA pin assignment for the CPLD and FLASH interfaces.


FPGA_D[0] AP33

FPGA_D[1] AT33

FPGA_D[2] AR33

FPGA_D[3] AU34

FPGA_D[4] AU33

http://www.altera.com/literature/hb/stratix-v/stx5_51010.pdf



36

FPGA_D[5] AN31

FPGA_D[6] AM31

FPGA_D[7] AU32

FPGA_D[8] AT32

FPGA_D[9] AR31

FPGA_D[10] AP31

FPGA_D[11] AW34

FPGA_D[12] AV34

FPGA_D[13] AW31

FPGA_D[14] AV31

FPGA_D[15] AW32

FPGA_D[16] AV32

FPGA_D[17] AJ33

FPGA_D[18] AH33

FPGA_D[19] AL33

FPGA_D[20] AK33

FPGA_D[21] AK32

FPGA_D[22] AJ32

FPGA_D[23] AH31

FPGA_D[24] AG31

FPGA_D[25] AF31

FPGA_D[26] AE31

FPGA_D[27] AJ30

FPGA_D[28] AH30

FPGA_D[29] AR30

FPGA_D[30] AP30

FPGA_D[31] AU30

CPLD_FPGA_IO0 AT30

CPLD_FPGA_IO1 AN30

CPLD-GC_FPGA AN29

CPLD_FPGA_IO2 AW29

FPGA-GC_CPLD AV29

CPLD_FPGA_IO3 AU29

CvPCIe_CONFDONE AT29

MSEL_0 AA9

MSEL_1 AA10

MSEL_2 AD8

MSEL_3 AG8

MSEL_4 AH7

Table (13): CPLD & FLASH FPGA Pin Assignment



37

◙ 2.13) GPS

External clock synchronization is provided through the X1 connector and supported through the FPGA

signals illustrated by table (14)


IRIG_TRIG_OUT_F AW8

IRIG_ADC_CS_N_F AV8

IRIG_ADC_SDO_F AW7

IRIG_ADC_SCLK_F AV7

IRIG_COMP_OUT_F AU8

Table (20): GPS FPGA Pin Assignment

Technical Support:

Technical support can be provided by contacting [email protected] Support requests are

responded in less than 24 hours.

Sales Support:

Sales support can be provided by contacting [email protected] or +1 408 781-7778 (8:00 AM –

6:00 PM Pacific Standard Time)

mailto:[email protected]

mailto:[email protected]

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