Tomasz HemperekHybrid or Monolithic ? Pixel detectors for future LHC experimentsPH-ESE electronics seminar, CERN 17th December 20131The Bonn Team2Design Team:Hans KruegerTomasz HemperekTetsuichi KishishitaMiroslav HavranekYunan FuPiotr RymaszwskiXiaochao FangMarcus GronewaldOur main projects:Thanks to our close collaborators!

Overview3Current status and futere of Hybrid Pixel Sensors Current status and futuer of Monolitic Pixle Sensors Conclusions

Moore's law in HEP4

NameD-OMEGA IonLHC1FE-I3FE-I4FE-I5Year1991~1996~2005~2011???Technology Node3 m10.25 m0.13 m65 nm??Chip size8.3x6.6 mm28x6.35 mm210.8x7.6 mm210.2x19 mm2???Pixel size75x500 m250x500 m250x400 m250x250 m225x100 m2 ??Pixel array16x6316x12718x16080x336???Transistor count???800k3.5M80M???Price/Scaling5Technology node130nm65nm40nm6T SRAM cell (um2)2.40.520.24bit size in memory (um2)~ 3.2~ 0.7~ 0.3210bit words in 100x100um~ 310~ 1430~ 3120NRI* (um2)$2000-$3000$6000-$7000$8000-$9000* based on MPW prices for bigger (>25um2) designsHybrid Pixel Detectors

-fine pitch flip-chip assembly of:CMOS r/o chips (CSA + DSP per pixel)Si (planar or 3D) or Diamond detectors- high density electronics- moderate - good SNR- high material budget- expensive assemblyParametersATLAS Pixel Module (FE-I3)

6Current state of art implementations - FE-I4 7

Analog ChannelOverviewCurrent state of art implementations - Medipix 38

Other hybrids in 130nm:Timpix 3VeloPixDosePixHybrid Pixels Future9

125 mmFE-X5 CMOS 130 nm 3D?FE-X5 CMOS 65 nm3D Integration10

3D Integration11

FE-I4-P14x3mm sizeIBM 0.13m LVT 8LMFE-C4-P14x3mm sizeCHRT 0.13m LP 8LMFE-C4-P24x3mm sizeCHRT 0.13m LP 8LMFE-C4-P32.5x2.5mm sizeCHRT 0.13m LP 8LM61x14 array61x14 array30x10 arrayCPPM, UniBonn, LBNL

4 years later ........ 65 nm prototypes designed in Bonn12Our goal: design Data handling Processor (DHP) chip for Bell2 explore potential of 65 nm technologyDesign of test-chips to study analog performance of 65 nm technologyAnalog FE-prototypes: FE-T65-0, FE-T65-1 Other prototypes: SAR-ADC, PLL, LVDS, SEU tests

FE-T65-1 DHPT0.1 (subm.10/2011)DHPT0.2 (subm. 03/2012)FE-T65-0 Chip size: 1.961.96 mm2 SAR-ADCFE-T65-1 single pixel13180 m25 mAnalog part : - CSA tunable input capacitance - programmable charge injection - FDAC tunable feedback current - TDAC tunable threshold - comparator Digital part (custom and big std. cells): - identical for every pixel - configuration register 15-bits - 8-bit shift register-counter - mask-bit - HitOr

Analog - 50 mCharge sensitive amplifier with continuous reset14Version with continuous comparatorVersion with dynamic comparator

Charge sensitive amplifier with switched reset15LHC Mode (40 MHz)

Slow mode (6.25 MHz)Properties of switched CSA: - no ballistic deficit - higher gain - fast reset - requires synchronous operationVersion with continuous comparatorVersion with dynamic comparatorFE with switched CSA

2ke 12ke; step 2ke

Continuous vs dynamic comparator16Differential stage CS StageDifferential stage LatchContinuous comparatorPopular 2 stage architectureAsynchronous operationConsumes power even idle stateDynamic comparatorBased on latch in metastable stateDoes not consume power in idle stateActive only when CLK edge comesPower proportional to CLK frequency

Noise continuous CSA 17

Continuous CSA + continuous comparator

Continuous CSA + dynamic comparatorNoise switched CSA, comparison of all versions18Switched CSA + continuous comparator Switched CSA + dynamic comparator

CSAComparator [e-]P [W]ContinuousContinuous 14410.4ContinuousDynamic18310.6SwitchedContinuous11314.6SwitchedDynamic15714.8

Cin = 75 mF, 40 MHzFE-I4 vs FE-T65-1 (analog part)19FE-I4FE-T65-1Technology130 nm65 nmDimensions of analog part156 50 m259 25 m2 Charge sensitive amplifier2 stages1 stageComparatorcontinuouscontinuous /dynamicAnalog power consumption12.6 + 5.4 + 3.9 = 21.9 W / pixel6.8 + 3.8 = 10.6 W (18 W) / pixelAnalog power density1.75 mW / mm22.36 mW / mm2 (4 mW / mm2)65 nm what we have learned: - shrinking pixel size down to 125 25 m2 is possible - dynamic comparator saves power but has larger threshold dispersion - ENC is comparable with FE-I4 - power density has to be optimized SAR ADC IN 65nm - Layout

40 um70umLayout is not area optimalPossible de-cup under DAC?DAC

Only external sample signal needed!20SAR ADC21

DACDAC LayoutControlMain Control LogicAsynchronous ADC Measurements @ 10MS/s22Single Ended ModeDifferential ModePower consumption: ~40uW @1.2VWorks up to 12.5 MS/sDynamic Range: 0.8V

22Some possibilities in 65nm (for imaging applications)23SRAM 3072x40 bits 368x231um ADCADCADCADC200 um200 um100 um100 umSRAM 384x40 bits 100x198um ADCADCADCADCFast full frame storageIn pixel histogramingPreemphasis24

Preemphasis OffPreemphasis OnDHPT 0.1 - High Speed Link in 65nm25

20m of Infiniband cable @1.6Gbps of random data

65nm in Bonn26Test chips for custom IP verificationTwo mini@sic submissions in 2011 and 20121.6GHz PLLGigabit link driverLVDS transmitter & receiverPixel matrices with analog front-ends (CSA + comp.)In pixel ADCs

DHPT 1.0, first production version MPW submission in Aug. 201312 mm2 area, C4 bumps (SAC 305), 200m pitch

>300k Gates, >3MB SRAM PLL, 1.6Gb/s serial link, CML preamhasisReferenceLVDS and HSTL IODACs, ADC ...

DHPT 0.1 and DHPT 0.2 test chips

3 mm4 mmData handling processor DHPT 1.065nm conclusions27Possible great improvement in functionality on smaller areaGood analog performanceGood radiation tolerance*Higher submission costMore digital chip Technology available on MPW with bumps/full wafers

BUT what about sensor?

Traditional MAPS28

- Better resolution (small pixels)- Low(er) power- Can be only NMOS in pixel- Slow

ParametersState of the art MIMOSA-2629

30

Now Future ?more volume higher SNR

collection by drift faster charge collection less trapping

lower cost (no hybridization)

Charge Collection in Depletion Layer31Options for n-on-p Read-out32p-substrateDeep n-wellP+p-wellCharge signalElectronics (NMOS only)P+p-substraten+p-wellCharge signalElectronics (NMOS only)n+CCPD (HVCMOS)DMAPS-AMAPS likeCMOS with additional implantsCMOS with twin or triple wellsp-substrateDeep n-wellP+ p-wellCharge signalElectronics (full CMOS)P+nwp-substraten+ p-wellCharge signalElectronics (full CMOS)n+nwdeep p-wellElectronics inside charge collection wellCollection node with large fill factor rad. hardLarge sensor capacitance (DNW/PW junction!) x-talk, noise & speed (power) penaltiesFull CMOS with isolation between NW and DNW Electronics outside charge collection wellVery small sensor capacitance low powerPotentially less rad. hard (longer drift lengths)Full CMOS with additional deep-p implantMonolithic Pixel Sensors on HV-CMOS process33

ParametersDepletion (small)Low leakagePossible high resolutionLimited use of PMOS

I. PericCCPD + FE-I4 (HV2FEI4)34

An active sensor!3T MAPS on standard CMOS process35

ParametersA. MekkaouiDepletion (small)Low leakagePossible high resolutionFull CMOSHigh capacitanceLow breakdown

Monolithic technology requirements for LHC36High-resistive substrate (>1kOhm-cm)Isolated PMOS and NMOS transistors (deep n-well/p-well)Good breakdown performanceThinning Backside implantation and implant activation Backside metallization (if needed)Simple device cross-sectionHigh signal (full depletion possible) Fast (collection by drift)Small pixels

Only NMOS in active areaInput capacitnce dominated by deep-nwell tp pwell capacitancePros Cons37

37Electrostatic Potential (HV)

38Charge Collections39

Electron Density @ 200V (no radiation)Current on collecting electrode @200VCharge Collections Efficiency40Fluence (Neq/cm2)Back Voltage [V]CCE [%]0100/2001001e14100961e14200971e15100751e1520080

ESPROS Photonic CMOS Process41

There is more to this in this technology EPCB01 - overview

DMAPS pixelsDeep N-well pixelsTransistor array for parameter extractionChip size: 1.41.4 mm2First 50um, back side processed, full CMOS, fully depleted(>2kOhm-cm substrate).EPCB01 - Functional Blocks43Deep N-well pixels3T readoutAnalog Output

DMAPS pixelsPixel Charge Sensitive Amplifier (CSA)continuous dischargeresetPixel ComparatorasynchronousdynamicTuning DACDigital Sift Register Readout

Custom Pads

TransistorsEPCB01 - Test system44

MIOGPACDUT

EPCB01FPGA Multi-IO (MIO) boardGeneral Purpose Analog Card - universality can be used for other DUTs - provides bias voltages and currents for DUT - provides power supply for the DUT - distributes digital signals from MIO to DUTBoard carrying DUTEPCB01EPCB01 - Pixel Array Readout45

CSA- switched reset dynamic comparatorCSA continuous discharge asynchronous comparatorEPCB01 - Pixel Array46Pixel size: 4040 m2Sensing area: 2020 m2

PIXELSENSORRESISTORCSAQ-INJ.HIT ORTDACCOMPCDS

EPCB01 - Pixel Array Bias Configurations47

AC coupled resistor biasAC coupled self biasDC coupled

EPCB0148

EPCB01 more measurements49

Pegasus50

Parameters:180nm CMOS (TowerJazz)Different wafer materials18m HR epi 40m HR epi HR bulk50 x 50 m2 and 25 x 25m2 pixelsthanks to W. Dulinski, M. Kachel (IPHC)

50Pegasus - Electrostatic Potential (TCAD example)51

PEGASUS - First signs of life52

Fe55 Spectra for 18m epiSr90 and Fe55 Spectra for 18m epiM. Kachel (IPHC)FD-SOI53

ParametersAlmost perfect technology but due to back gate effect not radiation hard.

53HV-SOI54

LayoutFirst signs of lifeConcept

More to come55 150nm submitted Q4 2012 full CMOS n-type > 2kOhm-cm substrate thinned back implanted180nm submitted Q1 2013 full CMOS p-type > 1kOhm-cm substrate full wafers -> thinning/back implanting possible180nm - submitted Q1 2013 full CMOS p-type - initially 100 Ohm-cm very HV isolation guaranteed130nm submission Q4 2013 HV-CMOS(CCPD)/full CMOS p-type >3kOhm-cm full wafers -> thinning/back implanting possible150nm - submission Q1 2014 HV-CMOS(CCPD)/full CMOS/ possibly T3 p-type >2kOhm-cm (~4-5k Ohm-cm) thinned back implanted full wafersPossible scenarios for Monolithic Sensors56Hybrid Pixels with smart diodes:HR- or HV-CMOS as a sensor (8)Standard FE chipCCPD (HVCMOS) on FE-I4

CMOS Active Sensor + Digital R/O chipHR- or HV-CMOS sensor + CSA (+Discriminator)Dedicated digital only FE chip

Monolithic Active Pixel SensorMAPS usually on epi substrate diffusion signal, not suited for HL-LHC

HR- material (charge collection by drift) Fully depleted MAPS (DMAPS)

Diode + full analog processingDigital only FE chipWafer to waferbondingDiode + preampFE chipDiode + Amp + DigitalConclusions57Hybrid Pixel Detectors:- minitaruzation 65nm and below- smaller pixel- smarter pixels- more digital chips- 3D, diamond or active CMOS sesors for ultra high radiation

Depleted Monolitic Detectors:- more radiation tolerance- will take space of hybrids/strips for less dymanding application- as a accitve sensor layer for ultra fast enviroments

58 Thank you!Question, comments, suggestions:hemperek@uni-bonn.dePreamp

Amp2

feedbox

Cf2

feedbox

Cc

Inj0

Inj1

injectIn

Cinj1

Cinj2

+

local feedback tune

FDAC4 Bit

NotKill

Vfb

Cf1

+

local thresholdtune

TDAC5 Bit

Vfb2

+

-

Vth

HitOut

SENSOR

TIER 1 (analog)

TIER 2(digital)

copper connection

TSV

wire bond interface

bump bond interface