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Practical Problems in VLSI Physical Design ILP Floorplanning (1/22) Fixed modules only, no rotation allowed m 1 (4,5), m 2 (3,7), m 3 (6,4), m 4 (7,7) I. Floorplanning with Fixed Modules
Practical Problems in VLSI Physical Design ILP Floorplanning (1/22)
Fixed modules only, no rotation allowedm1 (4,5), m2 (3,7), m3 (6,4), m4 (7,7)
I. Floorplanning with Fixed Modules
Practical Problems in VLSI Physical Design ILP Floorplanning (2/22)
ILP Formulation
Practical Problems in VLSI Physical Design ILP Floorplanning (3/22)
Non-Overlapping Constraints (cont)
Practical Problems in VLSI Physical Design ILP Floorplanning (4/22)
Additional Constraints
Practical Problems in VLSI Physical Design ILP Floorplanning (5/22)
SolutionsUsing GLPK we get the following solutions:
Practical Problems in VLSI Physical Design ILP Floorplanning (6/22)
Final FloorplanWhy the non-optimality?
Due to linear approximation of area objective (= y*)Chip width/height constraints also affectedIn fact, our ILP solution (y* = 12) is optimal under these conditions.
Practical Problems in VLSI Physical Design ILP Floorplanning (7/22)
II. Floorplanning with RotationFixed modules, rotation allowed
Fixed modules: m1 (4,5), m2 (3,7), m3 (6,4), m4 (7,7)Need 4 more binary variables for rotation: z1, z2, z3, z4
We use M = max{W,H} = 23
Practical Problems in VLSI Physical Design ILP Floorplanning (8/22)
ILP Formulation
Practical Problems in VLSI Physical Design ILP Floorplanning (9/22)
Non-Overlapping Constraints (cont)
Practical Problems in VLSI Physical Design ILP Floorplanning (10/22)
Non-Overlapping Constraints (cont)
Practical Problems in VLSI Physical Design ILP Floorplanning (11/22)
Additional Constraints
Practical Problems in VLSI Physical Design ILP Floorplanning (12/22)
SolutionsUsing GLPK we get the following solutions:
Practical Problems in VLSI Physical Design ILP Floorplanning (13/22)
III. Floorplanning with Flexible Modules2 Fixed modules:
m1 (4,5), m2 (3,7) (rotation allowed)
2 Flexible modules: m3: area = 24, aspect ratio [0.5, 2]m4: area = 49, aspect ratio [0.3, 2.5]
Practical Problems in VLSI Physical Design ILP Floorplanning (14/22)
Linear Approximation
Practical Problems in VLSI Physical Design ILP Floorplanning (15/22)
Linear Approximation (cont)
Practical Problems in VLSI Physical Design ILP Floorplanning (16/22)
Upper Bound of Chip Dimension
Practical Problems in VLSI Physical Design ILP Floorplanning (17/22)
Non-Overlap Constraint
Practical Problems in VLSI Physical Design ILP Floorplanning (18/22)
Non-Overlap Constraint (cont)
Practical Problems in VLSI Physical Design ILP Floorplanning (19/22)
More Constraints
Practical Problems in VLSI Physical Design ILP Floorplanning (20/22)
Solutions
Practical Problems in VLSI Physical Design ILP Floorplanning (21/22)
ComparisonFixed modules only = 12 × 12Rotation allowed = 11 × 11Flexible modules used = 10.46 × 10.32
Practical Problems in VLSI Physical Design ILP Floorplanning (22/22)
Approximation Error and OverlapDue to linear approximation
Approximated area of m3 = 3.46 × 5.2 = 17.99 (actually 24)Approximated area of m4 = 3.83 × 7.32 = 28.04 (actually 49)Real area of m3 = 3.46 × 6.94 = 24Real area of m4 = 3.83 × 12.79 = 49Floorplan area increases, overlap occurs
