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correct read ouill not require

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114

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115

enables costs to be reduced; since it has no bias circuit. The parasitic capacitance is utilized as the charging load at the drain of N3 transistor. To decrease the charged voltage, the threshold voltage of the two inverter composed of NMOS transistors N4, N5 and PMOS transistors P2, P3 have been added. This will result a shorter charging time of BL and makes the lower read power dissipation. Additionally, the newly designed voltage type SA is capable of resisting the degeneration features of the floating gate transistor by using a voltage sensing method rather than a current sensing method. The transient current and charges for charging in one read process are described respectively:

( ) = β(V −V − V ) , (5)

β(V −V − V ) dt = C (V −V ), (6)

where VBLT is the transient voltage of the BL,CN3 is the parasitic capacitance at the drain of N3 , and T is the charging time = /(2 ).

Using equation (5) and (6), the average charging time and current can be obtained during one read period.

Results and discussion

The 27oC operating condition for the modified voltage-type sense amplifier and the conventional sense amplifiers have been designed and simulated in CEDEC 0.18-μm CMOS process. Simulations is executed to evaluate the circuit performance of the modified sense amplifiers with the previously reported voltage-type SA [12]. The transistors involved in the sensing circuitry were of equal size W/L= 0.18μ/0.18μ. The significant design factors are C1=0.1pF, SG=3V and CG=1.5V.

By using the critical design parameters listed in above table the output data (Vout) for the modified SA is shown in Fig. 3 under 2.6V power supply voltage. As shown in Fig. 4, the modified voltage type SA reads ‘0’ data at the beginning. At 0.4μS the SA reads ‘1’. The circuit is also able to work >2.6V, but above this operating voltage, the circuit experience noises.

Fig. 3. Simulation results of voltage SA for a 2.6V power supply Furthermore, depending on the principle of the

memory cell, VCG in equation (1) is the best value for voltage sensing and a lower voltage can be set for VCG. Using equation (2) and regulating the threshold voltage of the inverter in Fig. 3, the modified voltage mode SA is

capable of operating at voltages as low as 1V. The Vout data for a 1V power supply voltage are shown in Fig. 4.

The simulation results in Fig. 4 shows that the voltage required by the voltage-type SA can be significantly reduced from 2.6V to 1V, where the voltage was controlled by CG. In order to show the correct behavior of the voltage-type SA, the power supply voltage is set to 1V and the capacitive load to 0.1 pF.

Fig. 4. Simulation results of the average current Icn, Vout and VBL The corresponding current consumption for the

modified voltage-type SA is also shown in Fig. 4. Here the average current consumption during the read period is only 43μA for the maximum clock speed of 20MHz. This feature is useful for some electronic systems focused on low voltage and low power such as RFID transponder.

Fig. 4 also presents a comparison results among the Vout data, the average current consumption during the read period, and the corresponding bit line voltage under 1V power supply voltage. The figure further proves that the SA is capable of operating at a voltage as low as 1V. The circuit is also able to work <1V, but in this operating voltage, the circuit experience noises.

Generally, the required working temperature range of the RFID tag is from −25°C to 85°C. As, the modified voltage-type SA circuit is able to work within the temperature range from −25°C to 125°C. Therefore, this modified circuit has no power differentiation in working temperature of RFID tag.

A comparisons study of voltage-type sense amplifiers between this work and Liu et. al with minimum and maximum voltage level is shown in Table 1. From the study, it is shown that the circuit is able to work within 1V to 2.6V power supply voltages, which is lower than the Liu et. al.

Table 1. Comparison study of voltage-type sa between liu et. al. and this work

Research Vdd (Min)

Vdd (Max)

CMOS Technology

Liu et. al. 1.4V 3.3V 0.35 μm This Work 1V 2.6V 0.18 μm

The modified low voltage-type SA circuit layout is

designed in CEDEC 0.18-μm CMOS process. In Fig. 5, the completed chip layout of the modified low voltage SA is presented. In this layout, the capacitor connected with the control gate transistor is about 0.1pF. This small capacitor

otsts

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Conclusions

An improvoltage SA cpresented in tdesigned by uEEPROM prconduction btransistors is uthe floating gresults, it has working over supply. The retype SA requvoltage-type Ssimulation resfrom the pow

L. F. Rahman, MElectrical Engine

Sense AmplifCMOS process todata. Memory accexperience the lavoltage-type SA iemperature range

voltage-type SA i

L. F. Rahman, Melektrotechnika.

Šuntinis stiprsiekiant sumažintinformacijos išrin

galios, kurios yra esant labai mažaiinkamas mažos įt

mall area of tp. In this resecell of the MOfied SA circuby Liu et. al.

t design of the l

oved design acircuit using this research. using the CEDocess. In th

between the used to sensegate transisto

been provena voltage ra

esults also veuired lower reSA designed sults confirm twer delineatio

M. B. I. Reaz, M.eering. – Kaunasfier is one of the

o achieve both thecess time, power

arger current or pis able to executee from -250C to s appropriate for

M. B. I. Reaz, – Kaunas: Tech

rintuvas (ŠA) yrai skaitymo galią

nkimo trukmė, galnetinkamos žem

i įtampai – nuo 1tampos aplikacijo

the circuit to earch, W/L =

OS transistors, uit size is low

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and a comparaa voltage seThe modified

DEC 0.18-μm his research,

drain and e the stored vors. Accordingn that, the cirange from 1Verify that the eading curren

by Liu et. that this low on caused by

. A. M. Ali, M. Ms: Technologija,

e major circuits ine lower reading pr dissipation and power dissipatione under a very lo1250C. The comlow-voltage appl

M. A. M. Ali, hnologija, 2012. –a viena iš pagrindir padidinti jutimlios suvartojimas os įtampos RFID1 V iki 2,6 V. ŠAoms kaip RFID E

reduce the co0.18μ/0.18μ iwhich also pr

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pe SA

ative study ofensing method circuit has CMOS embethe bidirectsource of M

voltage (‘0’/‘1g to the resercuit is capabV to 2.6V pmodified vol

nt/ power thanal. Moreovervoltage SA isy the temper

Marufuzzaman.2012. – No. 4(12

n CMOS nonvolapower and superithe reliability of

n problems, whicow power supply

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man. Šuntinio sP. 113–116. minties grandžių. tikimumą. RFID ikimumas labai paikomosioms sistrtas temperatūrų ibl. 10, lent. 1 (an

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Yasin F. M., KIdentification: Microwave Jou56–70. Liu D. S., ZoMemory Achievmemory for RMagazine. – IEEDaga J. M., PaG., GuichaouaEEPROMs embDesign & Test o68–75. Liu J., Wang XM. A low–volembedded flashIOPScience, 20Micheloni R., read path: buildof the IEEE. – IMing L. I., Kasense amplifieScience China I53(8). – P. 1676Liu D. S., Zou amplifier for University ScieHuang R, Zhodouble gate strumemory applicaSciences. – SpriXu F., He X. Q16 K bits embeInternational CSystems (ICCC1516–1520. Canet P., LaReliability in EProceedings of Symposium. – M

n of Sense Ampli6. The aim of this resensing operation

s vigorously influe for low voltagbetween 1V to 2

ried out to evalu 5, bibl. 10, tabl.

tiprintuvo įdieg

Tyrimo tikslas –transponderyje E

priklauso nuo ŠA emoms, išskaidymnuo -25 0C iki 1

nglų kalba; santra

ally, the circuansistors and c

Khaw M. K., REvolution of Trnal. – Horizon

ou X. C., Zhving Lower Pow

RFID tag IC /EE, 2006. – No

apaix C., Meraa J., Auvergnbedded in portaof Computers. –

X., Wang Q., Wltage sense amh memory // 10. – No. 31(10Crippa L., Sa

ding blocks andIEEE, 2003. – Nang J. F., Wanr for low–powInformation Sci6–1681. X. C., Yu Q., EEPROM memnce A., 2009. –ou F. L., Cai uctures for higations // Sciencinger, 2008. – N

Q., Zhang L. Kdded EEPROMonference on

CAS). – Chengd

alande F., RaEEPROM Nonv

the IEEE NonMarseille, Franc

Acc

ifier in 0.18-µm

esearch is to impn. In RFID transpuenced by the fee applications of2.6V VDD. The

uate the efficiency1 (in English; ab

gimas 0,18 µm C

0,18 µm CMOSEEPROM naudoja

savybių. Sroviniomo problemų. Pa

125 0C sričiai. Maukos anglų ir liet

uit size reducecapacitors.

Reaz M. B. I. RTransponder Cn House, 2006.

hang F. Embewer – New des// IEEE Circuio. 22(6). – P. 53andat M., Rechne D. Designtable systems o– IEEE, 2003. –

Wu D., Zhangmplifier for hiJournal of Se0). – P. 1–5. angalli M. Thd critical aspectNo. 91(4). – P. ng Y. Y. A no

ower nonvolaticiences. – Sprin

Zhang F. Newmory // Journ

– No. 10(2). – PY. M. Novel

gh density and ce China SerieNo. 51(6). – P.

Key design technM memory // Pr

Communicatiodu, Sichuan, C

azafindramoravolatile Memorn–volatile Memce, 2004. – P. 6

Rececepted after rev

CMOS Process

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bstracts in English

CMOS procese

S procese įdiegti ama duomenims o tipo ŠA sukelia

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tuvių k.).

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Radio FrequencCircuit Design

– No. 49(6). – P

edded EEPROMign of EEPROMits and Device

3–59. hard S., Meduln techniques foon chips // IEE– No. 20(1). – P

Z., Pan L., Liigh–performancmiconductors.

he flash memorts // Proceeding537–553. vel voltage–typile memoriesnger, 2010. – N

w design of sensnal of ZhejianP. 179–183.

vertical channlow power flass F: Informatio799–806. niques of a 40 nroceedings of thns, Circuits an

China, 2004. – P

a J. Integratery Cell Design

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