I3T Modeling flow : September-2011 Modeling flow and models improvement for I3T ON Semiconductor...

I3T Modeling flow : September-2011

Modeling flow and models improvement for I3T ON Semiconductor technologies

Petr Betak, Petr Zavrel, Lenka Sochova, Jan Plojhar

MOS-AK September 2011

I3T Modeling flow: September-2011

Overview• OVERVIEW: ON technologies• WHAT IS MODELING• GENERAL FLOW IN MODELING

Data For Modeling Purpose Built up model card as a subcircuit

• DEVICES (focus on I3T80 & I3T50) CMOS DMOS BIPOLARS DIODES RESISTORS CAPACITORS

• SPECIAL CASES, MODEL IMPROVEMENT


Overview: ON technologies

Bipolar : BIP14V, BIP18V, BIP30V, BIP50V, ON50 ...BCD : ONC25 (0.25um) , PS5, AIMAnalog CMOS: ACMOS, ONC110 (0.11um), ONC18 (0.18um), ONC25(0.25um)VHVIC (very high voltage) analog CMOSBCDMOS: I2T100 (0.7um) I3Txx: I3T25, I3T50, I3T80 (0.35um) C3, C5 (0.35um, 0.5um) Special: Low Vf Rectifiers, Integrated Power devices, HV FET, Microintegration ...


WHAT IS MODELING?

• DEVICE MODEL - set of mathematical relations between node voltages and terminal currents

• GOAL - accurately represent electrical behavior in circuit simulators• DEPENDEND ON DIFFERENT KIND OF PARAMETERS:

– technology parameters– geometry (layout) parameters– empirical (fitting) parameters

PWELL

N-epi

D G S B Nepi p-sub

N+

ENM (with Nepi terminal)

P+P+

Psinker

BLP

p-substrate

PWELL

N-epi

D G S B Nepi p-sub

N+


P+P+

Psinker

BLP

p-substrate

enm (d g s b) enm_model w=10 l=0.8model enm_model bsim3v3 type=n + vth0 = 0.582+ u0 = 290+ rdsw = 749.6872+ tox = 7.10e-9+ vsat = 5.55e4+ k1 = 0.55+ dvt0 = 10.7 + cj = 1.02e-3+ cjsw = 3.11e-10+ cjswg = enm_cjswg+ js = 3.5e-7+ jsw = 5e-13…….

…..

DEVICE EQUATIONS MODEL


GENERAL FLOW IN MODELING

Data for Modeling Purpose

DC :

• IV curves

• mismatch

• junction leakage, substrate leakage

• process variation

AC low frequency:

• junction capacitance

• low frequency noise

Building up the model card as a sub circuit

1/ Model extraction of the main device - ICCAP,UTMOST, Matlab,

Perl routines are used for optimization purpose

2/ Adding models of the parasitic component

3/ Building up corners (3 corners)

4/ Implementation of the SOA flags based on Reliability

inputs

5/ Implementation of the matching parameter into the

model

6/ Model of ESD cells

Testchip

•WL arrays

•Matching frames

•RF frames

Model Kit & test

Running basic and specific tests

at device level (simulate a netlist) and at circuit level

(simulation of schematic in

Design Environment)


Data For Modeling Purpose DC MEASUREMENT DATA measured on golden wafers of different lots:

IV curves, transformstemperature sweepsdifferent dimensions (W,L matrix)

CV MEASUREMENT DATA measured on golden wafers of different lots:

CV curves, junction capacitancesfrequency sweepsdifferent dimensions (W,L matrix)

S PARAMETERS DATA measured on golden wafers of different lots:

capacitance extraction high frequency verification

NOISE measurement, matching extraction ...


Built up model card as a subcircuit

STANDARD MODEL(BIPOLAR-VBIC,MOS -BSIM3V3..)

MACROMODEL= several standard model devices(DMOS –DMOS AMIS MACROMODEL..)

1/ Model extraction of the main device - ICCAP,UTMOST, Matlab, Perl routines are used for

optimization purpose

2/ Adding models of the parasitic component

3/ Building up process corners (3 corners)

4/ Implementation of the SOA flags based on Reliability

inputs

5/ Implementation of the matching parameter into the

model

6/ Model of ESD cells0 10 20 30 40 50

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

VDS (V)

VG

S (

V)

25 years10 years1 year1e6s1e5s1e4sForbidden region

Difference between identically designed analogue devices is modelled on the base of PELGROM FORMULA:

222

2 CSWL

A

0

0.00005

0.0001

0.00015

0.0002

0.00025

0.0003

0.00035

0.0004

0.00045

0 2 4 6 8 10 12

VGS (V)

ID (

A)

fast

typical

slow


I3T80 & I3T50 DEVICES

Short overview of model features & limitations per device groups:

• Low Voltage MOS• High Voltage MOS• Bipolar Transistors

• Diodes• Resistors

• Capacitors


Low Voltage MOSModel Features:•BSIM 3v3, BSIM4 model•SOA, Matching•DC (geom., temp., leakage) • AC (CV + 1/f noise)•Multi-fab / process corners•Verified till 200C

Model Limitations:•Moderate/weak inversion inaccuracy•Incapable of RF modeling

Pocket Diode:•NEPI-to-PSUB (NLVD, NMVD)

PWELL

N-epi

D G S B Nepi p-sub

N+


P+P+

Psinker

BLP

p-substrate

PWELL

N-epi

D G S B Nepi p-sub

N+


P+P+

Psinker

BLP

p-substrate

DEVICE

MODEL

nmos Nepi strap

P-substrate

+

Gm/Id vs VgsW/L=20/20 VDS=0.5 VBS=0 TEMP=27C

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

0.01

0.11

0.21

0.31

0.41

0.51

0.61

0.71

0.81

0.91

1.01

1.11

Vgs (V)

Gm

/Id

(1/

V)

Gm/Id_meas

Gm/Id_sim


VNDMOS

PwellPdrift

B || S G D

NW

BLNp-substrate

N+ plug

BLP

P+sinker

P+ N+N+

P+N+ guard ring

N-epi

N+ P+

channel region

driftregion

High Voltage MOSModel Features•JFET(J1) for drift region (model IDSAT & Ron)•Standard BSIM3v3 dominant MOS (M1) model channel part (VTH & BETA)•AC behaviour modelled by dominant MOS & added shorted MOSFETs (M2 & M3)•Parasitic diode integrated in subcircuit•Formula for BLN res.•SOA, Matching•Verified till 200C•1/f noise

•Limitations•No parasitic BJT •No self-heating•AC modelled at 100kHz

Pocket diode•NEPI/BLN-to-PSUB

DEVICE

MODELGate

SourceDrain

Bulk

Substrate

M1 M2

D1D3

J1

M3

D2

Nepi

+


MOS & DMOS• DC MODELING

– IDVG over temp. and over size– VTH, short & narrow channel effect– Body effect– IDVD over temp. and over size– IDSAT & RON over size

lfpdm80 output curves

Ron

IDSAT

NMOS short channel effect


MOS & DMOS

• Vth & Beta Matching • AC– Cgs,

Cgd over size

for different

VG & VD

2

22

T

T

VV

T CWL

AV

%8.95

0

.1729.9

2

R

mVC

mmVA

T

T

V

V

• 1/f noise

INTRINSIC MOSFETACCUMULATION

MOSFET


Model Features:•VBIC (NPN) model & BJT (PNP)•Vertical devices•Checked till 200C DC

Gummel Poon (+ Beta vs. Ic)Output characteristics (+ Early Voltage)Validated on band-gaps (∆VBE tuned)Base-emitor breakdown and parasitic PNP (for NPN)

ACdiffusion and depletion capacitances

Pfield

N-epi

BLN

p-substrate

Psinker

BLP

E B C p-sub

Nplug

N+

P+P+

N+ guard ring

BLN

P+

SIPROT

Pfield

N-epi

BLN

p-substrate

Psinker

BLP

E B C p-sub

Nplug

N+

P+P+

N+ guard ring

BLN

P+

SIPROT

Bipolar Transistors

,,

s

s

E

E

I

I

I

I

•Matching

Model Limitations•No S-param validation•No 1/f noise


Diodes / JunctionsModel Features:•DC

- forward

- Breakdown & leakage

- done for -30C till 200C

•AC (capacity modelled)

•SOA

•Based on diode, dio500 standard models

Model Limitations:•Transit-time model=charged based model, not accurate enough

•Parasitic bipolar not modelled

•Snap-back not modelled for ESD diodes

FORWARD BREAKDOWN & LEAKAGE

CAPACITANCE


Resistors

))(*)(*1(**2

*2* 2

21 nomcnomc TTTTTTEtchW

EtchLLRshR

sheet res.

temperature dep.correction

Model Features:•POLY ,Diff. Resistors ,METAL RESISTORS

•matching based on Pelgrom formula for resistance std. deviation

•based on phy_res, resistor, bsource standard models

•verified form -40C till 200C

Model Limitations:•TC not modelled over corners & over size

•TC based on typical silicon, only PPOR statistically verified


CapacitorsModel features:•MIM capacitor, metal to metal cap., horizontal bar & plate cap.•Voltage linearity and temperature dependency model (TC)•Scalable according the bar, width & length •Verified till 125C•SOA implemented

Model limitations:•no matching in the models•minimum dimension of device at least 10um•resistance & self inductance not included

MIMC


Special cases, model improvement

Model conversion into different simulator languageSPECTRE, ELDO, HSPICE:-> HSPICE model of the physical resistor

Modeling of the substrate current and recovery charge:JUNCTION DIODES:-> Enhanced NQS Lauritzen diode model

N-epiN-epi

T1 T2

P+N+

P+

P+N+

P-substrate

NWARSBNWRSB

N-epi

T1 T2

BLP

N-epiN-epi

T1 T2

P+N+

P+

P+N+

P-substrate

NWARSBNWRSB

N-epi

T1 T2

BLP


HSPICE model of the physical resistor

Circuit connection of the model elements in HSPICE for SPECTRE

“subtype=p”

Circuit connection of the model elements in HSPICE for SPECTRE “subtype=n”

Circuit connection of the model elements in HSPICE for SPECTRE

“subtype=poly”

N-epiN-epi

T1 T2

P+N+

P+

P+N+

P-substrate

NWARSBNWRSB

N-epi

T1 T2

BLP

N-epiN-epi

T1 T2

P+N+

P+

P+N+

P-substrate

NWARSBNWRSB

N-epi

T1 T2

BLP

21 CCCSPECTRE


HSPICE model of the physical resistor

Discrepancy between SPECTRE and HSPICE results

-0,0005

0

0,0005

0,001

0,0015

0,002

0,0025

0,003

0,0035

0,004

0,0045

0 0,5 1 1,5 2 2,5 3 3,5

Voltage (V)

Dis

crep

ancy

(%

)

L=10um

L=100um

L=1000um

Example of the Physical resistor conversion

Comparison of the SPECTRE and HSPICE results


ENHANCED NQS LAURITZEN DIODE MODEL

PARA DIODE (POCKET DIODE):•NQS diode verilog model for KPsub diode•current source model lAPsub=f(IPsub)•breakdown diode (SPICE)

MAIN DIODE: •NQS diode verilog model for AK diode (dioAREAmain and dioPERImain)•substrate current source model IPsub=f(IA)•breakdown diode (SPICE)


tau,tt

Comparison of current in time during recovery for measured diode (ia.m - blue) and NQS Lauritzen updated model (ia.s - cyan)

Extraction of diffusion capacityThe indirect approach of tuning and measuring reverse recovery effect consists in measuring S-parameters and extraction of a diffusion capacitance of forward biased diode in the area of threshold voltage region (OFF state to ON state) with the voltage step of 5 mV [3].

NQS updated Lauritzen model (blue) vs. measured (extracted) diffusion capacity (cyan)


Reverse recovery effect modeling


The current source IPsub:• model of the substrate current dependent on current flowing through the MAIN DIODE(IA)•expressed by (1), where m=1.606 and n= -5e-3 are variables to tune the current behavior, determined based on measurement data

Current source model

0,0E+00

2,0E-04

4,0E-04

6,0E-04

8,0E-04

1,0E-03

1,2E-03

1,4E-03

1,6E-03

1,8E-03

0,0E+00 5,0E-03 1,0E-02 1,5E-02 2,0E-02 2,5E-02

IPsu

b [A

]

IA [A]

IPsub vs. IA w=50um & T=30C

ISUB_w50_w12 ISUB_w50_w11_simIPsub_measured data IPsub_model data

•The proposed macro-model of diode enhances the standard diode model by adding Lauritzen NQS model of reverse recovery effect and the model of the diode cathode-to-substrate junction.• The updated macro-model of the diode visibly improves reverse recovery effect simulation results.•The proposed model of substrate current also fits well the measured data as well as reverse current from measured at the substrate node.• What is also positive point, the updated NQS model of investigated diode do not leads to convergence problem and do not increase simulation time.

IAnIAIPsub m


Conclusion

The current added by PARA DIODE to MAIN DIODE IAsub=g(IPsub) is lower level of magnitude, ca. 0.1% of MAIN DIODE IA stream ad is of same model where n= -66e-6 & m=5.163

(1)


REFERENCES[1] P.O Lauritzen, C.L. Ma, “A Simple Diode Model with Reverse Recovery”,

IEEE Transaction on Power Electronics, Volume 6, Issue 2, April 1991, pp. 188-191

[2] Sauter Martin, “Reverse Recovery Effects in SPT5 Diodes”, Infineon Technologies papers, IC-CAP Modeling Handbook, internet source: http://edocs.soco.agilent.com/pages/viewpage.action?pageId=105321342

[3] Sischka Franz, “IC-CAP Learning Week”, Agilent Technologies, EEsoft EDA Europe, May 2010

[4] A.Vladimirescu, The Spice Book New Yorl, 1994, John Wiley & Sons, Inc[5] Cadence Circuit Components and Device Models Manual Product Version

6.1, December 2006, CADENCE [6] HSPICE Reference Manual: Elements and Device Models Version C-2009-

09, September 2009,. SYNOPSYS[7] ELDO Users’s Manual Software version 6.10_2 Release AMS 2007.2a,

2007,. MENTOR GRAPHICS CORP.[8] Stanislav Banas, et al. “Enhanced NQS Lauritzen Diode Model”, MIXDES,

2011, Proceedings of the 18th International Conference, pp. 82-84

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I3T Modeling flow : September-2011 Modeling flow and models improvement for I3T ON Semiconductor...

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