P. J. TimansJTG Meeting, 2 February 2011

IEDM 2010 Short Course15nm CMOS

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Short Course Contents

• Course Organized by Kelin Kuhn, Intel• Presenters

– CMOS Technologies – Trends, Scaling and Issues (Thomas Skotnicki, ST)

– 15nm Device Challenges and Solutions (Mukesh Khare, IBM)– Lithography for the 15nm Technology Node (Sam Sivakumar,

Intel)– BEOL Technology toward the 15nm Technology Node

(Yoshihiro Hayashi, Renesas)– Device/Circuit Interactions at the 15nm Technology Node (Clive

Bittlestone, TI)

• Here we’ll focus on the 1st two tutorials

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Metrics for Success in Scaling

• Switching performance dominated by dynamic characteristics: Ieff metric, which depends on DIBL

• DIBL metric is especially relevant to low power applications

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Bulk Scaling Limit

• Limited scope for scaling planar device• Improvement possible through μ boost

– BUT - much of the feasible boost has already been used up

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III-V Channel: Hard to Scale & Keep Performance

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Fully-Depleted Devices Improve DIBL

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Performance Comparisons

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T. Skotnicki: Advocating Planar FDSOI

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M. Khare: Illustration of 15nm CMOS

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Scaling Challenges

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Gate Dielectric Scaling Has to Continue

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Junction Depths Have to Scale Too

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Underlap Optimization

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Vt Variability can be Improved

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Band-to-Band Tunnelling Issue for Low Power

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Pitch-Scaling: Loss of Strain

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SOI Progressing to Fully-Depleted Mode

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Finfets / Trigates: Parasitics Challenges

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Effort Continues to Reduce EOT

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Interface Layer Scaling

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M. Khare (IBM) - Conclusions