KEYNOTE ADDRESS

NON-VOLATILE MEMORY TECHNOLOGY - TODAYAND TOMORROWChih-Yuan Lu, Tao-Cheng Lu, and Rich Liu

Macronix International Co., Inc., 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan, R.O.C.

INTRODUCTION higher rate. Therefore, the tunnel oxide must be thick enoughWith the ubiquitous presence of portable consumer and to prevent charge tunneling through disconnected defects,

communication devices in recent years comes the stellar the "percolation" mechanism [1,2], as shown in Fig. 2a andgrowth of non-volatile memory application. Like their 2b. Thus tunnel oxide with a thickness > 8 nm can stay leakbiological counterparts, smarter devices must have larger free because a single defect in the oxide is insufficient tobrains containing both sophisticated functions (code storage) provide a leakage path, but oxide < 8 nm thick is prone toand more memory capacity (data storage) that do not vanish defect assisted leakage.when power is turned off. These functions are so far wellserved by two types of Flash memories - the code storage C tthrough the fast and random access capability provided by Iatthe NOR architecture, and the data storage by the pageaccess architecture of NAND Flash. Combined, the NORand NAND Flash memory revenues have reached > $19FlaigGtbillion dollars in 2005, nearly 4000 of the total memory amarket, or 9% of the annual semiconductor market.uc

While the portable device requirement for code storagecapacity follows a trend roughly parallel to that for DRAM,the demand for data storage has seen an explosive growth inrecent years. This can be attributed to the rapid growth of (a) Floating gate Device (b) Nitride storage devicedigital still cameras (DSC) and camcorders, universalacceptance of USB, and new applications in MP3. Fig. 1 Floating gate device and nitride storage device.Consequently, NAND Flash has enjoyed a revenue growth of>600o in 2005 and with similar growth promises for the nextfew years.

Despite the rapid growth, both NOR and NAND Flashmemories face steep technology challenges when furtherscaling into sub-65nm nodes. These scaling issues as well assome potential solutions are addressed in the followingsections.

NON-VOLATILE MEMORIES TODAYFloating gate NOR Flash memory and its scaling limit

The floating gate device stores charges in a small flake (a) (b)of polysilicon floating gate that is isolated on all sides byinsulators, as shown in Fig. la. The thinnest insulator is the Fig. 2 Percolation model for defect-assisted tunneling. (a) Fortunnel oxide between the floating gate and the channel of the thin tunnel oxide a single defect in the oxide may induceMOSFET device. The charge in the floating gate creates a Frenkel-Poole tunneling if the defect is unfortunately located.built-in electric field that provides a driving force for the The red circle represents the characteristic length an electroncharge to tunnel out (or for the opposite charge to tunnel in). may tunnel. (b) For a thick oxide a single defect is insufficient toTypically, the number of stored electrons is < 1,000 and in cause tunneling. Even multiple defects cannot assist tunneling iforder to keep the memory state for 10 years even a loss of they are not within reach of one another.one electron per week is intolerable. If oxide can be madeperfect with no point defects at all, then a tunnel oxide of 4 As is well known, to scale the channel length of annm would be sufficient to stop the electrons from tunneling. MOSFET device the vertical dimensions (gate oxide andHowever, it is theoretically impossible to fabricate defect junctions) must be scaled at the same time; otherwise, shortfree oxides because at any temperature there is an channel effects would severely degrade the performance ofequilibrium amount of point defects. When there is a defect the device. For NOR Flash memory the programming of thein the tunnel oxide, electrons stored in the floating gate can device is by channel hot electron (CHE), which is producedtunnel out through the Frenkel-Poole mechanism at a much by the steep lateral electric field at the drain edge. This

1-4244-0206-9/06/$20.OO ©)2006 IEEE 18 Proceedings of 13th IPFA 2006, Singapore

requires an abrupt drain junction that is relatively deep and it Floating gate NAND Flash memory and its scaling limitis difficult to control the short channel effects. As shown in The floating gate device for a NAND Flash memoryFig. 3a, the design space (substrate doping and drain bias looks very similar to that for the NOR Flash but theduring programming) for a NOR Flash cell is limited by operation principle is different, which creates an entirelyperformance parameters defined by system requirements. An different set of constraints for scaling. The NAND Flashideal memory cell should have low leakage (drain turn-on memory abandons the random access feature and puts acurrent), fast read current, fast programming speed and low string of devices in series and uses a page mode operation -program disturb (band-to-band tunneling leakage). However, programming and erase are both done on a page basis. Byany improvement in performance decreases the cell design abandoning the random access feature, NAND Flash is ablespace. Furthermore, as technology scales down, the cell to use the slower Fowler-Nordheim (FN) tunnelingdesign space shrinks even without increasing the mechanism for programming. Although slower on aperformance, as shown in Fig. 3b. This is because the tunnel bit-by-bit scale because of the low FN current, the lowoxide and the abrupt junction remain unscalable - either the current also allows the parallel programming of a whole pageperformance or the design space must suffer. Consequently, simultaneously. Consequently, the programming speed forif performance specifications are not relaxed NOR Flash will NAND Flash is several times higher than that for NOR Flash,have no design space left at 45nm technology node. and is suitable for handling large quantities of data that do

6_________5________ not need to be read bit-by-bit.6.5 Because NAND Flash device does not need CHE for

6) IpIrDTO = 2,AIcell programming it does not require abrupt deep junctions. It can

tPGM =psec also tolerate more channel leakage because all devices on theC,) same bit line must be turned on during read operation. In

addition, the read current requirement for NAND Flash ismuch lower (- 1OX) compared to NOR Flash because of the

X5 | IBBT 022pAell | much higher series resistance in the NAND string.m) /Consequently, the design space for NAND cell is much

E 4.5 larger even when the same tunnel oxide limitation stillE applies.

4 - Besides, the packing density of NAND Flash devices0 IREAD 1|pAIcell is more than twice that for NOR. This is because the NAND

3.5 architecture does not require a contact within each cell,0 0.5 1 1.5 2 resulting in an 4F2 cell compared to - 10F2 for NOR Flash.

(a) Channel Pocket Doping (1018/cm3) However, the closely packed devices also increase the

6 vulnerability to noise caused by cross talk between90 m node area neighboring floating gates. In addition, when densely packeden \ there is no room left between devices to allow the

g5.5 65 node - blue area wrap-around of control gate over the floating gate that helpsIS \m/nmlode nlo designl increasing the control gate coupling ratio as well as

. n/itoow decreasing the floating gate cross talk. Consequently, the5 s 9, , floating gate coupling cross talk issue will limit the scaling

capability to - 40nm node [3]. Beyond that, nitride storage4.5 devices, which are immune to floating gate coupling, must

be used.E~~~~~

X | 90nm node Nitride storage devices and their scaling limitscm - g 45lnm nlode

2 654m node Unlike the floating gate, which is a conductor sealed3.5 ' by insulators, nitride storage device exploits the fact that

0.2 0.7 1.2 18C3 1.7 silicon nitride contains intrinsic defects that trap charges.(b) Channel / Pocket Doping (101cm ) The device, shown in Fig. lb, is simpler than the floating

Fig. 3 Design space analysis for floating gate NOR Flash. (a) For gate device. An immediate benefit of the nitride trappinga 90nm node device, the lines indicate minimum acceptable cell device is that the charge is stored in an insulator and thusperformance for programming speed, read current, cell leakage localized. It is not vulnerable to defects in the tunnel oxide(IDTO= drain turn on current), and program disturb (IBBT). Arrows and its scaling is thus not limited by the > 8 nm thick tunnelpoint to directions of higher performance. (b) Design space oxide constraint. In addition, because the stored charges arevanishes for 45nm node device. localized it is possible to store two bits of information in one

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MOSFET and thus double the density. This is easily accomplished by reading the device in bothThe earlier version of nitride storage device is SONOS directions. As depicted in Fig. 4 the Vt's of the left-bit and

(Si/SiO2/SiN/SiO2/Si). This device uses thin 2-3 nm tunnel the right-bit are easily distinguished even when the two bitsoxide since the trap levels in SiN is deep and do not de-trap occupy an overlapping space. When charges are present onreadily. With the thin tunnel oxide the SONOS device can be both left and right the Vt's are higher than when there is onlyprogrammed and erased by +FN and -FN operations. During charge on one side. Therefore, even after the charges mergethe -FN erase operation holes in the substrate are injected it is still possible to distinguish 4 logic states (2 bits) - nointo the SiN neutralizing the negative charge. However, with charge, charge on left-bit, charge on right-bit, charges onthin tunnel oxide (2-3 nm) the stored charge induces a both sides. If only two logic states (1 and 0) are used themoderate electric field that is sufficient to cause substrate nitride storage device can scale below 35nm because it is nothole direct tunneling. There is also evidence that electron limited by the tunnel oxide thickness. No detailed studiesmay tunnel from the nitride trap to the Si/SiO2 interface trap have been published at this time, however.[4]. Thus data retention is difficult to achieve both fromcharge loss and from direct hole tunneling. NON-VOLATILE MEMORIES FOR TOMORROW

Recently, NROM [5] attracted much attention because Nano-crystal device and its scaling limitof its simple structure and 2-bit per cell capability (Fig. 4). A nano-crystal device can be achieved by simplyThe programming is by channel hot electron like that for the breaking up the floating gate into many nano-crystals offloating gate NOR Flash. However, since charges trapped in polysilicon (or metal) in a floating gate device [9], as shownthe SiN are difficult to tunnel out, erase is by band-to-band in Fig. 5. Since charge is stored in discrete nano-dots oftunneling of hot hole from the drain edge. Although there conductors a weakness in the tunnel oxide can only causehave been concerns about the reliability issue caused by hot charge loss in the nano-crystal immediately above the defecthole damage [6], however, several companies have shipped and is thus no longer fatal as for a floating gate device.products indicating at least engineering solutions. Therefore nano-crystal devices promise to also break the

scaling constraints set by the tunnel oxide thickness. Anadditional benefit of nano-crystal device is the capability of

(a) l l -Istoring two bits of information, since like the nitride storagedevices charges are stored in discrete, non-conducting,storage media.

Program: CHE Erase: Band-to-bandtunneling hot hole, 000000BTBTHH

(11) (10) (00) (01)

(b) Fig. 5 Nano-crystal device replaces the floating gate withnano-size polysilicon bits. Charge is stored in discretenano-crystals and thus reduces leakage. Programming is by

LVt= 1V L/tVt = 4V- LVt=2V- t = 5V\L CHE and erase is by FN tunneling. It is capable of 2-bit/cell.RVt = 1V RVt = 2V RVt = 4V RVt = 5V

Fig. 4 (a) Program and erase mechanisms for 2-bit/cell The scaling limit of nano-crystal device has not beenNROM device. (b) Even when left-bit and right-bit merge 4 established. Uniform deposition or self-assembly oflogic levels are still clearly distinguished. nano-crystals is a necessary condition; otherwise the

statistical fluctuation of the number of nano-crystal devicesThe electron charge by CHE is typically - 20nm wide for sub-65nm node becomes unacceptable. More

[7], thus the trapped charges on the left side and right side of troublesome is the Coulomb blockade phenomenon in athe MOSFET would tend to merge when the device is - 40 quantum dot structure. When a nano-crystal (< 5 nm innm in length. However, detailed analysis [8] shows that even diameter) receives a charge its repulsive force to otherwith 2-bit per cell the device can be scaled to <35 nm, as electrons prevents them from entering the same nano-crystal.depicted in Fig. 4. Intuitively, when the left-bit and right-bit Since the total number of nano-crystals in a small device ischarges start to merge the "resolution" is lost. However, it is small (K 100) this limits the programming capability (A Vt)not important to distinguish the left-bit from the right-bit of the device. Therefore, the scaling limit for nano-crystalwhen both bits are present. It is only important to distinguish device depends on how small nano-crystals can be made asthe left-bit from the right-bit when only one bit is present. well as means to uniformly deposit them.

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to smaller blocks with isolation devices in between [12].Phase-change memory (PCRAM)

Phase change memory exploits the large resistancedifference between amorphous and crystalline phases of VthO Vthlchalcogenide glass. Chalcogenide glasses consists of binary 11 Aand ternary compounds of Ge, Sb, As, Te, such as GeSb,GeSbTe, or GeAsTe. A class of chalcogenides, such asGeSbTe, exhibits threshold switching - a semiconductor -breakdown that changes the resistivity drastically at a certainvoltage. This allows the passing of current required for thephase change through the material even when the resistanceis high. The phase change is accomplished by ohmic heatingof the chalcogenide. As shown in Fig. 6, a low voltage pulseanneals the chalcogenide to form crystalline phase (low 0 0.5 1.0 1.5 2.0 2.5resistance), but a higher voltage pulse melts the chalcogenide Voltage (Volts)momentarily and the subsequent fast quenching leaves anamorphous phase (high resistance) [10]. The typical memorycell consists of an access device, usually a MOSFET, and thechalcogenide resistor memory element. The cell is similar toa DRAM cell and has a cell size of 6F2- 8F2. The transition Vthlto amorphous state requires substantial current that cannot bedelivered by a minimum size transistor. Currently, cell sizes6F2 to 15F2 are achieved by using bipolar and MOS access VthOdevices, respectively [ 10,11] .

AmorphizingRESET Pulse

_*t1t- Low Hiqh ReadTm 5 <=; ........ 5 5 5 5VthVfh

Program/Read pulse shapeCrystallizing

ic / / \(SET) Pulse \ Fig. 7 Characteristics of threshold voltage programming forE Tx phase change memory. Different Vth can be achieved by

t2 \ applying different program pulse voltages. A read pulsebetween the high and low Vth with a narrow pulse width isused to detect the memory state [12].

Ta TimeOne desirable feature of phase change memory is thatTime the energy required to effect the phase change diminishes

Fig. 6 Temperature pulses for amorphizing (RESET) and for with device size at a steep rate. This is because much energycrystallizing (SET) phase-change chalcogenide. The is wasted through thermal loss, and the smaller volume oftemperature pulses are generated by electric pulses passing scaled element gains better efficiency. It is widely expectedthrough the phase change element. Typical RESET pulse is that PCRAM will become a NOR Flash replacement, and10-20 ns long, and the SET pulse duration is 50-100 ns [10]. perhaps even a universal memory [10].

Because chalcogenide exhibits threshold switching, it TaN/A1203/SiN/SiO2 (TANOS) device for NAND Flashis possible to use this characteristic to construct a memory A NAND Flash device using TaN gate, A1203 blockingarray without the additional access device. All devices stay oxide, and SiN for storage with a moderate (4 nm) tunnelin the amorphous (high resistance) state and memory state is oxide, shown in Fig. 8a, has been reported [13]. The TaNindicated by the threshold voltage of the device [12]. As gate has a relatively high work function (compared to n+shown in Fig. 7, the state of the device can be detected by polysilicon gate) that decreases electron injection from thereading the current (Vth) the same way as for Flash memory. gate during-FN erase operation. The A1203 high-K dielectricThis gives a cross point array with cell size of 4F2. Since the replaces the lower-K 5i02 as the blocking oxide, thusphase change element is not truly a transistor, the array improves the total BOT. The device is programmed by FNleakage is higher and large memory has to be broken down injection of electrons from the channel; the charges are

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stored in the SiN layer. Both erase and program operations (a) Band Diagram at Retentionhave been demonstrated with reasonable performance. 6Unlike SONOS where the very thin tunnel oxide allows N2 02 Ni 01 Si-channeldirect tunneling of substrate holes for erase, the tunnel oxide 4for TANOS is - 4 nm, for which the hole tunneling current is >too small to account for the erase speed. However, this issue 2 9 Cis unsettled since some report still favors a hole tunneling ___Vaiendc Bandmechanism [14]. Nevertheless, the impressive performance a) 0reported makes this approach an important candidate for i *efuture NAND Flash memory. r -2 ---eV

m(a) TANOS BE-SONOS (b) -4

-4

A1203Gate -20 0 20 40 60 80

SiN - l SiN ^ Mulaed Position (Angstrom)SiO9 cS; IN (b) Band Diagram at High Electric Fieldsio-7~ ~ ~ ~ one

SiN 19MEleti

nLn fl N2 02 Ni 01 Si-channelSource P-well Drain Source P-well Drain 10

Fig. 8 (a) TANOS device. (b) BE-SONOS device. > 8 Ga)

Bandgap engineered SONOS (BE-SONOS) for NAND m6)4and NOR Flash au)

SONOS has data retention problems because the thin g 2 C\nductionBandtunnel oxide cannot stop substrate hole direct tunneling. r 0 Vaince BandNROM uses a thick (5-7 nm) tunnel oxide and thus must use m -2band-to-band hot hole to erase. An ideal device would be onepossessing the benefits of thin tunnel oxide for fast erase and -4thick tunnel oxide for good data retention. This has been -6achieved by bandgap engineer the tunnel dielectric [15]. As -20 0 20 40 60 80shown in Fig. 8b, the tunnel oxide is replaced by triple layers Position (Angstrom)of ultra-thin ONO. Above the composite ONO tunneldielectric are the thick SiN trapping layer and the blocking Fig. 9 The operational principle of BE-SONOS. (a) Underoxide. low field electrons stored in the thick SiN (layer N2) and

Under low electric field, as in the case of data retention, holes in the Si substrate are blocked by the thick compositeholes in the substrate and electrons in the SiN are blocked by 02/Ni/01 barrier. (b) When a high voltage is applied duringthe total thickness of the ONO barrier, as in Fig. 9a. During erase operation, the band offset makes the SiN (NI) barriererase operation where a strong -FN field is applied, the SiN vanish and the 02 barrier minimal. Holes in the Si-channeland the top layer of tunnel oxide become invisible to the then inject into the trapping SiN (N2) layer by directsubstrate holes because of the band offset. Consequently, tunneling through the thin 01 layer.substrate holes can tunnel directly through the bottom layerof tunnel oxide and erase the device rapidly, as in Fig. 9b.

Using a p+ polysilicon gate to reduce gate electron By using an n+ polysilicon gate, the BE-SONOSinjection the operation of a NAND BE-SONOS Flash is well device can operate in a NOR array by using CHEunderstood, as shown in Fig. 8. The measured hole tunneling programming and -FN channel hole erase. The n+ poly gatecurrent at high and low fields match the WKB simulation allows gate electron injection during the -FN erase operation,results very well. At low field, direct tunneling is completely thus provides a self-converging erase Vt [12]. This providescut off thus providing good data retention. 2-bit/cell density similar to NROM, but without the

band-to-band tunneling hot hole concern.

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1-1 01=1.5 nm,. .F ~~~~~~~ONO Tunneling Wang, S. Pan, C.Y. Lu, and S. ES.Gu, "Data retention behavior

N 1 °-2 k < SONOS) 01/N 1/02 of a SONOS type two-bit storage flash memory ecell", in Tech.

10-3 =1.5/2/1.8 nm Dig. 2001 Inter. Electron Dev. Meeting (IEDM), pp. 719 - 722,-4 cf~~~~~~4vYv 2001.

1(BE-SONOS) v 7. I.C. Yang, K.P. Chen, Y.W. Chang, and T.C. Lu, "Analysis of

n1 0-5 k D Electron and Hole Distributions on scaled NBit Flash Cells",10-6 FN Tunneli ng in Proc. of 2006 VLSI-TSA (Hsinchu, Taiwan, ROC), pp.-~ a 01>3 nm 30-31,2006.

8. L. Perniola, G. lannaccone, B. De Salvo, G. Ghibaudo, G.10 2.3..5..7 9 0 12 Molas, C. Gerardi, and S. Deleonibus, "Experimental and1 2 3 4 5 6 7 8 9 10 11 12 13

theoretical analysis of scaling issues in dual-bit discrete trap

EO, (MV/cm) non-volatile memories", in Tech. Dig. 2005 Inter. ElectronDev. Meeting (IEDM), pp. 877-880, 2005.

Fig. 10 Simulated hole tunneling current for various 9. S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D.tunnel oxide and ONO structures. For SONOS device with Buchanan, "Volatile and Non-volatile Memories in Siliconthin tunnel oxide, direct tunneling current is high even under with Nano-crystal Storage", in Tech. Dig. 1995 Inter. Electronlow field. For thicker tunnel oxide (01 > 3 nm, such as for Dev. Meeting (IEDM), pp. 521-524, 1995.NROM) the hole tunneling current is very low, unsuitable for 10. S. Lai and T. Lowrey, "OUM - A 180 nm Nonvolatileerase operation. For BE-SONOS, the ultra-thin ONO allows Memory Cell Element Technology For Stand Alone andhigh hole current during erase operation, yet no direct hole Embedded Applications", in Tech. Dig. 2001 Inter. Electrontunneling during retention [15]. Dev. Meeting (IEDM), pp. 803-806, 2001.

11. S.J. Ahn, Y.J. Song, C.W. Jeong, J.M. Shin, Y. Fai, Y.N.SUMMARY Hwang, S.H. Lee, K.C. Ryoo, S.Y. Lee, J.H. Park, H. Horii,

Despite strong scaling limitations for both NOR and Y.H. Ha, J.H. Yi, B.J. Kuh, G.H. Koh, G.T. Jeong, H.S. Jeong,NAND Flash memories, solutions to continue the Moore's Kinam Kim and B.I. Ryu, "Highly manufacturable highlaw are also emerging. For NOR Flash memory, 2-bit/cell density phase change memory of 64Mb and beyond", in Tech.NROM, BE-SONOS and phase-change chalcogenide Dig. 2004 Inter. Electron Dev. Meeting (IEDM), pp. 907-910,memory show promise to scale below 35nm node. For 2004.NAND Flash memory, new nitride storage devices such as 12. Y.C. Chen, J.F. Chen, C.T. Chen, J.Y. Wu, S.L. Lung, R. LiuTANOS and BE-SONOS are candidates for < 30 nm devices. and C.Y. Lu, "An access-transistor-free (OT/iR) non-volatile

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