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102 978-4-900784-03-1 2007 Symposium on VLSI Technology Digest of Technical Papers 6B-4 Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation J.I. Lee, H. Park, S.L. Cho, Y.L. Park, B.J. Bae, J.H. Park, J.S. Park, H.G. An, J.S. Bae, D.H. Ahn, Y.T. Kim*, H. Horii, S. A. Song **, J.C. Shin, S.O. Park, H.S. Kim, U-In. Chung, J.T. Moon, and B.I. Ryu Process Development Team, *CAE Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd. San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea **AE Center, Samsung Advanced Institute of Technology, POB 111, Suwon, 440-600, Korea TEL:82-31-209-3898, Fax:82-31-209-6299, E-mail:[email protected] Abstract We first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50nm contact for sub 50nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 A and thermally stable CVD Ge 2 Sb 2 Te 5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150nm depth. Our results indicate that the confined cell structure of 50nm contact is applicable to PRAM device below 50nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect. Keywords: CMP, confined, GST, CVD, PRAM device. Introduction PRAM has been focused one of the candidate of a nonvolatile memory to challenge conventional memories such as DRAM and flash memory due to its fast switching speed, good endurance, and compatibility with CMOS logic process[1]. Nevertheless, high reset current and etch damage are the bottle neck problems of developing high density PRAM. Fig.1 shows the simulation result of required reset current of planar and confined cell structure along with contact diameter at the GST node height of 100nm. In comparison to conventional planar cell structure with sputtered GST, the reset current was dramatically reduced using confined cell structure up to 50% [2]. Fig.2 shows the simulation results of thermal disturbance effect along with cell distance. When the reset current is applied to confined cell structure, melting of GST is expected to occur between electrodes limiting to isolated cell as shown in Fig. 2(a) and the temperature of adjacent cells is lower than that of planar cell structure as illustrated in Fig. 2(b). In spite of expected superior properties of confined cell structure in comparison to planar cell structure, the poor filling of GST within the small contact using conventional sputtering used to limit high aspect ratio confined cell structure. In this paper, using 50nm contact cell technology [3], we first introduced high aspect ratio confined cell structure filled with CVD GST for sub 50nm technology of PRAM. Results and discussion Fig. 3 shows the process flow and vertical image of confined cell structure. After Metal-0 line, recessed metal Bottom Electrode Contact (BEC) was formed in the contact, in which CVD GST was filled. For the recessed bottom electrode in the contact, metal plug material was filled in the contact and recessed by etch back process. Metallization was formed directly on GST after Chemical Mechanical Polishing (CMP). As design rule shrinks, there is a narrow process window for Top Electrode Contact (TEC) and BEC formation considering patterning technology. In case of confined cell structure, integration process is much simpler than planar cell structure as GST and TEC patterning is not necessary. Fig.4 shows a cross-section TEM-EDS analysis of CVD GST. CVD GST film with approximate composition of 23:21:55 atomic percentage was prepared using metal organic precursor and H 2 as precursors at 350 . We successfully filled a contact having aspect ratio of 3 with CVD GST, and the composition was relatively uniform along with 150nm depth. XRD results of CVD GST in Fig. 5 indicate that GST was consisted of hexagonal phase and thermally stable up to 400 . Fig. 6 shows the top, tilt, and vertical SEM images after GST CMP, scratching and excessive dishing due to residues were not observed and GST void was not detected. Fig. 7 shows the series resistance of GST/BEC/M0 (~ 2.7k in median), which is similar to the value of the planar cell structure. This result indicates that CVD GST was filled uniformly in the contact. Fig.8 shows the resistance of phase changed confined and planar cell structure as a function of reset current. We could dramatically reduce reset current in confined cell structure below ~260 A maintaining 6.7k of set resistance, which is more than 50% reduction of reset current as simulated in Fig.1. Fig. 9 shows the retention result by reading the stored data after heating under isothermal conditions at 140 for 48hrs. Apparent resistance drop after heat treatment was not found. The endurance characteristics of confined cell structure in Fig. 10 showed that set and reset was maintained for more than 1E8 cycles. Reliability is a critical for PRAM to compete as a non volatile memory. Due to the minimization of etch damage, reliability characteristics of confined cell structure is expected to be more reliable than that of planar cell structure. Fig.11(a) shows the magnified TEM image of 50nm contact device, and Fig.11(b) shows the SEM image of fully integrated confined cell structure on diode. Diameter of bottom and top contact region in Fig. 11(a) was 40nm and 50nm respectively. Since GST size is scaled along with top diameter of contact at direct TEC on GST in confined cell structure, we were able to scale down the GST size below 50nm in size. Figure 12 shows the cell and GST size as a function of technical node [4]. In the planar cell structure, it will be a big challenge to reduce GST size below 90nm node, while in this work, we successfully meet the required GST size for sub 50nm technical node as shown in Fig. 12. In addition to size effect, high scalability of confined GST is expected due to lower reset current and low thermal disturbance effect as well, which allow us to predict the scalability up to sub 50nm technology. Therefore, it is predictable that confined cell structure with CVD GST is inevitable for the future generation beyond the 50nm technology of PRAM device. Conclusion Confined cell structure with CVD GST and 50nm contact was successfully integrated using CMP. Thermally stable CVD Ge 2 Sb 2 Te 5 having hexagonal phase was uniformly filled within a contact having aspect ratio of 3, and TEM-EDS results indicated that composition was constant along with 150nm contact depth. The reset current was below ~260 A, and endurance characteristic was maintained up to 1E8 cycles without failure. As well, no apparent drop of resistance for 48 hrs after 140 annealing was observed. Our results within small contact below 50nm indicate that confined cell structure filled with CVD GST is applicable to PRAM device below 50nm design rule due to small GST size based on small contact and direct TEC, reduced reset current, minimized etch damage, and low thermal disturbance effect. Reference [1] Y.N. Hwang et al., IEDM Tech. Dig.. p. 37.1.1, 2003. [2] S.L. Cho et al., Sump. VLSI Tech dig., p. 96, 2005. [3] S.J. Ahn et al., Sump. VLSI Tech dig., p. 98, 2005. [4] A.L. Lacaita., IMST EPCOS., 2006.
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