Steep Subthreshold Slope Nanowire FETs with Gate-Induced Schottky-Barrier Tunneling

Qiliang Li 1, 2, Xiaoxiao Zhu 1, 2, Dimitris Ioannou 1, John Suehle 2 and Curt Richter 2

1. Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030; 2. Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD

20899; phone: 1-703-993-1596, email: qli6@gmu.edu, curt.richter@nist.gov

We report Schottky-barrier (S-B) nanowire field effect transistors (NW FETs) with high-performance characteristics brought about by gate-induced Schottky-barrier tunneling. The devices exhibit sharp subthreshold slopes (as small as 45 mV/dec), well-saturated inversion-mode IDS–VDS characteristics, and large on/off current ratios (≈ 108). The excellent device properties are attributed to: (i) the enhancement of tunneling through the NW FET S-B by the gate-channel-source coupling which results in sharp subthreshold slope, (ii) the clean, CMOS-compatible fabrication of NW FET leading to a high-quality dielectric/nanowire interface, and (iii) the good quality S/D barriers and low S/D series resistance associated with them. Previous studies have demonstrated high-performance nanowire and nanotube FETs with on/off current ratios ≈ 105 and subthreshold swings (SS’s) ≈ 100 mV/dec [1, 2]. The sharpness of the SS is a critical parameter in determining how small a fraction of the applied gate voltage is used to switch the device on and thus the maximum dissipated power. Previous pioneering results [3-5] have shown that nanotube and nanowire FETs with SS < 60 mV/dec can be achieved based on avalanche breakdown or interband tunneling in the un-gated channel regions between the gate and S/D. Typically such devices require large drain voltages and may have large series resistance, non-saturating IDS-VDS, small on/off ratios and ambipolar conduction. The S-B NW FETs fabricated in this work exhibit sharp SS’s at low operation voltage, large on/off current ratios and inversion-mode saturating IDS-VDS.

The S-B NW FETs are fabricated over an entire wafer by using a self-aligning technique with standard photolithographic and metal lift-off processes, enabling the large-scale, uniform integration of high-performance nanowire devices. The key steps in the self-aligning process are in-situ self-assembling and patterning the Si NWs grown from Au catalyst on pre-defined locations (see Fig. 1 (a) – (c)). Fig. 1 (d) and (e) show scanning electron microscope images of two Si NW FETs with a single nanowire channel. From Fig. 2 it is seen that the output characteristics (IDS–VDS) of a typical NW FET with single nanowire channel (see Fig. 1 d) display clearly recognizable strong, moderate and weak inversion regions. Moreover, IDS is well saturated at 3Φt (Φt = kT/q) in weak inversion and at VGS – VTH in strong inversion. Such saturated I-V characteristics are advantageous for integrated circuit application.

Fig. 3 shows the transfer characteristics (IDS–VGS) of the device (VGS is the top gate voltage). This is a depletion-mode p-channel FET with a threshold voltage of ~ 0.6 V and IDS on/off ratio ≈ 108. The capacitance per unit length is calculated to be 280 aF/µm from Synopsis TCAD simulations of the structure shown in Fig. 1 (d) (NW diameter ≈ 16 nm, gate length L ≈ 6 µm, oxide ≈ 4 nm, HfO2 ≈ 25 nm). With ION = 200 nA at VDS = VGS = VDD = – 1.0 V (see Fig. 4), the intrinsic delay for the device is 8.4 ns. Assuming the physical device parameters remain the same for shorter gate lengths, the intrinsic delay is equal to 2.3 ps for L = 100 nm which is less than half of the intrinsic delay of a comparable planar Si MOSFETs (td ≈ 5.2 ps).

The SS values as extracted directly from the IDS–VGS curves decrease from 63 mV/dec to 55 mV/dec as VDS decreases to 0.1 V. This reflects a new operation mechanism: the sharp subthreshold slope is caused by the SiNW FET gate-source coupling via the channel (see Fig. 4b), which modulates the Schottky barrier width and height. Both the barrier width and height decrease as VGS becomes more negative (see Fig. 4c), and the field emission (FE) tunneling becomes more important than thermionic emission. TCAD simulations (see Fig. 4d) illustrate that such a tunneling current will induce sharp SS, below 60 mV/dec. The tunneling current increases with the effective carrier density (Neff) [6], which increases with negative bottom gate voltage VBG. Fig. 5 shows that SS decreases to as low as 45 mV/dec as VBG becomes more negative. We have developed model equations (listed in Table 1) for the IDS-VGS (Eq. 3) at the subthreshold region: IDS is a product of tunneling rate T(VGS) and weak inversion charge QI0 at the source end. SS (Eq. 4), a function of Neff and VGS, can be much smaller than 60 mV/dec at room temperature. SS will return to the conventional MOSFET limit nΦtln10 if the gate-induced Schottky-barrier tunneling is negligible (when a = 0 and b = 1). Neff (Eq. 5) increases (so tunneling increases and SS decreases) with negative VBG, which fits the experimental data very well as shown in Fig. 5. nΦtln10 was extracted from the fitted data as ~ 60 mV/dec, indicating the ideal factor, n ≈ 1 for an optimal interface and fully-depleted channel. At strong inversion (large VGS), the S-B is so thin and low that the NW FETs exhibit conventional FET behaviors. In conclusion, the Si NW FETs fabricated by using the self-alignment method exhibit saturated output characteristics, sharp subthreshold slopes and large on/off current ratios at low operation voltage. The sharp SS (as low as 45 mV/dec) is achieved by the gate-channel-source coupling which modulates the S/D S-B and enhances the tunneling in the NW FETs. ---------------------------------------------------------------------------------------------- 1. J. Xiang et al., Nature, vol. 441, p. 7092 (2006); 2. Z. Zhang et al., Appl. Phys. Lett., vol. 92, p. 133117 (2008); 3. J. Appenzeller et al., Phys. Rev. Lett., vol. 93, p. 196805 (2004); 4. Q. Zhang et al., EDL, vol. 27, p. 297 (2006); 5. M. Bjork et al., Appl. Phy. Lett., vol. 90, p. 142110 (2007); 6. F. Padovani et al., Solid-State Elec., vol. 9, p. 695 (1966);

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Fig.1 - (a) Au film (~ 1 nm) was patterned on the oxide (50 nm) surface as the SiNW growth catalyst. (b) The SiNWs were grown in a low temperature chemical vapor deposition furnace, oxidized with ~ 4 nm thermal SiO2, and then patterned in-situ with Al contacts for S/D. (c) The SiNWs were covered with 25 nm HfO2 and patterned with Al top gates. (d) & (e): the scanning microscope images of SiNW FETs with gate-source overlap = 1 µm and 0 µm, respectively.

VG

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− 0.2 V

− 0.4 V

− 0.6 V

− Ι D

S [

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VGS = − 0.8 V(b)

Fig. 3 - The transfer characteristics (IDS-VGS) (bottom gate VBG = 0) at both log scale and linear scale. The operation voltage window at VDD ≈ 1 V shows on/off ratio ~ 108. SS decreases as VDS decreases, which is different with interband-tunneling or breakdown mechanism.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.21f

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− Ι D

S [

A ]

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VDS= − 0.1 V

VDD = 1.0 V

VTH = 0.6 V

1 00 00⁄ tanh 00⁄ 1

⁄

101

⁄ ⁄

0 | |

exp

00 2 , , , 1

0 2

1 21

Table 1- Model equations for S-B NW FETs at the subthreshold region. T(VGS): FE tunneling rate; QI0: weak inversion carrier density in the source end; Neff: effective carrier density (Neff >> QI0); CBG and VTHB: bottom gate capacitance and threshold voltage; n: ideal factor of FETs; C1 and C2 are constant (not depending on VGS).

Fig. 2 - IDS – VDS curves of a typical NWFET with VGS from 1.0 V to – 1.8 V showstrong, moderate and weak inversion regions. The IDS is saturated at VDS = 3Φt (≈78 mV at RT) in weak inversion and VGS-VTH in strong inversion, similar to that ofa conventional planar MOSFET. (a): log-scale view. (b): linear scale view.

Fig. 4 - (a) 3-D schematic of a S-B NW FET. (b) The NW valence bandEV is bent upward by negative gate voltages, resulting in a thinning andlowering of the Schottky barrier. (c) Schottky barrier shapes at differentgate voltages. (d) TCAD simulations of S-B NW FETs: subthresholdswings ≤ 10 mV/dec are achieved as S-B tunneling become dominant.

(a)

(b)

(c)

(d)

Fig. 5 - Subthreshold swings as a function of VBG. The fitting is based on the equations shown in Tab. 1. As VBG becomes more negative, the effective hole carrier concentration increases, enhancing tunneling.

-4 -2 0 2 440

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978-1-4244-3527-2/09/$25.00 ©2009 IEEE 114