Hot Carrier Effects on CMOS Phase-Locked Loop Frequency Synthesizers

Yang Liu and Ashok Srivastava* Department of Electrical and Computer Engineering

Louisiana State University, Baton Rouge, LA, USA 70803 *Phone: (225) 578-5622; fax: (225) 578-5200; e-mail: ashok@ece.lsu.edu

Abstract Two CMOS phase-locked loop chips are designed and

fabricated in 0.5 µm n-well CMOS process using single-ended voltage-controlled oscillator and differential voltage-controlled oscillator circuits. Hot carrier effects, jitter and phase noise performances are investigated and analyzed. On-chip measured experimental results show that for the phase-locked loop with the single-ended voltage-controlled oscillator working at 500 MHz carrier frequency, phase noise is -76 dBc/Hz at 10 kHz offset frequency and -119 dBc/Hz at 1 MHz offset frequency. For the phase-locked loop with differential voltage-controlled oscillator working at 500 MHz, phase noise reaches -82 dBc/Hz at 1 kHz offset frequency and -122 dBc/Hz at 1 MHz offset frequency. Tuning frequencies of the two phase-locked loops decrease about 100-200 MHz when subjected to four hours of hot carrier stress. The single-ended VCO gain decreases from 260 MHz to 70 MHz due to hot carrier stress. For the phase-locked loop with the differential voltage-controlled oscillator, a 50 ps RMS jitter increase is observed under hot carrier stress.

Keywords Phase-locked loops, voltage-controlled oscillator, CMOS

integrated circuit, hot carrier effect, jitter; phase noise.

1. Introduction Phase-locked loop (PLL) is widely employed in various

applications. Among many applications, the PLL-based frequency synthesizers are the key components in communication systems. There are many requirements in these applications for the PLL design. Some of these requirements include phase noise, sideband spur, power consumption, frequency tuning range, voltage-controlled oscillators (VCO) tuning gain and locking/settling time. VCO is the essential part of a PLL frequency synthesizer. Two kinds of voltage-controlled oscillators are normally used, which are single-ended and differential types, to lock phase and limit timing skews between the system clock and the chip clock.

This paper describes and compares two fully integrated PLL designs. One PLL is built with a single-ended VCO and the other one with a differential VCO. The hot carrier effects on oscillation frequencies and jitter/phase noise of the two PLLs are investigated.

Hot carrier effect on voltage-controlled oscillators is addressed in [1-2], however, effects on jitter and phase noise measurements on PLL are presented in a limited scope. Phase and frequency fluctuations have been widely studied in [3-5] and jitter/phase noise issue of ring oscillator has been analyzed in [6-7]. Hot carrier effects are not investigated in

[3-7] while analyzing PLL jitter and phase noise performances. There is not much reported work which either presents performances of PLL with single-ended and differential voltage-controlled oscillators due to hot carrier effect or relating jitter and phase noise to the physics of MOS transistors. It is well established that with the shrinking device geometries, hot carrier effect becomes very significant and performance of integrated circuits degrades. In this paper, an attempt has been made to study the hot carrier effect in two PLL chips designed using single-ended VCO and differential VCO and its effect on phase/frequency and jitter/phase noise.

2. Chip Design

2.1. PLL Frequency Synthesizers Figure 1 shows the building block diagram of a PLL. The

architectures of the two PLL synthesizers are same. PLL with a single-ended VCO uses three divide-by-two cells for the frequency divider. In PLL with a differential VCO, the divider is designed by using three D flip flops in series.

PFDLoopFilter

VCO

Divider

Input Output

+-

Figure 1: PLL building blocks.

2.2. Voltage-Controlled Oscillators

The single-ended VCO and divide-by-two cells of the PLL are shown in Figure 2 (a) and (b), respectively. Figure 2 (a) is a current starved single-ended VCO. The n-MOSFETs connected to VBias support enough current to charge the ring oscillator. M7, M8 and M9 are added to stress the circuits. This single-ended VCO has two operation modes. One is the normal mode for oscillation and the other is the stress mode for hot carrier injection. When VMode = 5 V, M7-M9 transistors are turned-off and the VCO operates as a normal oscillator. When VMode= 0 V, the VCO operates in stress mode and VStress = 5 V is connected to drains of the ring oscillator. The oscillator is not working in stress mode but the circuit is under hot carrier injection.

The divider circuit of Figure 2 (b) is built by connecting three divide-by-two cells in series which make the divider 1 by 8. Transistor sizes are minimized, thus very little static leakage current flows through the divider. The divider can work with a signal frequency up to 1.5 GHz.

978-1-4244-6455-5/10/$26.00 ©2010 IEEE 92 11th Int'l Symposium on Quality Electronic Design

M1 M2 M3

Output

M4 M5 M6

ModeV

BiasV

StressV

DDVDDVDDV DDV

DDV

Figure 2(a): Current starved single-ended VCO.

clk

out

VDD

clk

Figure 2(b): Divide-by-two cells of PLL with single-ended VCO.

The design of differential VCO and divider are shown in Figure 3 (a) and (b). In Figure 3 (a) and (b), in oscillation mode, when M1 turns on and M2 turns off, M3 is turned off and M4 is turned on. Output_b will be logic “0” and Output_a will be logic “1”. Since Output_a and Output_b are connected to In_a and In_b of the next stage, In_a and In_b will be logic “0” and “1”. In stress mode, transistors connected to VMode are on and VStress = 5 V is connected to stress the circuits.

The divider is built by three D flip-flops connected in series which achieve the function of divide 1-by-8. In Figure 3 (b), clk_in is the signal from the output of VCO.

Figure 4 shows PFD, charge pump (CP) and loop filter circuits. A second order passive loop filter is used in this design with PFD/CP. PFD is designed from D-flip-flops and NOR gates as shown in Figure 5. The D-flip-flop is a controllable flip-flop that is built from inverters and transmission gates as shown in Figure 6. S1 and S2 in Figure 4 are used to control the charge or discharge of loop filter. C2 is much smaller than C1 to eliminate the higher order noise in the circuit.

VDD

VBias

In_a In_b

ModeVStressV

M1 M2

M3 M4

Output_aOutput_b

Figure 3(a): Differential VCO.

D D D

reset reset resetin in in

clk clk clkclk_inclk_out

reset Figure 3(b): Divider using three D flip-flops.

C1

VCTRL

C2

R

ICP

ICP

S1

S2

UP

DN

VDD

Loop Filter

PFD

in

feedback

CP

Figure 4: A diagram of loop filter with PFD and charge pump.

Figure 5: PFD circuits.

Figure 6: D flip-flop.

3. Hot Carrier Model of VCO

3.1. Model of Device Degradation due to Hot Carrier Effect

Device degradation caused by the hot electron injection has become of major concern while designing CMOS circuits in sub-micron process. Device degradation is related to the generation of acceptor interface traps. Threshold voltage and electron mobility are affected by this kind of generation at the drain end of MOSFETs. The interface traps are generated by

the breaking of silicon-hydrogen bonds HSis [8]. The

HSis bond is broken by hot electrons. Interstitial

hydrogen atom iH and trivalent silicon

iS are produced

which form interface traps. Following Eq. (1) shows this phenomenon.

iie

s HSHSi

(1)

An empirical model for the device degradation in terms of shift in threshold voltage has been developed in [9]. The threshold voltage shift is described as follows,

m

th AtV (2)

In Eq. (2), A is the degradation constant, which is strongly affected by the drain stress voltage (VStress). The parameter m in Eq. (1) which is the slope of log-log plot of Vth shift versus stress time, is strongly affected by VStress. In this design, VDD = 5 V and VStress = 5 V. For 0.5 µm channel length, the parameters are: 4m , VA 1 , mVVth 480 .

3.2 Model of Single-Ended VCO Single-ended VCO can achieve larger frequency swing, higher modulation sensitivity and is more capable for wide-band operation than the differential VCO. The gain of VCO output frequency is given by,

DDL

thBIASOX

BIAS

V VC

VV

L

W

n

C

V

fK

0 (3)

where OXC is gate oxide capacitance per unit area, W/L is the

channel width to length ratio of n-MOSFET, which decides

the frequency of VCO output. BIASV is the bias voltage and

thV is the threshold voltage.

The single-ended VCO oscillation frequency is given by [10],

max8)(

1

NLq

VWC

ttNf OX

fr

(4)

thDD VVV 2/ (5)

In Eq. (4), is a constant to describe the relationship

between the stage delay and the slope of the waveform which is 0.75 for 0.5 µm CMOS process. N is the number of stages in an oscillator which is 3 in this design, µ is the electron mobility, W and L are channel width and channel length of the transistor M1-M3 in Figure 2 (a). The total charge in each node of the oscillator is qmax. Rise and fall times are rt and

ft ,

respectively. V is the gate overdrive voltage. Under hot carrier injection, V changes and is expressed

as follows,

ththDD VVVV 2/ (6)

where thV is the threshold voltage shift.

The accumulated jitter in a single-ended VCO can be

modeled and calculated as follows. t represents the jitter

and is a function of t , the delay between the signal input of

the oscilloscope and the trigger input. t is given by,

tt (7)

char

DD

V

V

P

kT

3

8 (8)

where is the jitter proportionality constant. T is the temperature. Vchar is the characteristic voltage of the MOSFETs and is given by,

/VVchar (9)

In Eq. (9), is the noise ratio between the saturation and

linear regions and numerical value for a short channel device is 4/3.

VCO phase noise presents the variation of the original signal in a frequency domain. The equation below shows the phase noise performance of a CMOS single-ended VCO [10],

2

2

0

3

8

f

f

PV

kTVfL

char

DD

. (10)

In Eq. (10), f is the offset frequency from the carrier. P is

the power dissipation and is expressed as follows,

DDDVNIP (11)

where DI is the drain current in each stage.

3.3 Model of Differential VCO Differential VCO is less affected by the supply and bias

voltage variations. The differential VCO oscillation frequency is given by [11],

max2 Nq

If tail

(12)

where tailI is the tail current in each stage. The expressions

for and phase noise are as follows,

)(3

8

tailL

DD

char

DD

IR

V

V

V

P

kTN

(13)

)(3

82

20

tailL

DD

char

DD

IR

V

V

V

f

f

P

NkTVfL

(14)

where RL is the effective load resistance. The oscillation frequency and jitter/phase noise under the

hot carrier injection can be modeled by modifying the value of threshold voltage and electron mobility from equations (3-4), (7), (10) and (12-14).

4. Chip Design and Experimental Results The two PLL chips are designed in a standard 0.5 m n-

well CMOS process. In these two PLL designs, the loop parameters are the same: divider ratio is 8, charge pump current, ICH = 30µA, loop filter RC circuit parameters:

kR 5.41 , pFC 3.431 and fFC 1002 .

Figure 7 (a) and (b) show the chip layout of two phase-locked loop designs.

Figure 7(a): Layout of a PLL chip with single-ended VCO.

Figure 7(b): Layout of a PLL chip with differential VCO.

Figure 8 shows the transient response of the control voltage of the VCO from unlock to lock states, which takes ~ 200 ns for the PLL with single-ended VCO and ~ 300 ns for the PLL with differential VCO to stabilize. It shows that PLL with single-ended VCO has a shorter locking time in comparison to PLL designed with differential VCO because of the large tuning swing.

Figure 8: Transient response of the control voltage.

Figure 9 (a) and (b) show dependence of oscillation

frequencies on bias voltages of single-ended VCO and differential VCO with and without hot carrier stress. The stress time is 4 hours. After stress, the single-ended VCO tuning frequency decreases about 200 MHz and the differential VCO tuning frequency decreases about 100 MHz.

1.5 2 2.5 3 3.5 4 4.5 5300

400

500

600

700

800

900

1000

1100

1200

Bias Voltage (V)

Osc

illat

ion

Fre

quen

cy (

MH

z)

Before Stress

After Stress

Figure 9(a): Single-ended VCO tuning frequency versus bias voltage under hot carrier effect.

Figure 9(b): Differential VCO tuning frequency versus bias voltage under hot carrier effect.

Figure 10 shows experiment results of the decrease of single-ended VCO frequency gain at 3 V bias voltage versus stress time, which agrees with calculations of Eq. (3). The VCO gain decreases from 260 MHz to 70 MHz after 4 hours of hot carrier injection.

0 0.5 1 1.5 2 2.5 3 3.5 460

80

100

120

140

160

180

200

220

240

260

Stress Time (hour)

VC

O F

requ

ency

Gai

n (M

Hz/

V)

Figure 10: VCO gain versus stress time.

Figure 11 shows the experimental results of PLL with differential VCO jitter performance measured at 560 MHz output frequency by the sampling oscilloscope.

Figure 11: Experimental results of PLL jitter at 560 MHz carrier frequency.

Figure 12 shows the variation of RMS jitter in PLL with differential VCO output frequencies with and without hot carrier effects. The experimental results show a 50 ps increase after 4 hours of stress.

250 300 350 400 450 500 550 600 650 70040

60

80

100

120

140

160

180

200

PLL Output Frequency (MHz)

RM

S J

itter

(ps

)

Before Stress

After Stress

Figure 12: Experimental results of PLL jitter with differential VCO.

Figure 13 shows simulation results for in single-ended VCO which are compared before stress and after stress. It shows that the hot carrier stress increases the accumulated jitter by value in Eq. (7).

500 550 600 650 700 750 800 850 900 950 10002.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8x 10

-9

Frequency (MHz)

κ (√

s)Before Stress

After Stress

Figure 13: The dependence of on VCO tuning frequency due to hot carrier effect.

Figure 14 shows experimental result of phase noise of free running single-ended VCO and differential VCO at 700 MHz carrier frequency due to hot carrier effect. The phase noise is measured by using Agilent ESA-E4404B spectrum analyzer. Figure 14 shows that the differential VCO can achieve lower phase noise when compared with the phase noise of single-ended VCO because of the large load resistance. It shows that the experimental results agree with the results modeled from Eqs. (10) and (14).

104

105

106

-120

-110

-100

-90

-80

-70

-60

-50

Offset Frequency (Hz)

Pha

se N

oise

(dB

c/H

z)

Modeled S VCO After StressExp. S. VCO Before Stress

Exp. S. VCO After Stress

Modeled D. VCO After Stress

Exp. D. VCO Before StressExp. D. VCO After Stress

Figure 14: Variation of VCO phase noise due to hot carrier effect.

Figure 15 shows the comparison of measured phase noise

of two PLL chips due to hot carrier stress. The results show that the phase noise of PLL designed with a differential VCO is lower than the phase noise of PLL designed with a single-ended VCO. The phase noise is degraded about 1~2 dBc/Hz under the hot carrier stress for both frequency synthesizers.

Table 1 and Table 2 show experimental results for PLL frequency synthesizers with single-ended and differential VCOs, respectively.

104

105

106

-125

-120

-115

-110

-105

-100

-95

-90

-85

-80

-75

Offset Frequency (Hz)

Pha

se N

oise

(dB

c/H

z)

PLL with single-ended VCO before stress

PLL with single-ended VCO after stress

PLL with differential VCO before stress

PLL with differential VCO after stress

Figure 15: Phase noise degradation of two PLLs at 500 MHz carrier frequency.

RMS jitter is measured by using Tektronix 11801A digital sampling oscilloscope. Results show that the PLL designed with differential VCO has better performance on jitter and phase noise than the PLL designed with single-ended VCO. However, PLL designed with single-ended VCO has larger tuning gain and faster locking time when compared with the PLL designed with differential VCO.

Table 1: Experimental results for PLL with single-ended VCO

Input Freq. (MHz)

Output Freq. (MHz)

RMS Jitter (ps)

RMS Jitter (ps) After Stress

Phase Noise (dBc/Hz) @10kHz offset

Phase Noise (dBc/Hz) @1MHz offset

31 250 136 177 -77 -107

38 300 141 190 -65 -101

50 400 136 175 -73 -103

63 500 68 113 -76 -119

75 600 60 104 -68 -109

88 700 48 95 -60 -102

Table 2: Experimental results for PLL with differential VCO

Input Freq. (MHz)

Output Freq. (MHz)

RMS Jitter (ps)

RMS Jitter (ps) After Stress

Phase Noise (dBc/Hz) @10kHz offset

Phase Noise (dBc/Hz) @1MHz offset

31 250 139 179 -70 -117

38 300 140 192 -75 -113

50 400 139 178 -77 -114

63 500 63 114 -82 -122

75 600 60 107 -68 -118

88 700 47 98 -68 -110

5. Conclusion The paper presents two fully integrated PLL frequency

synthesizers and compares designs for phase/frequency and jitter/phase noise performances. Device degradation models for the two kinds of VCO are investigated based on hot carrier effects. The accumulated jitter can be predicted by the proportionality parameter, . The phase noise of the PLL with single-ended VCO is in the range -60~-119 dBc/Hz under entire PLL oscillation frequency. The phase noise of the PLL with differential VCO is in the range -68 ~ -122 dBc/Hz under entire PLL tuning frequency. Hot carrier effect is limited to PLL implemented in 0.5 m CMOS. On the other hand NBTI is more pronounced in p-MOSFETs in deep-submicron/nm CMOS technologies. The present work does not consider the effect of NBTI on p-MOSFETs of PLL. The extension of this work considering the combined effect of hot carrier injection and NBTI on PLL performance will be a part of another future publication.

Acknowledgment Authors acknowledge support in part from National

Science Foundation under ECS Grant #0426644.

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