Novel Control Method for Matrix Converter to Reduce Switching Loss

Wei Cai, Xiaofeng Zhang, Mingzhong Qiao College of Electric and Information Engineering

Naval University of Engineering Wuhan, China

e-mail: caiwei19830530@163.com

Bi He China State Shipbuilding Corporation 704 Institute

Shanghai, China

Abstract—The high differential voltage in commutation under transitional space vector modulation strategy is the cause which results in large switching loss of matrix converter. This paper presents a novel method which rearranges the switching sequence according to the magnitude of input voltages, based on the analysis and calculation of switching loss. Combined with voltage commutation strategy, the new modulation method is utilized in matrix converter. The simulation and experiment verify the validity and feasibility of the proposed method.

Keywords-component; switching loss; rearrangement of switching states; matrix converter

I. INTRODUCTION Space vector modulation (SVM) is one of the common

modulation strategies of matrix converter (MC). The approach is easy to realize, having the advantages such as low computational complexity, adjustable power factor and the control ability under unbalanced input voltage, so it attracts many scholars’ attention [1]. Various selections and arrangement of the vectors result in abundant research production in SVM strategy, which suggest that we can optimize the method furthermore. For instance, the narrow pulse is prone to seen when MC is under low modulation index. The phenomena can be eliminated through the proper arrangement of zero vectors [2], meanwhile, the voltage is compensated [3]. The common-mode voltage of MC also can be controlled by this way [4].

Voltage commutation strategy is actually utilized corresponding to SVM. To avoid short circuit in voltage commutation, we rearrange the switching states in practice, the method we called “rearrangement of switching states”. This method doesn’t change the mean of input current and output voltage, so the waveforms are sinusoidal all the same [5]. But rearrangement of switching states also brings some problems, on which less research is given. For example, the switching loss changes as we use the different vectors sequence [6]. Aiming at the problem above, this paper presents an optimized synthetically SVM strategy from the point of view of the switching loss reduction. Related simulation and experiment is given to certify the validity of the method at last.

II. SPACE VECTOR MODULATION

A. Arrangement of Zero Vectors in Space Vector Modulation Many scholars give the research on the SVM of the MC. In

the modulation strategy, four effective vectors and zero vectors are in use, whose duty circles can be defined as d1, d2, d3, d4 and d0 separately. The zero vectors can be arranged by many ways in practice. Take the unilateral modulation strategy as the example, when the zero vector is prepositive, (we defined it as pre-zero vector), the sequence of the duty circle is d0-d1-d2-d3-d4; when the zero vector is middle, (we defined it as mid-zero vector), the sequence is d1-d2-d0-d3-d4; when the zero vector is postpositive, (we defined it as post-zero vector), the sequence is d1-d2-d3-d4-d0; when the 3 zero vectors are arranged, the sequence is d01-d1-d2-d02-d3-d4-d03, (d01, d02, d03 are all the duty circles of zero vectors, and d01+d02+d03=d0). The configuration of an arbitrary number of zero vectors is analogous.

Output voltage intervals and input current intervals of MC are schemed in Fig. 1. The corresponding vectors of the duty circles vary according to the intervals. Tab.1 gives switching states of SVM in input current interval 1 and output voltage interval I-VI, in which “baa” presents the output phases “A, B, C” link the input phases “b, a, a” respectively, the other intervals are similar.

1 2 3 4 5 6ii

ia iaib ic

I II III IV Vuo

uA uAuB uC

VI 6V

θ iθ oπ 00 π 2π

(a) Output voltage intervals (b) Input current intervals

Figure 1. Output voltage intercals and input current intervals

TABLE I. SWITCHING STATES OF SVM IN INPUT CURRENT INTERVAL 1

vector select corresponding duty

input current interval 1 I II III IV V VI

pre-zero vector d01 bbb bbb bbb bbb bbb bbb 1st effective vector d1 abb bab bab bba bba abb 2nd effective vector d2 aab aab baa baa aba aba

This project is sponsored by National Natural Science Foundation (51007094)

978-1-4577-0547-2/12/$31.00 ©2012 IEEE

mid-zero vector d02 aaa aaa aaa aaa aaa aaa 3rd effective vector d3 aac aac caa caa aca aca 4th effective vector d4 acc cac cac cca cca acc post- zero vector d03 ccc ccc ccc ccc ccc ccc

B. Transverse Description of Duty Circle in Space Vector Modulation We can get the output voltage in one switching period

under bilateral modulation strategy using 3 zero vectors in interval I-1 (i.e. output voltage interval I, input current interval 1), according to the switching states and the input voltage. It is shown in Fig.2.

d01/2d1/2

d2/2 d02/2 d3/2d4/2

d01/2d03d4/2

d3/2 d02/2 d2/2d1/2

ua

ub

ub

ub

ua

ua

uc

uc

uc

uA

uB

uC

abb aab aaa aac acc ccc acc aac aaa aab abbbbb bbb

ua

ua

ua

ub

ub

ub

dividing the switching period vertically

(a) 7 vertical duty circles

uA

uB

uC

abb aab aaa aac acc ccc acc aac aaa aab abbbbb bbb

daA/2

daB/2

daC/2

dcA

dcB

dcC

dbA/2

dbB/2

dbC/2

daA/2

daB/2

daC/2

dbA/2

dbB/2

dbC/2

dividing the switching period transversely (b) 9 transverse duty circles

Figure 2. Output voltage of SVM using 3 zero vectors

In section 2.A, we use d1, d2, d3, d4, d01, d02 and d03 to present the sequence of the vectors in SVM. These duty circles are actually the vertical description of time by dividing the entire switching period vertically from the perspective of integrated 3 phase output, which illustrates in Fig.2 (a). We defined them as vertical duty circles. From the perspective of single phase output, each output phase links input in sequence ub→ua→uc, then we can get 9 duty circles defined as transverse duty circles. They are shown in Fig.2 (b).

Three transverse duty circles of each phase output can be assembled by 7 vertical duty circles. For example, three duty circles of output phase B in Fig.2 can be assembled as:

daB=d2+d3+d02 dbB=d1+d01 (1) dcB=d4+d03

In (1), daB is the duty circle linking output phase B to input phase a. By this way, we can translate 7 vertical duty circles into 9 duty circles.

III. IMPLEMENT OF REARRANGEMENT OF SWITCHING STATES IN SPACE VECTOR MODULATION

A. Principle of the rearrangement of switching states So-called “rearrangement of switching states” is the change

of switching sequence in modulation [5]. For example, a single

phase switching sequence of MC modulation in a period Ts is ua→ub→uc initially (i.e., the output phase links to the input phase a, b, c in turn). Through the method (rearrangement of switching states), a new sequence ua→uc→ub is obtained. The process is shown in Fig.3.

00

Ts Ts

uc uc

ua ua

ub ub

d3 d3

d1 d1d2

d2

initial optimized

Figure 3. Principle of rearrangement of switching states

B. Reduce switching loss using rearrangement of switching states The paper presents simulation under the modulation

strategy using 3 zero vectors without loss of generality. The other arrangements of zero vectors can be regarded as the special case of arrangements of 3 zero vectors.

Fig.4 is the modulation sequence of SVM using 3 zero vectors and the waveform of output voltage. The simulated input lint to line voltage is 300V (rms), with 50Hz frequency. The voltage ratio is set at 0.6, while the frequency of output voltage is 30Hz,

(a) traditional unilateral modulation (b) improved unilateral modulation

Vol

tage

(80V

/div

)

Time(1ms/div)

commutation under high differential voltage

ua

ub uc

(c) output phase voltage under traditional SVM

Vol

tage

(80V

/div

)

Time(1ms/div)

commutation according to the

magnitude of input voltages

ua

ub uc

(d) output phase voltage under optimized SVM utilizing

rearrangement of switching states

Figure 4. Output phase voltage of SVM using 3 zero vectors

Fig.4 (a) and Fig.4 (c) shows the performance of traditional SVM strategy. In this method, MC is in the process of low-high-middle commutation (ub→ua→uc) under high differential voltage all along for the high zero mid-vectors ua. Even if ua is unused, low-middle commutation (ub→uc) exists in only one output phase, the other 2 output phases still include the high voltage in the middle, which result in the high differential voltage causing some unnecessary switching loss.

Because the rising and falling process of collector-emitter voltage and current is complex when turning on the switching semiconductor and turning off, the process analysis is given according to linear variation generally [7]. The turn-on loss Eon and turn-off loss Eoff of IGBT is a function correlating the product of on-state current and off-state collector-emitter voltage. Under the hard-switch mode, they can be calculated as following:

on ce_off on on

off ce_off on off

2

2

E U I t

E U I t

=

= (2)

In (2), Uce_off is the IGBT off-state voltage, Ion is the IGBT on-state current, ton and toff is the process time of turning on and turning off separately.

Take the commutation in Fig.4 (a) for example, the unilateral sequence is ub→ua→uc, then two differential off-state voltage of commutation are uab and uac. On the assumption that the load current I is constant in a single switching period (I=Ion), the output phase occurs one turn-on process and one turn-off process in every commutation [2], and the differential voltage are the same. Then the switching loss of the phase under traditional bilateral modulation can be obtained:

( ) ( )SVM1 b a a c c a a b

ab on off ac on off

2 2

E E E E Eu I t t u I t t

→ → → →= + + ++ +

= + (3)

Utilizing the rearrangement of switching states, the switch sequence according to the sequence of input voltage magnitude is ub→uc→ua, which is shown in Fig.4 (b). Two differential off-state voltages in commutation are uab and uac. Then the switching loss of the phase under new method can be obtained:

( ) ( )

( )

SVM2 b c c a a c c b

cb on off ac on off

ab on off

2 2

2

E E E E Eu I t t u I t t

u I t t

→ → → →= + + ++ +

= +

+=

(4)

In the shadow of Fig.4 (a), 0.5uab≤uac<uab, we can find that the switching loss under new method is half less than the traditional modulation strategy. The result of the modulation using single zero vector is similar.

The reason of reduction on switching loss is obvious, that is the high voltage ua in middle which makes differential off-state voltage high in commutation. So the rearrangement of switching states should be used in entire period to decrease the voltage change for the power loss reduction theoretically.

But there a problem must be attached importance to, which is the modulation is not suit to any situation. Reference [13] presents a two-step voltage commutation with a transition zone. The differential voltage is higher, the commutation is safer. If we take commutation as above, the failure maybe takes place in the transition zone where two phase voltage is close (ellipse in Fig4.(d)). So we must consider the strategy synthetically in practice. In the main zone where differential voltage is high, we can rearrange the switching sequence according to the magnitude of voltage to reduce the switching loss; in the transition zone, we can rearrange the sequence according to high differential voltage to ensure the commutation safety. Fig5 illustration shows the waveform of output phase voltage under optimized SVM.

Vol

tage

(80V

/div

)

Time(1ms/div)

main zone

80Vtransition zone

ua

ub uc

Figure 5. Output phase voltage of optimized SVM with short circuit avoided

and switching loss reduced

IV. EXPERIMENTAL RESULTS To illustrate the advantages obtained by the proposed

method, a prototype of a three-phase to three-phase 5 kW MC has been used to supply a linear passive R–L load. The control algorithm is implemented on the platform TMS320F28335, which is a floating-point digital signal processor provided by Texas Instruments. The switching frequency of the SVM strategies is 5 kHz. The converter is fed by an ac power supply through a transformer and the output links load through a L–C filter. The parameters of filter, supply, and load correspond to those reported in Tab.II.

TABLE II. SYSTEM PARAMETERS

supply filter load Vline-line=300 V(rms) Lf=0.2 mH VL=175 V(rms)

fs=50 Hz Cf=20 mF fL=30 Hz RL=7.5 Ω LL=1 mH

The experiment uses the voltage commutation in reference 13, i.e., the new method is not utilized in entire switching period.

Fig.6 is the experimental waveform of output phase voltage by the method reducing switching loss with one zero vector. It is seen that in main zone, the commutation takes place according to the sequence of voltage magnitude; in the transition zone, the high differential voltage is used as mid-zero vector to ensure the safe commutation. The waveform is similar to the Fig.5.

Time(5ms/div)

Vol

tage

(100

V/d

iv) transition zone according

to high differential voltage

main zone according to the magnitude of

voltage

Figure 6. Experimental waveform of output voltage by

using reducing switch loss

The switching loss of the method is experimentally obtained. Environmental temperature is 7.2℃. For getting the obvious result, a less resistance is selected to boost the load current. After half an hour work, we detect the temperature of the radiator. At the same condition where the output power is 4 kW, the temperature of the radiator is 29.3℃ by the traditional method, while the temperature is 26.6℃ by the proposed method. The result proves the effect of the new method in power switching loss reduction.

Fig7 is the contrast experimental waveform by the traditional method and new method reducing switching loss with one zero vector.

Time(10ms/div)

Vol

tage

(500

V/d

iv)

Cur

rent

(20A

/div

)

optimizedinitial

Vol

tage

(500

V/d

iv)

Cur

rent

(20A

/div

)

Time(10ms/div)

(a) output line-line voltage and phase current

Time(5ms/div)

Cur

rent

(20A

/div

)V

olta

ge(2

00V

/div

)

optimizedinitial

Cur

rent

(10A

/div

)

Cur

rent

(20A

/div

)V

olta

ge(2

00V

/div

)C

urre

nt(1

0A/d

iv)

Time(5ms/div)

(b) output phase voltage and output phase current before filter and latter

Time(5ms/div)

Vol

tage

(100

V/d

iv)

commutation under high differential voltage all the time

commutation according to high differential voltage

commutation according to the magnitude of voltage optimizedinitial

Vol

tage

(100

V/d

iv)

Time(5ms/div) (c) magnified waveform of output voltage

Figure 7. Experimental waveform by using and without using reducing switching loss

The output voltage is shown in fig8. It is similar to the simulation result. Although output phase voltage is influenced some, the output line-line phase is influenced little with little affection on input current and output current for the new method changes the order of the switching state only.

V. CONCLUSION The high differential voltage in commutation under

traditional SVM strategy makes the unnecessary switching loss. This paper presents a new method changing the order of the switching state according to sequence of the input voltage magnitude, which is utilized for the switching loss reduction. The simulation and experimental results verify the correctness and validity.

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