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IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 2, FEBRUARY 2015 141 Significant Reduction of Dynamic Negative Bias Stress-Induced Degradation in Bridged-Grain Poly-Si TFTs Meng Zhang, Zhihe Xia, Wei Zhou, Rongsheng Chen, Man Wong, Senior Member, IEEE , and Hoi-Sing Kwok, Fellow, IEEE Abstract— The device degradation of bridged-grain (BG) polycrystalline silicon thin-film transistors under dynamic negative bias stress (NBS) is investigated for the first time. By employing a BG structure in the active channel, dynamic NBS-induced hot carrier degradation could be significantly reduced from -99.9% to -2.4% (10 4 s dynamic NBS), which is attributed to a sharing of the lateral electric field across the multiple p-n junctions inherent in the structure. The nonequi- librium junction degradation model is employed and developed, incorporated with TCAD simulations. Index Terms— Bridged-grain, polycrystalline silicon, thin film transistor, dynamic negative bias stress, hot carrier. I. I NTRODUCTION P OLYCRYSTALLINE silicon (poly-Si) thin-film transistor (TFT) has been considered as a promising candidate for the realization of system-on-panel (SOP) application due to its ability to integrate pixel switching elements and driving circuits on a glass substrate [1]. Improvements in the per- formance and the reliability of poly-Si TFTs thus become the most important requirements for SOP application [1], [2]. Unlike pixel TFTs, TFTs in driver circuits suffer from dynamic voltage stresses [3]. Different from DC voltage stresses, dynamic voltage stresses could induce additional degradation in poly-Si TFTs at pulse transients [3]–[8]. The dynamic hot carrier (HC) effect [4]–[8] at pulse transients has been identified as the main degradation mechanism. Such dynamic voltage stress induced degradation mechanism has been inves- tigated and clarified for several years. However, research work on how to improve such dynamic voltage stress induced degradation in poly-Si TFTs is rarely reported. In this work, device degradation of bridged-grain (BG) poly-Si TFTs under dynamic negative bias stress (NBS) is characterized and analyzed for the first time. By employing Manuscript received October 27, 2014; revised November 22, 2014 and November 26, 2014; accepted November 27, 2014. Date of publication December 4, 2014; date of current version January 23, 2015. This work was supported by the Research Grants Council, Hong Kong Government through the Theme-Based Research Project under Grant T23-713/11-1. The review of this letter was arranged by Editor S. Hall. The authors are with the State Key Laboratory on Advanced Displays and Optoelectronics Technologies, Hong Kong University of Science and Technology, Hong Kong (e-mail: [email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2014.2377040 Fig. 1. (a) Cross-sectional schematic of the BG TFT and waveforms of gate voltage pulses applied to the gate electrode with S/D electrodes grounded. (b) SEM image of PR pattern of BG lines. a BG structure in the active channel, significant reduction in dynamic NBS induced HC degradation is observed. On-state current ( I on ) degradation is reduced from 99.9% to 2.4% after 10 4 s dynamic NBS. The related degrada- tion mechanism is proposed and discussed, incorporated with TCAD simulations. II. EXPERIMENTAL The schematic cross-section of the BG TFT is shown in Fig. 1a. First, 50nm-thick amorphous-Si (a-Si) was deposited on the substrate as the active layer by low-pressure chemical vapor deposition (LPCVD). The metal-induced crystallization method [9] was applied to convert a-Si film into poly-Si film. Then 50nm-thick low temperature oxide (LTO) was deposited, which would serve as the sacrificial layer for BG ion implanta- tion. A layer of photoresist (PR) was spin-coated and patterned into gratings with a period of 1 μm and an aspect ratio of 50%. Structures of the patterned PR captured by the scanning electron microscope (SEM) are shown in Fig. 1b. Boron implantation was performed to the exposed areas through the gratings. After implantation, the PR and LTO sacrificial layer were removed, followed by active island patterning. Then, 70nm-thick SiO 2 was deposited by LPCVD as the gate dielectric. Next, aluminum (Al) was deposited to act as the gate metal, followed by boron implantation to form the self-aligned source (S) and drain (D). Finally, passivation LTO and metal layers were formed and patterned to complete the fabrication process. For comparison, normal TFTs were also fabricated at the same time by going through the same processes only without the BG treatment. 0741-3106 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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Page 1: IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 2, FEBRUARY ...

IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 2, FEBRUARY 2015 141

Significant Reduction of Dynamic NegativeBias Stress-Induced Degradation in

Bridged-Grain Poly-Si TFTsMeng Zhang, Zhihe Xia, Wei Zhou, Rongsheng Chen, Man Wong, Senior Member, IEEE,

and Hoi-Sing Kwok, Fellow, IEEE

Abstract— The device degradation of bridged-grain (BG)polycrystalline silicon thin-film transistors under dynamicnegative bias stress (NBS) is investigated for the first time.By employing a BG structure in the active channel, dynamicNBS-induced hot carrier degradation could be significantlyreduced from −99.9% to −2.4% (104 s dynamic NBS), whichis attributed to a sharing of the lateral electric field across themultiple p-n junctions inherent in the structure. The nonequi-librium junction degradation model is employed and developed,incorporated with TCAD simulations.

Index Terms— Bridged-grain, polycrystalline silicon, thin filmtransistor, dynamic negative bias stress, hot carrier.

I. INTRODUCTION

POLYCRYSTALLINE silicon (poly-Si) thin-film transistor(TFT) has been considered as a promising candidate

for the realization of system-on-panel (SOP) application dueto its ability to integrate pixel switching elements and drivingcircuits on a glass substrate [1]. Improvements in the per-formance and the reliability of poly-Si TFTs thus becomethe most important requirements for SOP application [1], [2].Unlike pixel TFTs, TFTs in driver circuits suffer from dynamicvoltage stresses [3]. Different from DC voltage stresses,dynamic voltage stresses could induce additional degradationin poly-Si TFTs at pulse transients [3]–[8]. The dynamichot carrier (HC) effect [4]–[8] at pulse transients has beenidentified as the main degradation mechanism. Such dynamicvoltage stress induced degradation mechanism has been inves-tigated and clarified for several years. However, research workon how to improve such dynamic voltage stress induceddegradation in poly-Si TFTs is rarely reported.

In this work, device degradation of bridged-grain (BG)poly-Si TFTs under dynamic negative bias stress (NBS) ischaracterized and analyzed for the first time. By employing

Manuscript received October 27, 2014; revised November 22, 2014 andNovember 26, 2014; accepted November 27, 2014. Date of publicationDecember 4, 2014; date of current version January 23, 2015. This work wassupported by the Research Grants Council, Hong Kong Government throughthe Theme-Based Research Project under Grant T23-713/11-1. The review ofthis letter was arranged by Editor S. Hall.

The authors are with the State Key Laboratory on Advanced Displaysand Optoelectronics Technologies, Hong Kong University of Science andTechnology, Hong Kong (e-mail: [email protected]).

Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2014.2377040

Fig. 1. (a) Cross-sectional schematic of the BG TFT and waveforms of gatevoltage pulses applied to the gate electrode with S/D electrodes grounded.(b) SEM image of PR pattern of BG lines.

a BG structure in the active channel, significant reductionin dynamic NBS induced HC degradation is observed.On-state current (Ion) degradation is reduced from −99.9%to −2.4% after 104s dynamic NBS. The related degrada-tion mechanism is proposed and discussed, incorporated withTCAD simulations.

II. EXPERIMENTAL

The schematic cross-section of the BG TFT is shown inFig. 1a. First, 50nm-thick amorphous-Si (a-Si) was depositedon the substrate as the active layer by low-pressure chemicalvapor deposition (LPCVD). The metal-induced crystallizationmethod [9] was applied to convert a-Si film into poly-Si film.Then 50nm-thick low temperature oxide (LTO) was deposited,which would serve as the sacrificial layer for BG ion implanta-tion. A layer of photoresist (PR) was spin-coated and patternedinto gratings with a period of 1 μm and an aspect ratio of 50%.Structures of the patterned PR captured by the scanningelectron microscope (SEM) are shown in Fig. 1b. Boronimplantation was performed to the exposed areas throughthe gratings. After implantation, the PR and LTO sacrificiallayer were removed, followed by active island patterning.Then, 70nm-thick SiO2 was deposited by LPCVD as thegate dielectric. Next, aluminum (Al) was deposited to actas the gate metal, followed by boron implantation to formthe self-aligned source (S) and drain (D). Finally, passivationLTO and metal layers were formed and patterned to completethe fabrication process. For comparison, normal TFTs werealso fabricated at the same time by going through the sameprocesses only without the BG treatment.

0741-3106 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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142 IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 2, FEBRUARY 2015

Fig. 2. (a) Time evolution of transfer characteristics under dynamic NBSfor normal TFTs and BG TFTs. (b) Extracted �Ion dependent on stress timeunder dynamic NBS and DC stress in both normal TFTs and BG TFTs.

For poly-Si TFTs under test, channel width (W ) and channellength (L) are both fixed at 10 μm. As shown in Fig. 1a, squareVg pulse stress was applied to gate electrode with groundedS/D electrodes. The pulse swings from 0V to a peak voltageof −20V at a fixed duty ratio of 50%. Pulse parameters includefrequency ( f ), pulse number (N), pulse rising time (tr ) andpulse falling time (t f ). Device degradation is evaluated by apercentile change in Ion with respect to its initial value (�Ion).

III. RESULTS AND DISCUSSION

Transfer curve degradation behaviors under dynamic NBSin both normal TFTs and BG TFTs are shown in Fig. 2a.It is worth mentioning that under DC Vg stress of the sameamplitude (−20V), almost no degradation occurs in bothnormal TFTs and BG TFTs, as shown in Fig. 2b (hollowsymbols). For the initial characteristics, BG TFTs apparentlyshow much better electrical characteristics compared to normalTFTs. These great improvements achieved by utilizing theBG structure are mainly attributed to grain size effect [9]–[11],short channel effect [9]–[11] and characteristics of normalTFTs significantly degenerate, while for BG TFTs, the charac-teristics seem to have no change. Extracted from the transfercurve degradation of normal TFTs and BG TFTs after 104sdynamic NBS, as shown in Fig. 2b, the Ion degradation ofnormal TFTs is almost −100%, while for BG TFTs, theIon degradation is only −2.4%. By examining the devicedegradation more carefully, the Ion degradation of both normalTFTs and BG TFTs exhibits two stage degradation behaviors,which is also observed by the previous reports [12], [13].For the first stage degradation, electron trapping into thegate oxide [7], [12], [13] is responsible. For the secondstage degradation, dynamic HC effect at pulse transient maydominate since the degradation features in the second stageaccords well with the typical HC degradation [13].

The degradation of both normal TFTs and BG TFTsunder dynamic NBS is independent of f when plotting thedegradation data against the pulse number N (not shownhere), indicating that the degradation is associated with pulsetransients [3]. To clarify the key factors controlling the devicedegradation, device reliability under dynamic NBS with differ-ent tr and t f are examined. Shown in Fig. 3a is N dependentIon degradation for various tr with fixed t f = 0.1 μs.

Fig. 3. Pulse number dependent �Ion for (a) various tr with t f = 0.1 μsand for (b) various t f with tr = 0.1 μs in normal TFTs and BG TFTs.

Fig. 4. The dependence of lateral electric field Ex at the channel/edge on(a) the normalized tr transient and (b) the normalized t f transient in normalTFTs and BG TFTs. The inset is a device cross section showing where Exis simulated.

Clearly, BG TFTs (blue lines) exhibit more stable performancecompared to normal TFTs (red lines). Furthermore, for bothnormal TFTs and BG TFTs, Ion degradation curves overlapeach other under dynamic NBS with various tr , indicatingthe degradation is independent of tr . Shown in Fig. 3bis N dependent Ion degradation for various t f with fixedtr = 0.1 μs. Again, BG TFTs (blue lines) exhibit more stableperformance compared to normal TFTs (red lines). In normalTFTs, for a faster t f the device degenerates more severelyin the second stage and the turnaround point appears earlier.Trap state generation due to electron injection in the first stagetriggers the second stage degradation [13], [14]. For a faster t f ,electron injection in the first stage is severer [13], [14], leadingto an increasingly rapid growth of trap states. Therefore, thesecond stage degradation appears earlier. While for BG TFTs,Ion is enhanced by a faster t f in the first stage degradationand the second stage degradation is still absent within the104s dynamic NBS. These test results reveal that BG TFTs aremuch more stable than normal TFTs under the same dynamicNBS and the dynamic NBS induced degradation is related tot f rather than tr .

To investigate the underlying mechanism of dynamic NBSinduced degradation in normal TFTs and BG TFTs, a transientsimulation was performed by utilizing Silvaco ATLAS basedon a continuous defect poly-Si model. The total density ofstates includes two exponential tail bands and two Gaussiandeep bands. Optimum values of the model parameters areextracted from fits to subtheshold and output characteristics.In Fig. 4, the calculated lateral electric field (Ex) is plotted

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ZHANG et al.: SIGNIFICANT REDUCTION OF DYNAMIC NBS-INDUCED DEGRADATION 143

Fig. 5. Extracted Ex at 10nm below the oxide/channel interface alongthe source side to the drain side at the end of t f in a normal TFT and aBG TFT. The insets are Ex distribution in a normal TFT (upper) anda BG TFT (lower).

against the normalized transient moments. In Fig. 4a, withinthe tr transition, Ex curves for different tr in both normalTFTs and BG TFTs almost overlap each other and the valueof |Ex | is only ∼104V/cm, indicating the dynamic NBSinduced degradation is independent of tr . While within thet f transition, as shown in Fig. 4b, the Ex in both normalTFTs and BG TFTs first increases quickly to a high field(>105V/cm) and then deceases slowly at the rest part of t f .Carriers exposed to such high Ex become HCs, resulting indevice degradation [8]. For both normal TFTs (red lines) andBG TFTs (blue lines), a faster t f brings larger Ex and largerHC degradation. Furthermore, it is noted that Ex for BG TFTsis much smaller than that of normal TFTs at the same t f ,which explains why BG TFTs are more stable than normalTFTs in the second stage under the same dynamic NBS.

To clarify the underlying degradation mechanism, the non-equilibrium junction degradation model [13] is employed anddeveloped. When the pulsed Vg swings from 0V to −20Vwithin tr , the S/D junctions become forward biased andEx is too low (Fig. 4a) to generate HCs [13]. Thus, thedegradation in both normal TFTs and BG TFTs is independentof tr (Fig. 3a). When the pulsed Vg swings from −20V to0V within t f , the S/D junctions become reverse biased andthe depletion region in the channel around junctions needs toextend by emitting trap-related carriers. Later emitted carriersfrom the deep trap state are exposed at high Ex across thedepletion region and gain enough energy to become HCs. Fornormal TFTs, there are only two reversed junctions to sharethe voltage drop, while for BG TFTs, there are a series ofreversed junctions to share the voltage drop. Apparently, Ex atthe S/D drain junctions in BG TFTs would be reduced throughsuch sharing of the field across multiple junctions, resultingin better HC reliability in the second stage. Shown in insetsin Fig. 5 are Ex distributions in the normal TFT (upper) andthe BG TFT (lower) at the end of t f . It can be observed thatthe intensity of Ex in BG TFTs is weakened by the sharing ofthe field across multiple reverse biased junctions. To be clearer,Ex at 10nm below the oxide/channel interface along the source

side to the drain side in the normal TFT (red line) and theBG TFT (blue line) is extracted, as shown in Fig. 5. The peakvalue of Ex at S/D junctions is reduced by 60% via employinga BG structure in the active channel, which explains whyBG TFTs exhibit better HC reliability under dynamic NBS.

IV. CONCLUSION

Degradation behavior and degradation mechanism ofBG TFTs under dynamic NBS are characterized and analyzedfor the first time. It is found that dynamic NBS inducedHC degradation in BG TFTs is greatly reduced, comparedto normal TFTs. The Ex reduction caused by the sharing ofthe field across multiple reverse biased junctions is confirmedto be responsible for such improved dynamic HC reliabilityin BG TFTs. All test results indicate such BG structure thatcould effectively suppress HC effect has great potential forSOP application in the future.

REFERENCES

[1] M. Zhang et al., “A simple method to grow thermal SiO2 interlayerfor high-performance SPC poly-Si TFTs using Al2O3 gate dielectric,”IEEE Electron Device Lett., vol. 35, no. 5, pp. 548–550, May 2014.

[2] M. Zhang et al., “Characterization of DC-stress-induced degrada-tion in bridged-grain polycrystalline silicon thin-film transistors,”IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3206–3212,Sep. 2014.

[3] M. Zhang et al., “Degradation of metal-induced laterally crystal-lized n-type polycrystalline silicon thin-film transistors under synchro-nized voltage stress,” IEEE Trans. Electron Devices, vol. 56, no. 11,pp. 2726–2732, Nov. 2009.

[4] Y.-H. Tai, S.-C. Huang, and P.-T. Chen, “Degradation mechanismof poly-Si TFTs dynamically operated in OFF region,”IEEE Electron Device Lett., vol. 30, no. 3, pp. 231–233,Mar. 2009.

[5] Y.-H. Tai, S.-C. Huang, and C.-K. Chen, “Analysis of poly-Si TFT degra-dation under gate pulse stress using the slicing model,” IEEE ElectronDevice Lett., vol. 27, no. 12, pp. 981–983, Dec. 2006.

[6] C.-F. Huang et al., “Dynamic bias instability of p-channelpolycrystalline-silicon thin-film transistors induced by impactionization,” IEEE Electron Device Lett., vol. 30, no. 4,pp. 368–370, Apr. 2009.

[7] K. M. Chang et al., “Enhanced degradation in polycrystallinesilicon thin-film transistors under dynamic hot-carrier stress,”IEEE Electron Device Lett., vol. 22, no. 10, pp. 475–477,Oct. 2001.

[8] Y. Uraoka et al., “Hot carrier effects in low-temperature polysilicon thin-film transistors,” Jpn. J. Appl. Phys., vol. 40, no. 4S, pp. 2833–2836,2001.

[9] S. Zhao et al., “Bridged-grain polycrystalline silicon thin-film transis-tors,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 1965–1970,Jun. 2013.

[10] W. Zhou et al., “Bridged-grain solid-phase-crystallized polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett., vol. 33, no. 10,pp. 1414–1416, Oct. 2012.

[11] M. Zhang et al., “High-performance polycrystalline silicon thin-filmtransistors integrating sputtered aluminum-oxide gate dielectric withbridged-grain active channel,” Semicond. Sci. Technol., vol. 28, no. 11,p. 115003, 2013.

[12] J. Zhou, M. Wang, and M. Wong, “Two-stage degradation of p-channelpoly-Si thin-film transistors under dynamic negative bias temperaturestress,” IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3034–3041,Sep. 2011.

[13] M. Zhang et al., “Analysis of degradation mechanisms in low-temperature polycrystalline silicon thin-film transistors under dynamicdrain stress,” IEEE Trans. Electron Devices, vol. 59, no. 6,pp. 1730–1737, Jun. 2012.

[14] D. Zhang, M. Wang, and M. Wong, “Two-stage degradation of p-typepolycrystalline silicon thin-film transistors under dynamic positive biastemperature stress,” IEEE Trans. Electron Devices, vol. 61, no. 11,pp. 3751–3756, Nov. 2014.


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