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Digital Etching for Highly Reproducible Low Damage Gate Recessing on AlGaN/GaN HEMTs

D. Buttari, S. Heikman, S. Keller, and U. K. Mishra Department of Electrical and Computer Engineering

University of California, Santa Barbara, California 93106, U.S.A.

Abstract

A room temperature digital etching technique for aluminum gallium nitride has been de- veloped. An oxidizing agent and an acid have been used in a two step etching cycle to remove aluminum gallium nitride in approximately 5-6 8, increments. The process has been charac- terized to be reasonably linear and highly repeatable, offering an alternative to currently not available gate recess etch stopper technologies. Recessed gate Alo.yjGao.ssN/GaN HEMTs on sapphire were compared to un-recessed devices realized on the same sample. A fivefold gate leakage decrease and negligible variations on breakdown voltage support digital recess- ing as a viable solution for highly reproducib€e low surface-damage gate recessed structures.

I. INTRODUCTION Recessed gate geometries, in which the gate metal is placed slightly below the original epilayer surface, are conventionally achieved on 111-V semiconductors using either wet or dry etching. The improvements in terms of breakdown, transconductance, and linearity due to the recessed geometry are balanced by an increase in gate leakage (due to etch damage) and by a decrease in threshold voltage uniformity (due non-reproducible etch depth). The last two drawbacks have to be properly considered when comparing different etch techniques. Conventional wet recess etching is a low damage technique characterized by poor wafer uniformity and poor run to run reproducibility. Dry recess etching has been shown to be more reproducible, particularly when used with an etch stop layer, but at the same time more prone to damage. Both dry El], [2 ] , [3], [4], [5], [6], [7] and wet [8] etch techniques have been demonstrated to be feasible for gate recess etching on AlGaN/GaN HEMTs, but no etch stop for high aluminum content AlGaN has so far been reported, possibly leading to poor run to run threshold voltage uniformities [6]. Surface damage, poor reproducibility, and high variability in AlGaN:GaN selectivity are at present the three main shortcomings of dry etching on GaN. In the present study the accuracy and repeatability of a different, potentially low-damage, digital etching technique for gate recessing on AlGaN/GaN HEMTs has been analyzed. The resolution and reproducibility of the technique have been characterized to be in the 6 8, range, challenging the accuracy achievable by an etch stopper technology.

Digital recess etching was first suggested on GaAs by Bozada et al. [9]. The idea was to achieve a specified etch depth by consecutive repetitions of a two step process. On the first step the semiconductor epitaxial layer is oxidized by a diffusion limited process (rinse in Hz02) in which the oxidation depth is considerably process independent. On the second step the so formed oxide is selectively removed, with negligible effect on the underlying un-oxidized material. In the present study the technique has been successfully transferred to AlGaN/GaN HEMTs, the oxidation step being achieved by exposure to a low power oxygen plasma descum. The following results have been achieved: (a) reasonably linear,

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Fig. 1. Measured oxide thickness as function of oxygen plasma exposure time. The substrate was n-type, phosphorus doped, silicon single-crystal with an (1 11) oriented cleaved surface. The oxygen plasma was generated by a Technics Planar Etch PELIA Plasma System. RF excitation was applied at the electrode at a frequency of 30 IrHz. Oxide thicknesses were measured by a Rudolph Research AutoEL 111 ellipsometer. Oxide thicknesses were deduced assuming an index of refraction for silicon dioxide of 1.45. An error of f0.05 on index of refraction will induce an error of ~ 6 % on oxide thickness in the present oxide thickness range.

accurate, and extremely reproducible gate recess depths were determined by atomic force microscopy (AFM) as function of number of digital recess cycles, even for very shallow etches (less than 50 A); (b) decreased gate leakage and unaffected bee-terminal off state destructive breakdown were experienced for recessed devices compared to un-recessed ones, attesting the low surface-damage profile of the

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Fig. 2. Left. Measured etch depths as function of digital etch cycles for different oxygen plasma powers. Plasma power was progressively decreased from 50W to 1OW at 1OW increments. Three digital etch cycles were cumulatively performed for each plasma power. Etch depths were measured by atomic force microscopy (AFM) and averaged on 6 measurements. Averaged etch depths after 3, 6, 9, 12, and 15 etch cycles were 21.7, 40.8, 57.3, 72.2, and 83.2A. Corresponding standard deviations were 1.5,4.3,2.8,4.0, and 3.1 A. - Right. Measured etch depths as function of digital etch cycles for different hydrochloric acid concentrations. HCI:DI oxide removal solution was progressively diluted from 1:l to 1:31. Three digital etch cycles were cumulatively performed for each solution. Plasma power was 20W. Etch depths were measured by atomic force microscopy (AFM) and averaged on 6 measurements. Averaged etch depths after 3, 6, 9, 12, and 15 etch cycles were 15.6,29.7,43.5,59.4, and 74.1A, respectively. Corresponding standard deviations were 1.0,2.0, 1.1,2.7, and 2.1 A.

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technique; (c) no etch selectivity between GaN and AlGaN was detected for oxygen plasma powers in the 20-50 W range.

11. PROCESS CHARACTERIZATION The diffusion limited nature of the oxygen plasma oxidation was verified by ellipsometric techniques

on silicon samples. We used n-type, phosphorus doped, Si single-crystals with an (1 11) oriented cleaved surface. The natural oxide was removed by a dip in HF (49%) for 1 min. Initial oxide thicknesses were in the 13.1 - 19.4 8, range. Different samples were cumulative oxidized at 20, 50, and 100 W oxygen plasma powers, corresponding to 0.027, 0.069, and 0.137 W C ~ - ~ power densities (12 inch diameter plate electrode). The samples were cumulatively exposed to the plasma for 7.5, 15, 30, 60, 120, and 240 s (Fig. 1). System pressure was 300 mTorr. The oxygen plasma was generated by a Technics Planar Etch PEIIA Plasma System. RF excitation was applied at the electrode at a frequency of 30kHz. After each oxidation step oxide thicknesses were measured by a Rudolph Research AutoEL III ellipsometer. The angle of incidence was q~ = 70° and the wavelength used was d = 632.8nm (He-Ne laser). Oxide thicknesses were deduced assuming an index of refraction for silicon dioxide of 1.45. Average natural oxide thickness after HF treatment was 16.98,with a standard deviation of 1.5& as measured on 4 different samples averaging 6 times each measurement. Oxide thickness after the whole experiment on an untreated sample kept at room atmosphere was 19.5 A, with a standard deviation on 6 measurements of 1.6 A. The dependence of film thickness on time was strictly logarithmic in the tested time frame. The pre-exponential period of oxidation [ 101 was shorter than 7.5 s . Growth rates at 20,50, and 100 W were 15.1, 16.7, and 18.5 .@decade. The logarithmic dependence of oxide thickness on oxidation time is representative of a self-limiting process. A self-limiting thickness is significant for digital etching because it results in an effective etch depth that is not proportional to time, but is essentially constant over a reasonably large time frame. The dependence of oxide thickness on oxidation plasma power was instead roughly linear, with a possible negative impact on digital etch repeatibility.

The effect of different plasma powers on A10.35Gao65N digital etch rate is shown in Fig. 2 (left). Tests were performed on a sample grown by metal organic chemical vapor deposition (MOCVD) on a c-plane

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Fig. 3. Left. Etch selectivity between GaN and A I O . ~ ~ G ~ O & I for digital recesses performed at oxygen plasma powers between 20 and 50W. - Right. Etch selectivity between GaN and Al0.35GW.65N for low power chlorine RIE etches. Etch depths were measured by atomic force microscopy ( A F M ) on top and bottom of lithographically defined mesas (corresponding to A10.35Gw.65N and GaN material, respectively). GaN etch depth (rate) was found to be relatively repeatable, with an average of 249 A (1.24 us) and standard deviation of 13 A (0.06 k s ) . AlGaN etch rate was more variable, with an average of 94.6 8, (0.47 us) and standard deviation of 37.1 8, (0.18 k s ) . AIGaN:GaN etch ratio varied between 0.54 1 and 0.241.

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sapphire substrate. The epilayer consisted of a semi-insulating GaN buffer, a 5 8, AlN dipole barrier [ 113, and a 290 8, silicon doped &.&a0.65N layer. Estimated etch rates were roughly linear in power, varying from 3.67 &cycle for the 10 W plasma oxidation to 7.22 &cycle for the 50 W plasma oxidation. No etch selectivity between AlGaN and GaN was ever detected on multiple tests at plasma powers in the 20-50W range (Fig. 3 left). A selective character was instead found for low power chlorine (Clz) dry etching [6] (15 W input power, -1V DC voltage, 10 sccm C12 flow, 10 mTorr pressure, 200 s exposure time), with highly variable selectivity from run to run (Fig. 3 right).

The so formed oxide was removed by a solution of HC1:DI. The samples were rinsed in the solution for 1 min at 25OC. The solution was constantly mixed by a magnetic stirrer rotating at 160ipm, and it was left covered for most time during the experiment. The independence of etch rate on acid concentration is illustrated on Fig. 2 (right), were the etch rate is constant for HC1:DI ratios between 1:l and 1:31.

The degradation in 2DEG sheet charge density and mobility due to cumulative exposures to oxygen plasma was evaluated by Hall measurements (Fig. 4). Measurements were averaged on 3 different dies, and each measurement was repeated 3 times. No oxide removal was intentionally performed between

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Fig. 4. Top. Degradation in 2DEG sheet charge density due to cumulative exposures to oxygen plasmas at two different power levels (20 and 100 W). Channel degradation increased at the increase in plasma power and oxidation time. No oxide removal was intentionally performed between subsequent oxidations. - Bottom. Degradation in 2DEG electron mobility due to cumulative exposures to oxygen plasmas at different power levels. Channel degradation increased at the increase in plasma power. No oxide removal was intentionally performed between subsequent oxidations.

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subsequent oxidations, leaving the AlGaN barrier thickness unchanged during the experiment. Channel degradation increased at the increase in plasma power and oxidation time. After 4 minutes exposure to lOOW oxygen plasma a degradation of 21% (19%) was detected in channel charge (mobility), compared to 6% (1%) in the case of 20W exposure. At 20W plasma power, 16 minutes exposure, a reduction of 12% (9%) was detected in channel charge (mobility).

111. DEVICE FABRICATION Devices were fabricated on a sample grown by metal organic chemical vapor deposition (MOCVD) on

a c-plane sapphire substrate. The epilayer consisted of a semi-insulating GaN buffer, a 5 %, AlN dipole barrier [ 111, and a 290 8, silicon doped &.35Ga065N layer. On the wafer, HEMTs were fabricated through Ti/AVNi/Au ohmic metal evaporation, mesa isolation, and Ni/Au/Ni gate definition. A13 layers were defined by i-line stepper lithography. Ti/AI/Ni/Au (200 k1500 U375 k500 8,) ohmic contacts were deposited by e-beam, and annealed at 87OOC for 30 s in forming gas. Mesa isolation was obtained by reactive ion etching (RE). Plasma conditions were 100 W power, 5 mTorr pressure, and 10 sccm Clz flow rate, corresponding to an etch rate of about lO&s. The mesa etch depth was about 12008,. After gate lithography, and before gate metal evaporation, a self aligned gate recess was achieved by a digital etching technique. As already explained, an oxidizing agent and an acid were used in a two step etching cycle to remove the aluminum gallium nitride in approximately 6 8, limited increments. In the first step of the cycle the AlGaN surface layer was oxidized by a low power oxygen plasma descum (20 - 50 W power, 300 mTorr oxygen pressure, 30 s exposure). In the second step of the cycle the oxide was removed by a rinse in HC1:DI (1: 1 - 1 : 15) for 1 min at 25 OC. These steps were repeated to reach the desired etch depth. After completion of the gate recess etch step the gate metal (Ni/Au/Ni) was deposited by e-beam evaporation (300A/2000A/500A) . Devices adopted a 2 finger T-layout configuration with a nominal gate length of 0.7pm and a gate width of 150pm. The spacing between gate and drain was 2.Opm and gate-source spacing was 0.7pm. Recessed and un-recessed devices were obtained on the same sample.

Iv. MEASUREMENTS AND RESULTS Etch depths were measured by atomic force microscopy (AFM) after 0,2,4, 8, 12, and 16 etch cycles (Fig. 5) at a plasma power of 50 W. The oxide removal solution was HC1:DI (1: 1). Increasing the number of digital etch cycles produced larger etch depths, but the etch rate as calculated by:

Measured etch depth Number of digital etch cycles

Digital etch rate(%,/cycle) =

remained relatively constant. Depth data were collected on 3 different dies for each number of digital etch cycles. For each measurement both the downward and upward trench edges were measured and averaged. Average etch depths after 2, 4, 8, 12, and 16 etch cycles were 14.0, 23.0, 51.9, 75.9, and 97.0& corresponding to digital etch rates of 7.0, 5.7, 6.5, 6.3, and 6.0kcycle. Standard etch depth deviations were 1.2, 2.7, 3.3, 0.7, and 4.58,, respectively. Average etch depth after lithography, but before any digital etching was 1.7 A, with a standard deviation of 1.4 A. While the 2,4, 8, and 12 etch cycles were cumulatively reached by progressively covering portions of the sample, the 16 etch cycle was achieved in a separate run. The high linearity of etch depth vs number of etch cycles supports the repeatability and accuracy of the method. A possible slight decrease in etch rate at the increase in the number of etch cycles is apparent from Fig. 5. The decrease could be due to the incomplete effectiveness

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0 2 4 6 0 10 12 14 16 NUMBER OF ETCH CYCLES

Fig. 5. Measured etch depths as function of digital etch cycles. Oxygen plasma conditions were: 50 W power, 300mTorr pressure, 30 s exposure. Acid rinse was performed in HC1:DI (1: 1) for 1 min at 25OC. Etch depths were measured by atomic force microscopy (AFM) and averaged on 6 measurements. Averaged etch depths after 2, 4, 8, 12, and 16 etch cycles were 14.0,23.0,51.9,75.9, and 97.0A. Corresponding standard deviations were 1.2,2.7,3.3,0.7,4.5 R. Average etch depth after lithography, and before any digital etching was 1.7 A, with a standard deviation equal to 1.4A.

of hydrochloric acid in removing oxidation byproducts like aluminum oxide. Gate lengths as measured by AFM after 2, 4, 8, 12, and 16 digital recess cycles were 0.71, 0.70, 0.83, 0.87, and 0.85 ym. The slight enlargement in gate length at the increase in number of digital etch cycles was related to the action of oxygen plasma and hydrochloric acid on Shipley MEGAPOSITTMSPRTM950 photoresist. No dependence of recess depth on feature dimensions was detected in the 0.65 - 5.Oym gate length range.

The digital nature of the process was verified by comparing the etch depth obtained after 16 cycles of (a) 30 s oxygen plasma descum (50W); (b) 1 min rinse in HC1:DI (1: 1) to the one obtained by a single cumulative cycle characterized by an 8 min oxygen plasma exposure (30 s x 16) followed by a 16 min HC1:DI rinse (1 min x 16). Averaged etch depths as measured on 3 dies were 97 8, for multiple cycles and 12 A for the single cumulative cycle. Corresponding standard deviation were 4.5 and 0.89 A. The approximate oxide growth rate deduced by these data was 4.9 &decade.

Devices were realized for the 16 digital etch cycle recesses and the results were compared to nearby un- recessed devices (= 400ym apart). An increase in extrinsic transconductance and a positive threshold shift were observed as a consequence of the recess etch (Fig. 6). Threshold voltage shifted from -6V for un-recessed devices to -2SV for the recessed ones, and extrinsic transconductance, measured at a drain bias of 4V, increased from about 220 to 250 mS/mm. Despite the source-drain saturation current (Idss) was reduced from 1.0 to 0.45 Nmm due to the recess etch (Fig. 6 left), the maximum source-drain current, (hmax), measured at a forward gate bias current of 1 mA/mm, remained almost unchanged, decreasing only slightly from 1.2 to l.lA/mm [7]. The two terminal gate-drain leakage, measured at a gate-drain voltage of 1OV with the source floating, averagely decreased from about 4 pNmm to 0.8 yA/mm. Standard deviations, collected from measurements on 10 devices, were 0.62 pA/mm and 0.091 pNmm, respectively. The destructive three-terminal breakdown voltage was between 40V and 60V for both etched and un-etched devices. Hall measurement data performed before and after 10 digital etch cycles revealed a drop in charge from 1.48 x 1013cm-2 to 1.13 x 1013cm-2 due to thinning of the AlGaN barrier, and a slight drop in mobility from 1620cm2/Vs to 1320cm2/Vs.

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In an attempt to minimize 2DEG degradation multiple oxidations were performed at a lower power level of 20 W. After each oxidation the sample was rinsed in HC1:DI (1: 15) for 1 min at 25OC. 26 cycles were performed (Fig. 7 right). The expected etch depth as extrapolated from Fig. 2 (right) was 128 A. The experimental one was 103.8 A, with a standard deviation of 5.5 A. The error in etch depth could be due to a reduction in etch rate at the increase in the number of digital etch cycles, as mentioned above. Hall measurements performed before and after the digital etch process revealed a drop in charge from 1.43 x 10'3crn-2 to 0.79 x 10'3cm-2, and a drop in mobility from 1590cm2/Vs to 708cm2/Vs. Standard deviations in charge and mobility were 0.93 x 10" cm-2, 6.17 x 10" cm-2 and 10.2cm2/Vs, 92.6cm2/Vs, respectively. The causes of the unexpected channel degradation are currently under study. No recovery in channel performance was obtained by rapid thermal anneal in nitrogen atmosphere for temperatures in the 400 - 800OC range (1 min anneals). A recovery in channel performance after anneal has been previously reported in the case of high frequency (13.56MHz), medium power, R E oxygen plasma exposures [ 121.

AFM scans of the etched AlGaN surface revealed no appreciable degradation in surface morphology. The associated RMS roughness measured on multiple 0.5 ym x 0.5 ym windows was 1.9 A, compared to a typical as grown surface roughness of 1.88,. The apparent surface roughness measured on a 2.0pm x 2.Oym window increased from 2.5 8, to 6.9 A, due to enlargement of surface dislocations consequent to isotropic etching. Gate leakage, measured in a two terminal configuration, at a gate- drain voltage of 1OV with the source floating, averagely decreased from 0.01 mA/mm to 0.003 rnA/mm. Standard deviations were 0.002 and 0.001 W m m , respectively.

A comparison with standard low power chlorine etches was performed. Etch conditions for the C12 re- active ion etches were: 15 W input power, w1V DC voltage, 10 sccm Cl2 flow, 10 mTorr pressure, 200 s exposure time (corresponding to an etch depth of w 130 A). A clear degradation in surface quality was detected in this case. RMS surface roughness increased from 1.9 to 9.0A, independent of windows size in the 0.5 - 2.0pm range. Surface morphology showed an AVGa droplet-like structure, which could

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Fig. 6. Left. h - Vd characteristics for digitally recessed and un-recessed devices as measured on 75pm gate width tran- sistors. Gate-source voltage was varied between +4V and -6V. Dashed lines correspond to un-recessed conditions and open-circles refer to 97 A recesses (SOW oxygen plasma power). Threshold voltage shifted from -6V for un-recessed devices to -2.SV for the recessed ones. - Right. Transconductance characteristics for digitally recessed and un-recessed devices as measured on 7Spm gate width transistors. Gate-source voltage was varied between -lOV and 5V. Drain voltage was 4V. Dashed lines correspond to un-recessed conditions and open-circles refer to 97 A recesses. Original &.35G~.aN banier thickness was 290A. Threshold voltage shifted from -6V for un-recessed devices to -2.5V for the recessed ones. Extrinsic transconductance increased from about 220 to 250 mS/mm.

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Fig. 7. Left. Transconductance characteristics for chlorine recessed and un-recessed devices as measured on 75pm gate width transistors. Gate-source voltage was varied between -lOV and 4V. Drain voltage was 4V. Dashed lines correspond to un-recessed conditions and open-circles refer to 128 8, recesses (20W oxygen plasma power). Original 4 . 3 5 G a , - ~ ~ N barrier thickness was 290A. Threshold voltage shifted from -6V for un-recessed devices to -3.5V for the recessed ones. Extrinsic transconductance increased from about 220 to 300 mS/mm. - Right. Transconductance characteristics for digitally recessed and un-recessed devices as measured on 75pm gate width transistors. Gate-source voltage was varied between -lOV and 4V. Drain voltage was 4V. Dashed lines correspond to un-recessed conditions and open-circles refer to 104 A recesses (20W oxygen plasma power). Original &.3&%.65N barrier thickness was 2908,. Threshold voltage shifted from -6V for un- recessed devices to -2.5V for the recessed ones. Extrinsic transconductance increased from about 220 to 250 mS/mm.

be attributed to preferential removal of nitrogen [13]. The degraded surface morphology could jus@ the average increase in gate leakage from 0.01 mA/mm to 0.95 mA/mm for unrecessed and Cl2 recessed structures. Standard deviations were 0.002 and 0.13 d m m . Surface degradation had negligible conse- quences on active channel performances. Hall data revealed an increase in mobility from 1607cm2/Vs (standard deviation: 23.3 cm2/Vs) to 1668 cm2/Vs (standard deviation: 3 1.7 cm2/Vs). Channel charge density decreased from 1.44 x 10'3cm-2 (standard deviation: 8.8 x 1010cm-2) to 1.28 x 1013cm-2 (standard deviation: 6.7 x 10" cmP2). The decrease in channel charge was qualitatively compatible to thinning of the AlGaN barrier (from -290 A to -160 A), and the increase in electron mobility testifies the low damage profile of low power Cl2 plasma etch techniques on active channel (Fig. 7 left).

v. DISCUSSION AND CONCLUSIONS Previous reports of digital recess etching on GaAs-based FETs suggested the feasibility of the tech-

nique for highly reproducible low damage gate recesses on m-V semiconductors [9]. The present study confirms the potential of the technique even in the case of AlGaN/GaN HEMTs. Extremely controllable etch depths were achieved by successive surface oxidations and oxide removal etches. The reduction in gate leakage, the invariability in breakdown voltage, and the promising reproducibility and control in gate recess depth support digital etching as a viable tool for reproducible processing of gate recessed structures. Nevertheless a reduction in channel degradation and a simplification of the oxidation process have to be achieved in order to render the technique attractive. Since the process does not intrinsically require the action of a plasma but only the availability of an oxidizing agent of any kind, it is expected that the process could be slightly modified to be completely damage free. Such a modification should not affect the results on accuracy and reproducibility presented in this work.

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[2] 0. Breitschadel, B. Kuhn, F. Scholz, H. Schweizer, “Minimization of leakage cumnt of recessed gate AlGahVGaN HEMTs by optimizing the dry-etching process,” Journal of Electronic Materials, Vo1.28. No.12, IEEE, pp. 1420-1423, Dec 1999.

[3] C.-H. Chen, S. Keller, E. D. Haberer, L. Zhang, S. P. DenBaars, E. L. Hu, U. K. Mishra, Y. Wu, “Cl2 reuctive wn etching for gate recessing of AlGuh!/GMfik&effect transistor;” J. Vac. Sci. Technol. B, 17(6), pp. 2755-2758, N o v m 1999.

[4] T. Egawa, G.-Y. Zhao. H. Ishikawa, M. Umeno, and T. Jimbo, “Churucterimtion of Recessed gate A l G a “ HEMTs on Sapphire,” IEEE Transactions on Electron Devices, Vol. 48, No. 3, pp. 603-607, March 2001.

[5] Y. Sano, T. Yamada, J. Mita, K. Kaifu, H. Ishikawa, T. Egawa, M. Umeno, “High performance AlGoN/GuN HEMTs with recessed gate on sapphire substrare”, Device Research Conference, Conference Digest, IEEE, p.81,2001.

161 D. Buttari, A. Chini, G. Meneghesso, E. Zanoni, P. Chavarkar, R. Coffie, N.Q. Zhang, S. Heikinan, L. Shen. H. Xing, C. Zheng, U.K. Mishra, “Systematic churucterization of C12 reuctive ion etching for gate recessing in AlGaN/GaN HEMTs,” IEEE Electron Device Letters, vo1.23, (no.3). IEEE, pp. 118-120. March 2002.

[7] J. S. Moon, W. S. Wong, J. Duvall, M. Micovic, G. Peng, M. Antcliffe, P. Hashimoto, L. McCray, “Highperformume recessed gate A l G a ” HEMTs” IEEE Int. Symp. Compound Semiconductors, ISCS 2001, Tokyo, p. 177, October 2001.

[8] J.-S. Lee, J.-W. Kim, D.-C. Jung, C.4. Kim, W.4. Lee, J.-H. Lee, J.-H. Shin, M.-W. Shin, J.-E. Oh, J.-H. Lee. “Photo- electrochemical gate recess etching for the fabricution of AlGaN/GaNheterostructurefieM effect transistoc” Jpn. J. Appl. Phys. Part 2 (Letters), vo1.40, (no.%), pp. L198-200, 1 March 2001.

[9] C. A. Bozada, G. C. DeSalvo, J. L. Ebel, C. L.A. Cerny, R. W. Dettmer, J. K. Gillespie, C. K. Havasy, T. J. Jenkins, K. Nakano, C. I. Pettiford, T. K. Quach, J. S. Sewell, G. D. Via, “Digital wet etching of semiconductor materials,” United States Patent (6,004.881), Dec. 21, 1999.

[IO] R. J. Archer, “Optical Measurements of Film Growth on Silicon and Germanium Surfaces in Room Air”, Journal of the Electrochemical Society, pp. 619-622, Oct. 1957.

[ll] L. Shen, S. Heikman. B. Moran, R. Coffie, N.-Q. Zhang, D. Buttari, I. P. Smorchkova, S. Keller, S. P. DenBaars, U. K. Mishra, “AlGd/AlN/GaN high-power microwave HEMT”. IEEE Electron Device Letters, v01.22. (no.10). IEEE, pp. 457-459. Oct. 2001.

[12] R. Dimitrov, V. Tilak. W. Yeo, B. Green, H. Kim, J. Snmt, E. Chumbes, J. R. Shealy, W. S c M , L. E Eastman, C. Miskys, 0. Ambacher, M. Stutunann, “Injuence of oxygen and methane plusma on the electrical properties of urrdoped AIGaN/GaN heterostructures for high power transistors”, Solid State Electronics, Vo1.44, pp. 1361-1365,2OOO.

[13] Ji-Myon Lee, Ki-Myung Chang, Seong-Ju Park, Hong-Kyu Jang, “Incuctively Coupled C12/Ar/@ Plawnu Etching of GUN, InGuN, and AlGuN”, Journal of the Korean Physical Society, Vo1.37. No.6, pp. 842-845, December 2OOO.

State Electronics, VO1.41, No.2, pp. 247-250.1997.

ACKNOWLEDGMENT The authors would like to thank ONR IMPACT MURT, ONR CANE MURT, and AFOSR programs

for support. This work made use of MIU Facilities supported by National Science Foundation under award No. DMR96-32716.

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