Multiplier-less Digital Down Converter in 90nm CMOS Technology Saiyu Ren, Steven Billman and Ray Siferd

Department of Electrical Engineering, Wright State University Dayton, OH 45435

Email: {saiyu.ren, billman.3}@wright.edu Abstract—A Digital Down Converter (DDC) is presented based on square wave local oscillators facilitating a multiplier-less implementation with no constraints on the sampling frequency. The DDC includes a pseudo multi-rate SINC low pass filter which exhibits better performance compared to the standard multi-stage sinc filter. The pseudo multi-rate SINC filter can be implemented with a unique cascaded integrator comb (CIC) filter to obtain the same improved performance. A 90nm CMOS design with 8 bit inputs clocked at 400MHz demonstrates a flexible, very low power/size DDC architecture for single chip digital receiver applications.

I. INTRODUCTION A digital down converter (DDC) typically receives a

digital input that has been generated by an analog to digital converter (ADC) operating at intermediate frequency (IF) in an RF receiver chain. The function of the DDC is to down convert the IF signal to baseband in phase (I) and quadrature (Q) signals as shown in the block diagram in Fig. 1 [1,2,3,4,5]. This is accomplished by multiplying the incoming IF signal centered at fIF by in phase and quadrature sinusoid oscillator signals with frequency equal to fIF. The outputs of the complex multiplier are I and Q signals centered at DC and at 2fIF. The DDC includes low pass filters in the I and Q output paths to reject the signal centered at 2fIF and pass the signal centered at DC with the desired bandwidth.

There are numerous applications for DDCs including software radios, smart antennas, cellular base stations, channelized receivers, and spectrum analysis [1,2,3,4]. Sophisticated single chip DDC implementations are available which include complex signal synthesizers to generate the I and Q local oscillator (LO) signals in continuous wave (CW), frequency hopped, and chirped formats [3,4]. These commercially available chips provide the flexibility and processing power to meet a variety of applications; however, they are not suited for embedding in single chip solutions

SIN

ADC

Complex SinusoidGenerator

High DecimationFilter

High DecimationFilter

Low Pass FIR Filter

Low Pass FIR Filter

COS

I

Q

IF

Figure 1. Typical Digital Down Converter

such as single chip software receiver or in an integrated single chip multichannel smart antenna receiver. This paper presents a very low power area efficient CMOS DDC that is intended for applications where the ADC and the DDC are integrated with receiver chain digital processing hardware on a single chip. This paper details the design of a multiplier-less digital mixer with no constraints on the sampling frequency fs. Previous implementations of multiplier-less digital mixers require the mixer sampling frequency to be set at 4fIF so the LO sinusoidal inputs have values of 1,0,-1,0 for each cycle [2]. The sampling frequency for this implementation can be set to any value up to the maximum sampling frequency of the ADC which provides flexibility for meeting bandwidth and filtering requirements for various embedded applications. The design also includes a unique pseudo multi-rate SINC filter that has better performance than the standard cascaded multi-stage SINC filter [5]. A unique cascaded integrator comb (CIC) filter design is described which gives the same improved performance compared to the standard CIC filter design or the FIR SINC filter design.

II. DIGITAL DOWN CONVERTER ARCHITECTURE AND MATLAB RESULTS

The block diagram of the multiplier-less DDC architecture is shown in Fig. 2. As can be seen, the LO sinusoidal generator is replaced by a square wave generator. If the LO is a sine wave signal, then restricting the sampling frequency to be 4fIF results in a cycle of the I and Q LO signals being represented by 1,0,-1,0 and 0,1,0,-1 respectively. If higher sampling frequencies are desired, the

ADC

Multi-stage LPF

Clock BasebandI

BasebandQ

Digitalmixer

Digitalmixer

Multi-stage LPF

SquareWave LO

90°phaseshift

Clock

Clock

Clock

Multiplierless DDC

FIRCompensation

Filter

FIRCompensation

FilterReceiverDigital

Processing

On Chip Digital Processing

IF

Figure 2. Single Chip Digital Receiver with Multiplier-less DDC

978-1-4577-1041-4/11/$26.00 ©2011 IEEE 316

values of the I and Q LO signals must be generated with a sinusoidal synthesizer to produce the required values at the sample times and the digital mixer must execute complex multiplies. For this implementation, the LO signals are square waves, so if the sampling frequency is 4fIF, then one cycle of the I and Q LO signals are represented by 1,1,0,0 and 1,0,0,1 respectively. If it is desired to have a sampling frequency equal to 16fIF, then one cycle of the I and Q LO signals are represented by 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, 0 and 1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1. Thus, the sampling frequency of the DDC can be increased relative to the IF frequency while performing the digital mixer operation with only adds and subtracts.

A. Mixer Output Spectrum for Square Wave LO For the square wave LO, the digital mixer multiplication

is performed by adds and subtracts even for the higher sampling rates. The pure sine wave LO results in the digital mixer outputs having only the sum and difference frequency components centered at fIF-fLO and fIF+fLO, with an information bandwidth equal to the fbw. For the square wave LO, the output of the digital mixer will have frequency components centered at fLO-fIF, fLO+fIF, 3fLO-fIF, 3fLO+fIF, 5fLO-fIF, 5fLO+fIF, …, due to the harmonics of the square wave at 3fLO, 5fLO, … So if fIF = fLO, then for the sine wave LO, the digital mixer output is the desired baseband signal centered at DC and the sum component centered at 2fIF, while for the square wave LO, the digital mixer output signals are centered at baseband DC, 2fIF, 4fIF, 6fIF, …, with the baseband signal bandwidth of fbw.

As an example, a specific implementation for a smart antenna requires fIF=25MHz with a signal bandwidth of +/-12MHz (24MHz). With a square wave LO, we would expect to see the digital outputs centered at DC, 50MHz, 100MHz, 150MHz, … with bandwidths of +/- 12MHz. If we give an IF input of 25MHz+12MHz=37MHz we can expect a spectrum with outputs at 12MHz, 38MHz, 62MHz, 88MHz, 112MHz, … with the baseband signal at 12MHz. The 37MHz IF input results in the undesired harmonic having the lowest frequency of 38MHz, so the stop band frequency for the low pass filter design is set at 38MHz for this example. The pass band frequency is set at 12MHz to give the desired bandwidth of 24MHz centered at DC. For this application, the sampling frequency is set at 16fIF; however, with the square wave oscillator, the sampling frequency can set to any value up to the maximum frequency of the ADC. As will be discussed below, if the sampling frequency is constrained to 4fIF, then the desired stop band frequency of 38MHz can not be met with the use of multiplier-less CIC or FIR SINC filters.

B. Pseudo-Multi-rate SINC Low Pass Filter For this implementation, we need a LPF with pass band of

12MHz and stop band at 38MHz with stop band attenuation of at least 60dB. The low pass filter is typically implemented with a cascaded integrator comb (CIC) filter or cascaded FIR SINC averaging filter [3]. A four stage CIC filter and four stage FIR averaging filter are shown in Fig 3 and Fig. 4.

Figure 3. Four Stage Cascaded Integrator Comb (CIC) Filter

Figure 4 Four Stage FIR SINC Averaging Filter

The transfer function for both filters is given by

∑ . (1)

The filters in Fig. 3 and Fig. 4 have N=4 and D=10. The CIC filter shown does not decimate the sampling frequency after the integrator stages on top and prior to the comb stages on the bottom since the application required no decimation. The CIC filter can be implemented with a decimation of fs/D for the combs. The magnitude of the frequency response for both filters is given by

| | . (2)

Both filters have nulls at each multiple of fs/D. For our implementation example, we desire a stop band frequency of 38MHz, so with a sampling frequency of 400MHz, we could implement a filter with D=10 to give a first null at 40MHz. With N=4, then the frequency response that is obtained is shown in Fig. 5. If the sampling frequency was constrained to 4fIF (100MHz), the filters would have nulls at 100MHz/D, which does not permit a stop band frequency of 38MHz.

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5dB down at12MHz

Figure 5. Frequency Response for CIC or FIR SINC Filter (D=10 and N=4)

It is noted that the stop band attenuation does not reach the desired 60dB for this case (e.g. 50MHz). The response can be improved by implementing a pseudo multi-rate CIC or FIR averaging filter with four cascaded sections with D1=10, D2=9, D3=7, and D4=6. The transfer function is given by

. (3)

The magnitude frequency response is

| | .(4)

Changing the values of D for each comb of the CIC filter or for each stage of the FIR filter changes the null frequencies to fs/D1, fs/D2, fs/D3, and fs/D4, which has the effect of changing the sampling frequency. The frequency response obtained for the modified filters is shown in Fig. 6.

It is seen from Fig. 6 that the desired stop band attenuation of more than 60dB is obtained and also that the linear phase response is maintained in the pass band. It is noted that the droop in the pass band of 12MHz is 3dB for the

3dB down at12MHz

Figure 6. Frequency Response for Pseudo Multi-rate SINC Filter with Four

Cascaded Sections

12MHz

38MHz

Figure 7. Frequency Spectrum of DDC Pseudo Multi-rate CIC or FIR SINC

Filter Output with IF Input at 25MHz+12MHz=37MHz

Pseudo Multi-rate SINC Filter (Fig. 6) compared to 5dB for the standard CIC (Fig. 5) or standard SINC averaging filter with D=10 and N=4. Thus the FIR compensation filter, which would be added for most applications to reduce the pass band droop to the desired value, would be less demanding for the modified filters.

Fig. 7 shows the MATLAB simulation of the multiplier-less DDC with the square wave LO and either the pseudo multi-rate CIC or FIR SINC filter with an IF inputs of 25MHz+12MHz=37MHz. It is noted in Fig. 7 that the worst case baseband input of 12 MHz results in all harmonics being suppressed by at least 60dB. Fig. 7 also shows that the harmonics associated with the square wave LO are located at the frequencies discussed previously (38MHz, 62MHz, 88MHz, 112MHz, …).

III. 90NM CMOS IMPLEMENTATION

A 90nm CMOS implementation of the DDC has been implemented with an 8 bit IF input and 8 bit I and Q outputs to demonstrate performance and assess the size and power. The 8 bit resolution was adequate for the intended application and for demonstration purposes, but higher resolution would be required for many applications. The design parameters are the same as previously discussed with the IF input centered at 25MHz and the sampling frequency set at 400MHz. The pseudo multi-rate FIR SINC filter has four stages as discussed above with D1=10, D2=9, D3=7, and D4=6. The layout of the DDC in 90nm CMOS is shown in Fig. 8. The area is 333.485um x 617.47um and the power consumption is 12.53mW for an 8 bit implementation when clocked at 400 MHz. The 90nm design can be extended to higher resolution inputs and to higher clocking frequencies as required for specific applications.

The layout simulation results for a baseband input of 12MHz (IF input=25MHz+12MHz=37MHz are shown in Fig. 9 and Fig. 10. The weighted sum I and Q outputs of the pseudo multi-rate filter in Fig. 9 are the expected baseband

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12MHz sinusoidal signals. The FFT of the in phase component of the output shown in Fig. 10 indicates the output at 12MHz and the noise floor and spur free dynamic range are consistent with the 8 bit resolution.

8 BitInput

8 Bit inphaseOutput

8 BitQuadrature

Output

Figure 8. Layout of DDC in 90nm CMOS

Figure 9. Baseband Weighted Sum of 8 Bit 12MHz I and Q Outputs of 90nm

CMOS DDC with IF input of 37MHz (25MHz +12MHz)

Figure 10. FFT of Baseband In Phase Output of 90nm CMOS DDC with IF

input of 37MHz (25MHz +12MHz)

IV. CONCLUSION A Digital Down Converter has been presented with square

wave I and Q local oscillators facilitating multiplier-less digital mixers while allowing sampling frequencies that are not constrained to four times the IF frequency. The square wave oscillator implementation allows greater flexibility in choosing IF frequencies and LO frequencies to meet specific application requirements for ADC compatibility, bandwidths, and filter parameters. The square wave oscillator is combined with a pseudo multi-rate CIC or FIR SINC low pass filter to facilitate selectively placing the notch frequencies of the filter stages to obtain improved performance with less hardware than a standard multi-stage CIC or FIR SINC filter implementation. A 90nm CMOS implementation of the DDC with 8 bit inputs and 400MHz sampling frequencies is included. Transient responses and FFT results are consistent with expected performance for the 8 bit implementation. The DDC architecture provides a flexible very low power/area alternative for single chip digital receiver applications.

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Down Converter," Signal Processing, 2008. ICSP 2008. 9th International Conference , pp.498-501, 26-29 Oct. 2008.

[2] M. Kim, and S. Lee, "Design of Dual-Mode Digital Down Converter for WCDMA and cdma2000," ETRI Journal, vol. 26, no. 6, pp.555-559, December 2004.

[3] Analog Devices, “150 MSPS Wideband Digital Down Converter, AD6636”, Data Sheet, 2005.

[4] Texas Instruments, “GC5018 8-Channel Wideband Receiver,” Data Sheet, May 2005.

[5] E. Hogenauer , "An economical class of digital filters for decimation and interpolation," Acoustics, Speech and Signal Processing, IEEE Transactions, vol.29, no.2, pp. 155- 162, April 1981.

[6] R. Jacob Baker, CMOS Mixed-Signal Circuit Design, vol. 2, Wiley-IEEE Press, 2002, pp. 106-.

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