IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015 1709
Direct SMT Interconnections of Large Low-CTEInterposers to Printed Wiring Board
Using Copper Microwire ArraysXian Qin, Pulugurtha Markondeya Raj, Vanessa Smet, and Rao Tummala
Abstract— This paper reports compliant microwire copperarrays, in thin polymer carriers, as an innovative approachfor direct surface mount technology (SMT) attach of largesilicon, glass, and low coefficient of thermal expansion organicinterposers to printed wiring boards (PWBs). The microwirearrays (MWAs) are prefabricated as free-standing ultrathincarriers using standard, low-cost manufacturing processes suchas laser vias and copper electroplating. Such wire array carriersare then assembled in between the interposer and the PWB asa stress-relief interlayer. The MWA interconnections show lowinterconnection stress and strains even without the underfills. Theapproach is extensible to larger interposer sizes (20 mm×20 mm)and finer pitch (400 µm), making it suitable for smart mobilesystems. The parallel wire arrays that form each joint result inlow resistance and inductance, and therefore, do not degradethe electrical performance. The scalability of these structuresallows extendibility to finer pitch and larger interposer sizesfor high-performance applications. The finite-element methodwas used to design the MWAs to meet the thermomechani-cal reliability requirements. Computational models were builtin 2.5-D geometries to study the reliability of 400-µm-pitchinterconnections with a 100-µm-thick, 20 mm × 20 mm siliconinterposer that was SMT-assembled onto an organic PWB. Thewarpage, equivalent plastic strain, and projected fatigue lifeof the MWA interconnections are compared with those of theball grid array interconnections. A unique set of materials andprocesses was used to demonstrate the low-cost fabrication ofthe MWAs. Copper microwires with 15 µm diameter and50 µm height were fabricated on both sides of a 50-µm-thickthermoplastic polymer carrier using dry-film-based photolithog-raphy and bottom-up electrolytic plating. The copper microwireinterconnections were assembled between silicon interposer andFR-4 PWB with SMT-compatible processes. Thermomechanicalreliability of the interconnections was characterized by thermalcycling test from −40 °C to 125 °C. The initial fatigue failure inthe interconnections was identified at 700 cycles, consistent withthe models.
Index Terms— Connectors, electronics packaging, surface-mount technology.
Manuscript received May 18, 2015; revised August 26, 2015; acceptedSeptember 21, 2015. Date of publication October 15, 2015; date of currentversion November 6, 2015. This work was supported in part by the PackagingResearch Center, Georgia Institute of Technology, Atlanta, GA USA, andin part by Qualcomm. Recommended for publication by Associate EditorC. J. Bailey upon evaluation of reviewers’ comments. (Corresponding author:Xian Qin.)
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2015.2482962
I. INTRODUCTION
THE TREND to high I/O densities, performance, andminiaturization at low cost is driving the industry toward
shrinking interposer design rules, similar to back end of line,requiring a new set of packaging technologies. Interposers ofhigh-density wiring with 2–4 μm lithographic dimensions at20–40 μm off-chip interconnection pitches are projected forfuture generation of high-performance, smart mobile, and con-sumer systems. These applications require reduced thickness,short interconnection length, low cost, and direct-assemblyonto system boards without any intermediate packagesin-between. Most of today’s packages are made of organicmaterials. They are widely available, readily processable, andcost efficient, but they are low-temperature materials withlow Tg, resulting in poor dimensional stability at chip andboard assembly temperatures around 260 °C. The dimen-sional instability leads to layer-to-layer via-registration chal-lenges, and thus to low I/O densities. In addition, theyhave poor thermal conductivity, resulting in poor heat dis-sipation. Their chip-to-package coefficient of thermal expan-sion (CTE) mismatch also limits scalability of the inter-connection pitch. To address these limitations of standardorganic substrates, low-CTE organic, silicon, and glass inter-posers or packages are being explored by the industry andGeorgia Tech (GT)-Packaging research center. Silicon andglass interposers are high-temperature materials and thushave excellent dimensional stability and matched CTEwith ICs, thus allowing the formation of ultrahigh I/O den-sity interposers [1]. Organic substrate manufacturers are alsoaddressing this problem of CTE mismatch and dimensionalstability with novel low-CTE polymer composites that alsohave higher glass-transition temperatures (Tg) [2].
These advances in low-CTE interposers, however, poseinterconnection reliability challenges when they are assem-bled directly on a printed wiring board (PWB) using solderjoints, because of the now large mismatch in CTE betweeninterposers (2.7–8 ppm/°C) and PWB (12–18 ppm/°C). Dueto the environmental hazards and the associated restrictions(RoHS, WEEE, J-MOSS, etc.) with the use of lead-basedsolders, lead-free solders have been widely adopted world-wide in the semiconductor industry. Most of these lead-freesolders, however, are known to be less ductile and moreprone to fatigue. When the lead-free interconnections betweenthe low-CTE packages and boards are subjected to power
1710 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015
Fig. 1. (a) Copper MWA in a polymer carrier. (b) MWA as an SMT-compatible solution for reliable board-level interconnections.
or thermal cycling, cyclic shear stresses are created in thesolders, subsequently leading to fatigue failures. This problemis further aggravated with large-body-size interposers, requiredfor multichip integration in memory-intensive high-bandwidthapplications.
CTE-mismatch-related reliability issues have been solvedin the past at the IC-package level with silicon IC-to-organicpackage interconnections by a variety of methods such asby the use of organic underfills. However, underfilling is notan acceptable option for package-to-board interconnections,where reworkability after assembly is required. Current high-density Si interposers use an intermediate organic ball gridarray (BGA) package to address the board-level reliabilitychallenge. This approach creates an additional package leveland additional process steps, increases cost and thickness, anddegrades the electrical performance. Therefore, there is anurgent need to investigate novel methods to address reliabilitychallenges in direct surface mount technology (SMT) attachof low-CTE packages to system boards.
Large low-CTE pin grid array and land grid array packageshave been used by IBM [3] and others to connect very largelow-CTE, glass-ceramic Low temperature cofired ceramicmodules of the same CTE as silicon to the system board.The reliability in this example was accomplished by compliantpins, but not by standard SMT. In research and development,multiple approaches have been reported in the literature,including the use of compliant metal springs or leads. Widearea vertical expansion structures by DiStefano et al. [4] utilizea flexible copper lead, surrounded by a compliant polymer, tointerconnect the die and the substrate, thereby allowing relativemovement between IC and package. The G-Helix compliantinterconnect structure has been reported by GT, where acopper arch was used to achieve large compliance [5]. FlexibleMoCr cantilevers, which can be released from the substrate byintrinsic stresses, are explored as compliant interconnectionsin-between chip and substrate [6]. Other than metal springsor leads, copper pillars are also widely investigated to replacesolders for reliable interconnections at finer pitches [7], [8].
Another approach to address the CTE mismatch is toutilize stress-buffer structures such as polymer layers or airgaps. Reliable interconnections between low-CTE glass inter-posers and PWB by compliant polymer stress-buffer layers
Fig. 2. Top view of the 20 mm × 20 mm interposer.
was reported by the Packaging Research Center at GT [9],where thin polymer layers were used to decouple the stressin BGAs. GT has also reported the sea-of-leads technol-ogy, which utilizes compliant leads on a polymer layer withembedded air gaps to achieve flexible chip-to-substrate inter-connections [10]. Double-solder ball chip-scale wafer-levelpackaging technology has been reported by IZM [11], wherea second array of solder balls are stencil-printed or placedon top of an array of original solder balls, thus increasingtheir compliance. The bottom solder balls are embedded inthe stress compensation layer, laminated onto the die. TheELAStec wafer-level packaging technology has been reportedby Infineon and IZM, which uses printed silicone bumps ascontacts [12].
In this paper, copper microwire arrays (MWAs) are proposedand demonstrated as a low-cost and SMT-compatible approachfor direct SMT attach of large low-CTE interposer, as shownin Fig. 1. A two-step process was developed to assemble thesilicon interposers onto FR-4 PWBs through the MWAs. Thejoints on both the interposer side and the board side weresimultaneously formed during reflow. The reliability of theinterconnections was characterized by thermal cycling testsfrom −40 °C to 125 °C.
II. FINITE-ELEMENT MODELING
A 20 mm × 20 mm silicon interposer, designed for mobileapplications, and directly assembled onto an FR-4 PWBthrough MWA interconnections at 400-μm pitch, was modeledwith ANSYS. A 2.5-D finite-element method (FEM) modelwas built and used to study the detailed structure of theassembly, and to achieve high calculation efficiency. Due tothe half-symmetric nature of the geometry, a 400 μm×10 mmstrip located in the geometrical center was modeled, as shownin Fig. 2. The strip considers 25 unit interconnections, eachwith a dimension of 400 μm×400 μm. The detailed structureof each unit for the initial setup is shown in Figs. 3 and 4.The silicon interposer thickness was assumed to be 100 μm, ascommonly used for 2.5-D and 3-D architectures. The copperwires are held together by a 25-μm-thick polymer carrier, asshown in Fig. 4. On each side of the carrier, the wires are
QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1711
Fig. 3. Cross-sectional view of a single unit.
Fig. 4. Detailed structure of the copper MWA interconnections.
50-μm long, and connected by a 230-μm diameter pad at thetop, before they are soldered onto the interposer and PWB.Compared with directly soldering the wires, the additionalpads provide more contact area and bonding strength, and alsohelp prevent solder wetting onto the copper wires. The padscan be formed by mushroom plating during wires fabrication,without adding additional lithography steps. The wires are10 μm in diameter, and are fully populated at 20 μm pitch inthe 230-μm diameter pad area.
Symmetric boundary conditions were applied at the rightboundary of the strip. The assembly was subjected to a temper-ature drop from a stress-free temperature of 230 °C to 25 °C,emulating the SMT process, followed by three thermal cycles,each from 125 °C to −40 °C. The Von-Mises stress andthe equivalent plastic strain range in each thermal cycle wascalculated to assess the reliability of interconnections. UnifiedAnand’s model was used to describe the viscoplastic behaviorof SAC305 solder [13]. The material properties used for siliconand the FR-4 board are summarized in Table I. Bilinearisotropic hardening model was used for copper (as illustratedin Fig. 5), where the modulus is 121 GPa and the yield stressis 172.4 Mpa.
Based on the fabrication constraints from packagingprocesses, the aspect ratio of the wires was limited to 5 in the
TABLE I
MATERIAL PROPERTIES USED FOR FEM MODELING
Fig. 5. Bilinear isotropic hardening model for copper.
modeling, with 10 μm diameter and 50 μm height on bothsides. Higher aspect ratio of the wires offers greater com-pliance, though they increase the complexity of fabrication.By fabricating the copper wires with aspect ratio of 5 on bothsides of the carrier, a total aspect ratio of 10 is achieved forthe MWA interconnections.
III. FINITE-ELEMENT MODELING—THE EFFECT
OF POLYMER CARRIER
The polymer carrier not only acts as a mechanical holder ofthe copper wire arrays, but also introduces an anchor point andaffects the strain distribution along the wires. The effect of thepolymer carrier’s CTE and modulus on the reliability of MWAinterconnections was studied by finite-element modeling.
Fig. 6 shows how the CTE and modulus of the carrier affectthe maximum nodal strain in both the copper wires and thesolders. The solid lines show the strain in solders, while thedashed lines show the strain in copper wires. In this paper,the dimension of the copper wires and the material proper-ties of other materials were kept constant. The CTE valuesstudied were 20, 40, and 60 ppm/°C, and the modulus valueswere 1, 2, and 3.5 GPa. It can be observed that the strain inthe copper wires reduces with the decrease in the CTE of thecarrier, and the higher the modulus of the carrier, the higherthe reduction rate. Therefore, a stiffer carrier with low-CTEcorresponds to low strain in the copper wires.
1712 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015
Fig. 6. Effect of the mechanical properties of the polymer carrier on thestrain in solder joints.
Fig. 7. Geometry of the BGA model.
As shown by the solid lines, when the modulus of the carrierincreases from 1 to 3.5 GPa, the strain in the solder joints alsoincrease. The CTE of the carrier has a less significant effecton the strain values in the solder, compared with that in thecopper wires. The polymer properties that correspond to lowerstrain in copper wires also lead to higher strain in the solderjoints. Interconnection failure is defined by either failure ofcopper wires or that of solder joints, whichever comes first.Therefore, an optimized design is achieved when the fatiguelife of copper wires and solder joints are close to each other,and both exceeds 1000 cycles. The solution was found whenthe modulus of the polymer carrier is 7.5 GPa and the CTEis 20 ppm/°C. The fatigue performance of the interconnectionswith the selected polymer properties is discussed in detailin Section IV.
IV. FINITE-ELEMENT MODELING
RESULTS AND ANALYSIS
The reliability performance of the copper MWA was com-pared with standard BGA interconnections, using responseparameters such as warpage of the silicon interposers, equiv-alent plastic strain in the interconnections and the projectedfatigue life. The same dimensions for the silicon interposer
Fig. 8. Volume averaged strain over the elements sharing the node withlargest nodal strain for fatigue life prediction.
TABLE II
EQUIVALENT PLASTIC STRAIN RANGE AND PROJECTED FATIGUE LIFE
FOR MWA & BGA INTERCONNECTIONS
and board were applied in the BGA model, as shown in Fig. 7.Standard SAC305 solder balls of 250-μm diameter wereused for BGA interconnections at 400-μm pitch. The sameboundary conditions and loading profiles were applied for bothbaseline BGA and MWA models.
At the end of the thermal cycles, the silicon interposersshowed a concave down warpage for both types of inter-connections, since the FR-4 PWB shrank more than thesilicon, as the assembly cooled from reflow temperature toroom temperature. At 20-mm interposer size, the warpagewas 0.16 mm with microwire interconnections, and 0.19 mmwith BGA interconnections. Larger warpage negatively affectsthe integrity of the vias and redistribution layers in theinterposer, as well as of the reliability of the chip-to-interposerinterconnections.
Coffin–Manson models were applied for both copper andsolder to estimate the fatigue performance of the interconnec-tions. Several damage metrics have been previously reportedfor fatigue life prediction, such as accumulated plastic strainper cycle, plastic strain range per cycle, accumulated creepstrain per cycle, strain energy density per cycle, creep strainenergy per cycle among others [14]–[16]. In this paper, theelemental averaged equivalent plastic strain range in eachthermal cycle was chosen as the damage metric. The elementalstrain is the volume average of the strain in the elementsthat share the same node in which the maximum nodal strainoccurs, as illustrated in Fig. 8. Equations (1) and (2) describethe low-cycle fatigue of both SAC305 and copper [17], [18],in which ε f is a material-related constant, with the value of
QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1713
Fig. 9. Strain contours in (a) copper microwire interconnections and (b) BGA interconnections.
0.325 and 0.2249 for solder and copper, respectively. Fig. 9shows the strain contour of both interconnections: in the MWAinterconnection, the deformation is distributed between thecopper wires and the solders, while in the BGA interconnec-tion, the deformation is solely accommodated by the solderjoints. Table II shows the strain range and projected fatiguelife for both interconnections. In the MWA interconnections,the first failure is predicted to be in the solder joint on theinterposer side, with a fatigue life of 1158 cycles, and thecopper wires are predicted to survive more than 1450 cycles.The geometry parameters of the interconnection structure canbe further optimized to balance the strain distribution betweencopper wires and solder joints to achieve lower strain in soldersat the cost of higher strain in copper. The fatigue life of BGAsis predicted to be 719 cycles, which is much lower than thatof the MWA interconnections
N f −solder = 0.5
(2ε f
�γp
) 10.57
(1)
N f −copper =(
ε0.75f
�γp
) 10.6
. (2)
V. TEST VEHICLE DESIGN AND FABRICATION
Silicon interposers (600 μm thick), FR-4 PWBs (800 μmthick), and copper MWAs in polymer carriers were designedand fabricated for assembly and reliability tests. The siliconinterposers have 1 layer of copper traces (10–12-μm thick)built with semiadditive process, and silicon nitride as passi-vation layer. Solder mask defined design was used for thesilicon interposer, where the diameter of copper pad is 344 μmand that of passivation is 225 μm. Electroless nickel andimmersion gold was used as surface finish. The board has1 layer of copper traces patterned by an etch-back method,while solder mask was used for the passivation, and Organicsolderability preservative as the surface finish. Nonsolder maskdefined pads design was used for the board, where the paddiameter is 231 μm, and the passivation opening is 344 μm.The boards and interposers have matched daisy chain designsto test the integrity of the interconnections. The daisy chain isdesigned with 90° rotational symmetry, 5 daisy chains in eachquarter, and 20 daisy chains in each test vehicle.
The key attribute of this innovative SMT technology is theuse of a prefabricated MWA stress-relief insert, illustratedin Fig. 1(a). Syron 7000 films were chosen as the carriermaterial based on the modeling results. It is a thermoplasticsubstrate material, with a modulus of 8.6 GPa and CTE of18 and 23 ppm/°C in the two in-plane directions, which areclose to the guidelines recommended by modeling. To fabri-cate copper wires of high aspect ratio with low-cost packaging-compatible processes, multiple photoresist candidates wereevaluated. A 25-μm-thick dry-film photoresist from HitachiChemical was shown to have the best performance for high-aspect-ratio features. Two layers of photoresist are applied onboth sides of the carrier to achieve 50-μm stand-off height ofthe electroplated wires. The diameter of the wires is designedto be 15 μm for the initial proof-of-concept samples.
The fabrication process flow is shown in Fig. 10. Copper-filled vias were formed in the Syron carrier as the current pathin between the wires on both sides. Continuous copper posts,other than the individual wires as shown in the modeling, wereused in the carrier, for ease of via formation and alignmentof wires onto the posts. CO2 laser was used to process thevias with 225 μm diameter in the Syron film. The viaswere metallized by bottom-up electrolytic plating. Lithographyof microwire pattern was performed on both sides of thecarrier, followed by electrolytic plating to build the copperwires. Copper pads were formed on the top of the wires byoverplating, which help prevent solder wetting along the wiresduring reflow. Eutectic 96.5Sn3.5Ag alloy was coplated on thetop of the copper pads for assembly. SAC305 solder was usedin the modeling, since it is widely used for the board-levelinterconnections, but SAC305 cannot be coplated. The crosssection of the MWA interconnections is shown in Fig. 11.
The process is compatible with standard high-volume SMTassembly, making it a manufacturable and cost-effectiveapproach for reliable board-level interconnections of silicon,glass, and low-CTE organic interposers.
VI. ASSEMBLY AND RELIABILITY CHARACTERIZATION
The assembly was carried out with a semiautomatedflip-chip bonder (Finetech Matrix Fineplacer), with a place-ment accuracy of ±3 μm. A two-step process was developed
1714 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015
Fig. 10. Process flow for fabrication of copper MWA interconnections.
Fig. 11. Cross section of the interconnections before assembly.
to assemble the silicon package to the PWB through MWAinterconnections, as shown in Fig. 12.
The first step is to place the MWAs onto the board[Fig. 12(a)] using a vacuum-locked 20 mm × 20 mm gim-bal tool. The Syron carriers with copper wires and solderbumps plated on both sides had significant warppage. Tackyflux (ALPHA NCX-FD) was applied onto the board to holddown the carrier. ALPHA NCX-FD flux is a no-clean fluxthat does not leave residues, and is compatible with lead-free applications that require higher reflow temperatures.The amount of flux has to be carefully controlled to avoidheavy degassing, which may cause voiding in the solder joints.An external force was also applied to offset the warpage ofthe carrier and the noncoplanarities of the solders. The applied
force was limited to below 5 N to avoid damaging the softsolder caps. The silicon package was then picked up witha 10 mm × 10 mm flat tool head, aligned onto the MWAinterconnections, and pressed on top with a 5 N placementforce. The same flux was also applied on the silicon interposerto remove oxide and promote bonding between the solder andthe pads on the interposer. The joints on both sides weresimultaneously formed during reflow of the solder, with thepeak temperature at 260 °C. The cross section of the assemblyis shown in Fig. 13.
Warpage of the Syron carrier and noncoplanarity of thesolder bumps were identified as major challenges for assemblyyield. The warpage of the Syron carrier is caused by thefollowing.
QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1715
Fig. 12. Two-step assembly process. (a) Placement of the MWA interconnections onto the PWB. (b) Placement of the silicon package, and reflow.
Fig. 13. Cross section of silicon package-MWA-PWB assembly.
1) The low thickness and modulus of the polymer material,which made the stand-alone film prone to deformationduring the fabrication process. The deformation inducedin the polymer film further affected the contact betweenthe polymer and the mask during lithography, and causednon-ideal development and resist residues in certainareas. The adhesion of the plated wires in these areaswas weak, which resulted in wires falling off duringresist stripping and therefore missing interconnections,as shown in Fig. 14.
2) The asymmetry in the structure on both sides of thepolymer film, which is induced by both the missingbumps and unbalanced copper and solder plating.
Noncoplanarities are primarily caused by the nonuniform cur-rent distribution in both copper and solder plating processes.The difference in copper plating rates generated mushroompads of different diameters and thicknesses, which later onaffected the plating rates of solder on these copper pads. Theplating nonuniformity of the solder itself further exaggeratedthe issue. The process control to achieve symmetric structureson both sides of the polymer carrier is the key to mitigatewarpage and to improve the yield of the assembly, whichfurther eliminates premature failures caused by imperfectbonding during the thermal cycling test. Missing solder bumpsis another cause of package distortion and misalignment duringassembly.
Regardless of the defects described above, the daisy chainsyielded well in locations where the polymer carrier wascomparatively flat with uniformly plated solder caps.
Thermal cycling test was used to characterize the reliabilityperformance of the MWA interconnections by tracking the
Fig. 14. Missing interconnections caused by process defects.
resistance of the yielded daisy chains. The temperature rangewas −40 °C–125 °C, with 15-min dwell time at each temper-ature extreme, at a rate of 1 cycle/h, as per JEDEC standard(JESD22-A104D, type G). The resistance of each daisy chainwas measured every 50 cycles.
The daisy chain resistance readings are shown in Fig. 15(a).A dramatic increase in the resistance was detected between700 and 800 cycles. The locations of the failed daisy chainsare shown in Fig. 15(b). The earliest failure was identified inone of the corner daisy chains (#7), while dc #13 and #14 arelonger chains which are located more toward the inner area.The interconnections at the corners have larger distance to the
1716 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015
Fig. 15. (a) Resistance of the daisy chains during thermal cycling test. (b) Location of the failed daisy chains.
Fig. 16. Cross section of failed MWA interconnections.
neutral point compared with the inner ones, and experiencelarger strains during thermal cycling, and are consequentlyexpected to experience earlier failures.
The sample was cross-sectioned for failure analysis, asshown in Fig. 16. The solder joints in Fig. 16 are the edgejoints located in dc #13 [Fig. 15(b)]. The solder on theinterposer side showed fatigue cracks, which propagated along
the diagonal direction. Two reasons may have contributedto the way the cracks propagate. The first one is the warpageof the carrier itself, which pulled the solder joints in the verti-cal direction. The second reason is the imperfect alignmentbetween the solder and the capture pads on the interposer(shown in Fig. 16), which caused necking in the joints andaccelerated crack initiation. The imperfect alignment is mainly
QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1717
Fig. 17. Comparison of the refined model and the original model.
driven by the warpage of the carrier, which made it difficult tofocus and align during assembly. The fatigue failure initiatedfrom the solder joints on the interposer side, which agrees withthe larger strains on the interposer side compared with that onthe board side, as suggested by modeling.
VII. ANALYSIS AND DISCUSSION OF
MODEL-TO-EXPERIMENT CORRELATIONS
The geometry and material parameters typically deviatefrom the design because of processing compromises andmaterial availability. This section analyzes the critical para-meters in the fabricated samples that are different from theoriginal design, and discusses the effect of these parameterson the reliability of interconnections.
A. Change in Geometry Parameters
1) Change in Silicon Thickness: In the original design, thethickness of the silicon interposer is 100 μm, representingthe typical thickness for 2.5-D and 3-D architectures. In thefabricated samples, however, the packages are not thinned andhave a thickness of 600 μm. This larger silicon thicknessincreases the rigidity of the interposer, and results in largerstrains in the interconnections. In the refined model, theinterposer thickness was changed to 600 μm.
2) Change in Carrier Thickness: The polymer carrieris 25 μm thick in the original design, while the commerciallyavailable Syron material has a thickness of 50 μm. Thelarger carrier thickness helped handling of the polymer duringprocessing and the control of warpage and deformation, butrestricted the deformation of the wire arrays and increased thestrain in the solder joints.
3) Change in Wire Diameter: The wires were initiallydesigned to have a 10 μm diameter. However, a mask with15-μm openings was used for lithography to help improvethe yield of the wires. The average wire diameter after seedlayer removal was found to be around 12 μm. Larger wirediameters reduced the aspect ratio of wire array and decreasedthe compliance. Diameter of 12 μm was used in the refinedmodel and the same element size was applied for both models.
B. Change of Solder Material
The solder material used in the original models wasSAC305, as it is one of the most popular lead-free soldersfor reliable board-level interconnections. However, SnAgeutectic solder (96.5Sn3.5Ag) was used in the samplesfor processing convenience. The two solder materials havedifferent viscoplastic behaviors and fatigue performance.The Anand model for 96.5Sn3.5Ag reported byWang et al. [19] was used in the updated model.
The low-cycle fatigue performance of 96.5Sn3.5Ag wasstudied by Kanchanomai et al. [20] in detail. Their ductility-modified Coffin–Manson relationship was used for fatigue lifeprediction of the solder joints, as shown in the followingequation. D is the fracture ductility, which equals to 1.6 for96.5Sn3.5Ag solder. α and θ are material constants, which are1.07 and 13, respectively. The snapshot of the refined modeland how it compares to the original model is shown in Fig. 17(
�εP
2D
)Nα
f = θ. (3)
The same boundary conditions and loading profiles wereapplied in the refined model. The maximum elemental plasticstrain range per cycle was calculated for fatigue life estimation.The calculated strain and fatigue life for both solder jointsand copper is shown in Table III. Due to the combination ofthicker silicon packages and larger wire diameter, the strainsin the interconnections are larger than that shown in the initialdesign. With the refined model, the estimated fatigue life is801 cycles, defined by the failure in the solders.
As discussed previously, fatigue failures were detected inone of the corner daisy chains at 700 cycles. The model wasable to describe the performance of the interconnections well,in spite of other parameters such as misalignment, intermetalliccompounds, and solder voids that were not considered in themodels but are expected to degrade the fatigue life. The modelsare therefore validated by the experiment. The major factorthat led to the decrease in fatigue life is the thick silicon. Withthinner packages, such as the ones used in today’s 2.5-D and3-D architectures, the MWA interconnections are expected tosurvive more than 1000 cycles in accelerated test for packagesizes up to 20 mm × 20 mm.
VIII. CONCLUSION
The trend toward high I/O density, ultraminiaturization andhigh performance has heralded a new era of low-CTE silicon,glass and organic interposers. However, the CTE mismatchbetween these interposers and PWBs creates new majorreliability concerns at board-level interconnections. A newset of interconnection technologies that are SMT-compatibleand manufacturable are, therefore, required. In this paper, aninnovative compliant copper MWA concept was explored tomeet this need.
The FEM was used to analyze the reliability performance ofthe copper microwire interconnections to provide guidelinesfor design of the MWA structure. The warpage, equivalentplastic strain, and projected fatigue life were compared withstandard BGA interconnections. At the same interposer sizeand interconnection pitch, the copper MWAs showed lower
1718 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015
TABLE III
MWA FATIGUE LIFE CALCULATION WITH THE REFINED MODEL
warpage, lower plastic strain, as well as longer fatigue lifethan standard BGA interconnections.
A low-cost approach was used to fabricate the coppermicrowire interconnections using standard photolithographyand plating processes. A two-step assembly process wasdeveloped to assemble 20 mm×20 mm silicon interposers ontoFR-4 PWBs with MWA interconnections. The reliability per-formance was assessed by thermal cycling tests from −40 °Cto 125 °C. Initial fatigue failures were identified at one of thecorner daisy chains at 700 cycles. The finite-element modelswere further refined based on the geometry and materialparameters used in the fabricated samples. Good correlationbetween modeling and experimental data was achieved withthe refined models. The models were therefore validated byreliability characterization. With thin low-CTE interposers orpackages, the compliant MWA interconnections are expectedto survive more than 1000 cycles, as predicted by the models.The MWA concept is thus demonstrated as a highly reliableand SMT-compatible interconnection solution for direct attachof large low-CTE interposers.
ACKNOWLEDGMENT
The authors would like to thank the industry mentorsDr. U. Ray and Dr. J. Lee from Qualcomm for their activeguidance, suggestions, and support of this work. They wouldalso like to thank Rogers Corporation for providing polyimidematerials and Atotech Germany for their support with solderalloy plating.
REFERENCES
[1] R. R. Tummala et al., “Trend from ICs to 3D ICs to 3D systems,” inProc. IEEE Custom Integr. Circuits Conf., Sep. 2009, pp. 439–444.
[2] M. Miyatake et al., “Newly developed ultra low CTE materials forthin core PKG,” in Proc. IEEE 62nd Electron. Compon. Technol.Conf. (ECTC), May/Jun. 2012, pp. 1588–1592.
[3] J. U. Knickerbocker et al., “An advanced multichip module (MCM) forhigh-performance UNIX servers,” IBM J. Res. Develop., vol. 46, no. 6,pp. 779–804, Nov. 2002.
[4] T. H. DiStefano, J. W. Smith, Z. Kovac, and K. Karavakis, “Compliantmicroelectronic mounting device,” U.S. Patent 5 706 174, Jan. 6, 1998.
[5] Q. Zhu, L. Ma, and S. K. Sitaraman, “Compliant off-chip interconnects,”U.S. Patent 6 784 378, Aug. 31, 2004.
[6] I. Shubin et al., “A package demonstration with solder free compli-ant flexible interconnects,” in Proc. 60th Electron. Compon. Technol.Conf. (ECTC), Jun. 2010, pp. 1429–1435.
[7] T. Wang, F. Tung, L. Foo, and V. Dutta, “Studies on a novel flip-chipinterconnect structure—Pillar bump,” in Proc. 51st Electron. Compon.Technol. Conf., May/Jun. 2001, pp. 945–949.
[8] V. S. Rao, A. A. O. Tay, V. Kripesh, C. T. Lim, and S. W. Yoon, “Bed ofnails—100 microns pitch wafer level interconnections process,” in Proc.6th Electron. Packag. Technol. Conf. (EPTC), Dec. 2004, pp. 444–449.
[9] X. Qin, N. Kumbhat, V. Sundaram, and R. Tummala, “Highly-reliablesilicon and glass interposers-to-printed wiring board SMT intercon-nections: Modeling, design, fabrication and reliability,” in Proc. IEEE62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012,pp. 1738–1745.
[10] M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Seaof leads ultra high-density compliant wafer-level packaging technology,”in Proc. 52nd Electron. Compon. Technol. Conf., 2002, pp. 1087–1094.
[11] M. Topper et al., “Wafer level package using double balls,” in Proc.Int. Symp. Adv. Packag. Mater., Process., Properties Interf., Mar. 2000,pp. 198–200.
[12] R. Dudek et al., “Thermomechanical design for reliability of WLPswith compliant interconnects,” in Proc. 7th Electron. Packag. Technol.Conf. (EPTC), vol. 1. Dec. 2005, pp. 1–7.
[13] M. Motalab et al., “Determination of Anand constants for SAC soldersusing stressstrain or creep data,” in Proc. 13th IEEE Intersoc. Conf. IEEEThermal Thermomech. Phenomena Electron. Syst. (ITherm), 2012.
[14] J. Pang, B. S. Xiong, and T. H. Low, “Comprehensive mechanicscharacterization of leadfree 95.5 Sn–3.8 Ag–0.7 Cu solder,” Micromater.Nanomater., vol. 3, pp. 86–93, 2004.
[15] A. Schubert, R. Dudek, E. Auerswald, A. Gollbardt, B. Michel, andH. Reichl, “Fatigue life models for SnAgCu and SnPb solder jointsevaluated by experiments and simulation,” in Proc. 53rd Electron.Compon. Technol. Conf., May 2003, pp. 603–610.
[16] J. H. Lau, D. Shangguan, D. C. Y. Lau, T. T. W. Kung, and S. W. R. Lee,“Thermal-fatigue life prediction equation for wafer-level chip scalepackage (WLCSP) lead-free solder joints on lead-free printed circuitboard (PCB),” in Proc. 54th Electron. Compon. Technol. Conf., vol. 2.Jun. 2004, pp. 1563–1569.
[17] D. Shangguan, Lead Free Solder Interconnect Reliability. Materials Park,OH, USA: ASM International, 2005.
[18] R. Iannuzzelli, “Predicting plated-through-hole reliability in high tem-perature manufacturing processes,” in Proc. 41st Electron. Compon.Technol. Conf., May 1991, pp. 410–421.
[19] G. Z. Wang, Z. N. Cheng, K. Becker, and J. Wilde, “Applying Anandmodel to represent the viscoplastic deformation behavior of solderalloys,” J. Electron. Packag., vol. 123, no. 3, pp. 247–253, 2001.
[20] C. Kanchanomai, Y. Miyashita, and Y. Mutoh, “Low-cycle fatiguebehavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi lead-free solders,”J. Electron. Mater., vol. 31, no. 5, pp. 456–465, May 2002.
QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1719
Xian Qin received the B.S. degree in electrical engi-neering from Tsinghua University, Beijing, China,and the Ph.D. degree in materials science and engi-neering from the Georgia Institute of Technology,Atlanta, GA, USA, in 2015.
She focused primarily on reliability of board-levelinterconnections with the 3-D Systems PackagingResearch Center, Georgia Institute of Technology,during her thesis research. She is involved in mod-eling, design, fabrication, and reliability characteri-zation of compliant interconnections.
Pulugurtha Markondeya Raj received the B.S.degree from IIT Kanpur, Kanpur, India, in 1993, theM.S. degree from the Indian Institute of Science,Bangalore, India, in 1995, and the Ph.D. degree inceramic engineering from Rutgers University, NewBrunswick, NJ, USA, in 1999.
He co-developed several technologies, whichinclude low-cost capacitor and inductor integra-tion, advanced thin film precision analog andRF components with nanomagnetic and nanocom-posite dielectrics, and their package integration as
functional modules. He is currently a Research Professor and ProgramManager for the Power and RF Functional Components and Modules Programwith the 3-D Systems Packaging Research Center (PRC), Georgia Instituteof Technology, Atlanta, GA, USA. At PRC, he provides leadership in theareas of power-supply component integration on silicon, glass, and organicsubstrates for power conversion and integrity, RF and precision components(antennas, diplexers, matching networks, and nonlinear devices), and fine-pitch interconnections. He has co-authored 215 publications, eight books, andeight patents with others pending.
Dr. Raj received 15 best paper awards for his conference and journal publi-cations that include the Distinguished Scholar Award from the MicrobeamAnalysis Society, the IEEE TRANSACTIONS ON ADVANCED PACKAGING
Commendable Paper Award, the IEEE Outstanding Technical Paper Award,the IEEE ECTC Best-Poster Award, and the Philips Best Paper Award.He is the Co-Chair of the IEEE CPMT Nanopackaging Technical Committee,and the Track Chair of Nanopackaging at the IEEE NANO Conference.He is also the Co-Chair and served as the Session Chair of the High-Speed, Wireless and Components thrust in the Components, Packaging andManufacturing Technology Conference and the Electronics and ComponentTechnology Conference.
Vanessa Smet received the B.S. degree in appliedphysics from the École Normale Supérieure deCachan, Cachan, France, the M.S. degree in appliedphysics from the University of Paris XI, Orsay,France, and the Ph.D. degree in electrical engi-neering with a minor in reliability assessment ofpower modules from the University of Montpellier 2,Montpellier, France.
She was a Post-Doctoral Researcher with theTyndall National Institute, Cork, Ireland, where shewas involved in novel high-temperature high-power
die-attachment solutions for power chips and µBGA assembly. She is currentlya Research Scientist and Program Manager for the Interconnections andAssembly Program with the 3-D Systems Packaging Research Center, whereshe focuses on ultrafine pitch first-level interconnections and microelectro-mechanical systems (MEMS) packaging. Her current research interests includepower electronics, thermomechanical modeling, 3-D integration, intercon-nections, assembly processes (flip-chip, thermocompression, and SLID), andMEMS packaging.
Rao Tummala was the Director of Packagingwith IBM, Armonk, NY, USA. He is currently theJoseph M. Pettit Chair Professor and Director of the3-D Systems Research Center with the School ofElectrical and Computer Engineering and MaterialsScience and Engineering, Georgia Institute of Tech-nology, Atlanta, GA, USA. He is also the FoundingDirector of the first National Science FoundationEngineering Research Center in the U.S. He is aWorld Renowned Packaging Expert and has devel-oped several major technologies from concept to
manufacturing, including the industry’s first 100-chip ceramic modules, firstplasma display, and thin film magnetic storage devices for which contributionshe was named an IBM Fellow.
